DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 01/20/2026, in which claims 1, 12, 21, 29 were amended, claims 2, 8, 10-11, 16, 18-20, 22 were cancelled, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 9, 21, 23-27, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20130077376) in view of Chen et al. (US Pub. 20140098591), hereafter Chen591, and Chen et al. (US Pub. 20220028899), hereafter Chen899 and Lilak et al. (US Pub. 20210296315).
Regarding claim 1, Kim et al. discloses in Figs. 9-11, paragraph [0007], [0018]-[0019], [0051]-[0066] a semiconductor device, comprising:
a first programming transistor [M12 or M22];
a second programming transistor [M15 or M25];
a first reading transistor [M13 or M23] coupled to the first programming transistor [M12 or M22] in series and to a bit line [BL and BLb];
a second reading transistor [M16 or M26] coupled to the second programming transistor [M15 or M25] in series and to the bit line [BL and BLb];
a conduction path configured to form in response to the first programming transistor [M12 or M22] broken down, the conduction path between a gate terminal of the first programming transistor [M12 or M22] and the bit line [BL and BLb][paragraph [0055], [0062]];
wherein a first gate structure [G12 or G22] of the first programming transistor [M12 or M22] is coupled to a word line [WLP],
wherein the first reading transistor [M13 or M23] and the first programming transistor [M12 or M22] share a common source/drain structure.
Notes, the limitation of “programming transistor”, “reading transistor”, and “a conduction path configured to form in response to the first programming transistor broken down, the conduction path between a gate terminal of the first programming transistor and the bit line” direct to intended operation of the device. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 (II). Besides, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
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Kim et al. fails to disclose
a plurality of first nanostructures of the first programming transistor disposed on a substrate and extending along a first lateral direction;
a plurality of second nanostructures of the second programming transistor, disposed on the substrate and extending along the first lateral direction, the second programming transistor being separated from the first programming transistor along a second lateral direction perpendicular to the first lateral direction;
a dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures, the first sidewall facing the second lateral direction;
the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls;
a second gate structure of the second programming transistor straddling the plurality of second nanostructures; and
wherein the dielectric fin structure laterally and completely separates the plurality of first nanostructures and the first gate structure of the first programming transistor from the plurality of second nanostructures and the second gate structure of the second programming transistor along the second lateral direction, respectively;
the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure;
Chen591 discloses in Fig. 1A, paragraph [0042]-[0043]
an active region [region of 118 overlapped with gate 114] of the first programming transistor [transistor having gate 114], extending along a first lateral direction;
an active region [region of 118 overlapped with gate 112] of the second programming transistor [transistor having gate 112], extending along the first lateral direction, the second programming transistor [transistor having gate 112] being separated from the first programming transistor [transistor having gate 114] along a second lateral direction perpendicular to the first lateral direction;
a dielectric fin structure [116] extending along the first lateral direction;
wherein the dielectric fin structure [116] laterally and completely separates the first gate structure [114] of the first programming transistor from the second gate structure [112] of the second programming transistor along the second lateral direction, respectively;
the second gate structure [112] of the second programming transistor is isolated from the first gate structure [114] of the first programming transistor by the dielectric fin structure [116];
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen591 into the method of Kim et al. to include an active region of the first programming transistor, extending along a first lateral direction; an active region of the second programming transistor, extending along the first lateral direction, the second programming transistor being separated from the first programming transistor along a second lateral direction perpendicular to the first lateral direction; a dielectric fin structure extending along the first lateral direction; wherein the dielectric fin structure laterally and completely separates the first gate structure of the first programming transistor from the second gate structure of the second programming transistor along the second lateral direction, respectively; the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing layout structure of an antifuse one-time programmable (OTP) memory cell with performance improvement that can prevent yield loss caused by a rupture location of an antifuse layer being in a location where an antifuse gate and a substrate are in direct contact [paragraph [0008], [0042]-[0043] of Chen591].
Chen 591 and Kim et al. fails to disclose
the active region of the first programming transistor comprising a plurality of first nanostructures disposed on a substrate and extending along the first lateral direction;
the active region of the second programming transistor comprising a plurality of second nanostructures disposed on the substrate and extending along the first lateral direction
the dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures along the second lateral direction;
the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and
the second gate structure of the second programming transistor straddling the plurality of second nanostructures;
wherein the dielectric fin structure laterally and completely separates the plurality of first nanostructures and the first gate structure of the first transistor from the plurality of second nanostructures and the second gate structure of the second transistor along the second lateral direction, respectively.
Chen899 discloses in Fig. 9, paragraph [0087]-[0115] a semiconductor device, comprising:
the active region of the first transistor comprising a plurality of first nanostructures [201] of a first transistor disposed on a substrate and extending along a first lateral direction [out of plane direction];
the active region of the second transistor comprising a plurality of second nanostructures [203] disposed on the substrate and extending along the first lateral direction [out of plane direction];
the dielectric fin structure [213] extending along the first lateral direction [out of plane direction] and disposed immediately next to a first sidewall of each of the plurality of first nanostructures [201] along the second lateral direction [horizontal direction];
the first gate structure [223] of the first transistor wrapping around each of the plurality of first nanostructures [201] except for the first sidewalls; and
the second gate structure [224] of the second transistor straddling the plurality of second nanostructures [203];
wherein the dielectric fin structure [213] laterally and completely separates the plurality of first nanostructures [201] and the first gate structure [223] of the first transistor from the plurality of second nanostructures [203] and the second gate structure [224] of the second transistor along the second lateral direction [horizontal direction], respectively.
Chen899 also discloses in Fig. 9
the second gate structure [224] of the second transistor is isolated from the first gate structure [223] of the first transistor by the dielectric fin structure [213].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen899 into the method of Chen 591 and Kim et al. to include the active region of the first programming transistor comprising a plurality of first nanostructures, extending along the first lateral direction; the active region of the second programming transistor comprising a plurality of second nanostructures, extending along the first lateral direction the dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures along the second lateral direction; the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and the second gate structure of the second programming transistor straddling the plurality of second nanostructures; wherein the dielectric fin structure laterally and completely separates the plurality of first nanostructures and the first gate structure of the first transistor from the plurality of second nanostructures and the second gate structure of the second transistor along the second lateral direction, respectively. The ordinary artisan would have been motivated to modify Chen 591 and Kim et al. in the above manner for the purpose of providing a fork nanosheet (forksheet) device having a GAA feature to provide an excellent channel control capability, to optimize effective drive current per unit are, and to provide better scalability of area and performance [paragraph [0003]-[0005], [0027]-[0028] of Chen899].
Kim fails to disclose
wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure.
Kim discloses in Fig. 9-11
wherein the first reading transistor [M13 or M23] and the first programming transistor [M12 or M22] share a common source/drain structure.
Chen591 discloses in Fig. 1A
wherein the first programming transistor and the first reading transistor share a common semiconductor source/drain structure [118].
Lilak et al. discloses in Fig. 8C
a source/drain structure [805] of a transistor vertically extending from the substrate [801] to a top surface of a gate structure [813].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lilak et al. and Chen591 into the method of Kim to include wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure. The ordinary artisan would have been motivated to modify Kim in the above manner for the purpose of providing suitable configuration of a source/drain structure [paragraph [0079] of Lilak et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 3-6, Chen 591 discloses
wherein the first [114] and second [112] gate structures each extend along the second lateral direction.
Chen899 further discloses in Fig. 9, paragraph [0087]-[0115]
wherein the first [223] and second [224] gate structures each extend along the second lateral direction [horizontal direction];
wherein the dielectric fin structure [213] is also disposed immediately next to a second sidewall of each of the plurality of second nanostructures [203], the second sidewall facing the second lateral direction [horizontal direction];
wherein the second gate structure [224] wraps around each of the plurality of second nanostructures [203] except for the second sidewalls;
wherein the second gate structure [224] wraps around each of the plurality of second nanostructures [203];
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen899 and Chen 591into the method of Kim et al. to include the first and second gate structures each extend along the second lateral direction; wherein the dielectric fin structure is also disposed immediately next to a second sidewall of each of the plurality of second nanostructures, the second sidewall facing the second lateral direction; wherein the second gate structure wraps around each of the plurality of second nanostructures except for the second sidewalls; wherein the second gate structure wraps around each of the plurality of second nanostructures. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing a fork nanosheet (forksheet) device having a GAA feature to provide an excellent channel control capability, to optimize effective drive current per unit are, and to provide better scalability of area and performance [paragraph [0003]-[0005], [0027]-[0028] of Chen899].
Regarding claims 7, 9, 24-27, Kim et al. fails to disclose
a plurality of third nanostructures of the first reading transistor, extending along the first lateral direction;
a third gate structure of the first reading transistor, straddling the plurality of third nanostructures;
wherein the plurality of third nanostructures and the third gate structure form, in part, the first reading transistor of an anti-fuse memory cell;
a plurality of fourth nanostructures of the second reading transistor, extending along the first lateral direction;
wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction;
a fourth gate structure straddling the plurality of fourth nanostructures, wherein the plurality of fourth nanostructures and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell.
Chen591 discloses in Fig. 1A, paragraph [0042]-[0043]
an active region [region of 118 overlapped with gate 110] of the first reading transistor [transistor having a portion of gate 110], extending along the first lateral direction;
a third gate structure [a portion of 110] of the first reading transistor [transistor having a portion of gate 110] straddling the active region [region of 118 overlapped with gate 110] of the first reading transistor [transistor having a portion of gate 110];
wherein the active region [region of 118 overlapped with gate 110] of the first reading transistor [transistor having a portion of gate 110] and the third gate structure [110] form, in part, the first reading transistor of an anti-fuse memory cell;
an active region [region of 118 overlapped with gate 110] of the second reading transistor [transistor having another portion of gate 110], extending along the first lateral direction;
a fourth gate structure [another portion of 110] straddling the active region [region of 118 overlapped with gate 110] of the second reading transistor [transistor having another portion of gate 110],
wherein the active region [region of 118 overlapped with gate 110] of the second reading transistor [transistor having another portion of gate 110] and the fourth gate structure [another portion of 110] form, in part, the second reading transistor of the anti-fuse memory cell.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen591 into the method of Kim et al. to include an active region of the first reading transistor, extending along the first lateral direction; a third gate structure of the first reading transistor straddling the active region of the first reading transistor; wherein the active region of the first reading transistor and the third gate structure form, in part, the first reading transistor of an anti-fuse memory cell; an active region of the second reading transistor, extending along the first lateral direction; a fourth gate structure straddling the active region of the second reading transistor, wherein the active region of the second reading transistor and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing layout structure of an antifuse one-time programmable (OTP) memory cell with performance improvement that can prevent yield loss caused by a rupture location of an antifuse layer being in a location where an antifuse gate and a substrate are in direct contact [paragraph [0008], [0042]-[0043] of Chen591].
Chen 591 and Kim et al. fails to disclose
the active region of the first reading transistor comprising a plurality of third nanostructures, extending along the first lateral direction;
the third gate structure of the first reading transistor, straddling the plurality of third nanostructures;
the active region of the second reading transistor comprising a plurality of fourth nanostructures, extending along the first lateral direction;
wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction;
the fourth gate structure of the second reading transistor, straddling the plurality of fourth nanostructures.
Chen899 discloses in Fig. 9, paragraph [0087]-[0115]
the active region of the third transistor comprising a plurality of third nanostructures [206] extending along the first lateral direction [out of plane direction];
the third gate structure [225] straddling the plurality of third nanostructures [206];
the active region of the fourth transistor comprising a plurality of fourth nanostructures [208] extending along the first lateral direction [out of plane direction];
wherein the plurality of fourth nanostructures [208] extend along the first lateral direction [out of plane direction] and separated from the plurality of third nanostructures [206] along the second lateral direction [horizontal direction];
the fourth gate [226] straddling the plurality of fourth nanostructures [208].
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Incorporating GAA structure disclosed by Chen899 to formed the first and second reading transistors of the anti- fuse memory cell suggested by Chen 591 and Kim et al. would result to the limitation of “wherein the plurality of third nanostructures and the third gate structure form, in part, the first reading transistor of the anti- fuse memory cell” and “wherein the plurality of fourth nanostructures and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen899 into the method of Chen 591 and Kim et al. to include the active region of the first reading transistor comprising a plurality of third nanostructures, extending along the first lateral direction; the third gate structure of the first reading transistor, straddling the plurality of third nanostructures; wherein the plurality of third nanostructures and the third gate structure form, in part, the first reading transistor of the anti- fuse memory cell; the active region of the second reading transistor comprising a plurality of fourth nanostructures, extending along the first lateral direction; wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction; the fourth gate structure of the second reading transistor, straddling the plurality of fourth nanostructures, wherein the plurality of fourth nanostructures and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell. The ordinary artisan would have been motivated to modify Chen 591 and Kim et al. in the above manner for the purpose of providing an antifuse one-time programmable (OTP) memory cell including fork nanosheet (forksheet) device with performance improvement that provide an excellent channel control capability, that optimize effective drive current per unit are, that provide better scalability of area [paragraph [0003]-[0005], [0027]-[0028] of Chen899].
Regarding claims 21 and 23, Kim et al. discloses in Figs. 10-11, paragraph [0007], [0018]-[0019], [0051]-[0066] a semiconductor device, comprising:
a first programming transistor [M12 or M22];
a second programming transistor [M15 or M25];
a first reading transistor [M13 or M23] configured to couple between the first programming transistor [M12 or M22] in series and to a bit line [BL and BLb];
a second reading transistor [M16 or M26] configured to couple between the second programming transistor [M15 or M25] in series and to the bit line [BL and BLb];
a conduction path configured to form in response to a programming voltage applied to the first programming transistor [M12 or M22] broken down, the conduction path between a gate terminal of the first programming transistor [M12 or M22] and the bit line [BL and BLb][paragraph [0055], [0062]];
a word line [WLP] is coupled to a first gate structure [G12 or G22] of the first programming transistor [M12 or M22].
Notes, the limitation of “programming transistor” and “a conduction path configured to form in response to the first programming transistor broken down, the conduction path between a gate terminal of the first programming transistor and the bit line” direct to intended operation of the device. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 (II). Besides, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
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Kim et al. fails to disclose
a plurality of first nanostructures of the first programming transistor, extending along a first lateral direction;
a dielectric fin structure disposed immediately next to a first sidewall of each of the plurality of first nanostructures, wherein the first sidewall faces a second lateral direction perpendicular to the first lateral direction;
a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls;
a plurality of second nanostructures of the second programming transistor, extending along the first lateral direction;
a second gate structure straddling the plurality of second nanostructures;
wherein the dielectric fin structure laterally and completely separates the first nanostructures from the second nanostructures, and also laterally and completely separates the first gate structure from the second gate structure along the second lateral direction;
wherein the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure;
wherein the dielectric fin structure is also disposed immediately next to a second sidewall of each of the plurality of second nanostructures, wherein the second sidewall faces the second lateral direction.
Chen591 discloses in Fig. 1A, paragraph [0042]-[0043]
an active region [region of 118 overlapped with gate 114] of the first programming transistor [transistor having gate 114], extending along a first lateral direction;
a dielectric fin structure [116];
an active region [region of 118 overlapped with gate 112] of the second programming transistor [transistor having gate 112], extending along the first lateral direction;
wherein the dielectric fin structure [116] laterally and completely separates the first gate structure [114] from the second gate structure [112] along the second lateral direction, respectively;
wherein the second gate structure [112] of the second programming transistor is isolated from the first gate structure [114] of the first programming transistor by the dielectric fin structure [116].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen591 into the method of Kim et al. to include an active region of the first programming transistor, extending along a first lateral direction; a dielectric fin structure; an active region of the second programming transistor, extending along the first lateral direction; wherein the dielectric fin structure laterally and completely separates the first gate structure from the second gate structure along the second lateral direction, respectively; wherein the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing layout structure of an antifuse one-time programmable (OTP) memory cell with performance improvement that can prevent yield loss caused by a rupture location of an antifuse layer being in a location where an antifuse gate and a substrate are in direct contact [paragraph [0008], [0042]-[0043] of Chen591].
Chen 591 and Kim et al. fails to disclose
the active region of the first programming transistor comprising a plurality of first nanostructures disposed on a substrate, extending along the first lateral direction;
the dielectric fin structure disposed immediately next to a first sidewall of each of the plurality of first nanostructures, wherein the first sidewall faces a second lateral direction perpendicular to the first lateral direction;
the first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls;
the active region of the second programming transistor comprising a plurality of second nanostructures disposed on the substrate, extending along the first lateral direction
the dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures along the second lateral direction;
the second gate structure straddling the plurality of second nanostructures;
the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and
the second gate structure of the second programming transistor straddling the plurality of second nanostructures;
wherein the dielectric fin structure laterally and completely separates the first nanostructures from the second nanostructures;
wherein the dielectric fin structure is also disposed immediately next to a second sidewall of each of the plurality of second nanostructures, wherein the second sidewall faces the second lateral direction.
Chen899 discloses in Fig. 9, paragraph [0087]-[0115] a semiconductor device, comprising:
an active region of a first transistor comprising a plurality of first nanostructures [201] disposed on a substrate and extending along a first lateral direction [out of plane direction];
the dielectric fin structure [213] disposed immediately next to a first sidewall of each of the plurality of first nanostructures [201] along a second lateral direction [horizontal direction] perpendicular to the first lateral direction [out of plane direction];
the first gate structure [223] wrapping around each of the plurality of first nanostructures [201] except for the first sidewalls;
an active region of a second transistor comprising a plurality of second nanostructures [203] disposed on the substrate and extending along the first lateral direction [out of plane direction];
the second gate structure [224] straddling the plurality of second nanostructures [203];
wherein the dielectric fin structure [213] laterally and completely separates the first nanostructures [201] from the second nanostructures [203], and also laterally and completely separates the first gate structure [223] from the second gate structure [224] along the second lateral direction [horizontal direction];
wherein the dielectric fin structure [213] is also disposed immediately next to a second sidewall of each of the plurality of second nanostructures [203], wherein the second sidewall faces along the second lateral direction [horizontal direction].
Chen899 also discloses in Fig. 9
the second gate structure [224] of the second transistor is isolated from the first gate structure [223] of the first transistor by the dielectric fin structure [213].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen899 into the method of Chen 591 and Kim et al. to include the active region of the first programming transistor comprising a plurality of first nanostructures, extending along the first lateral direction; the dielectric fin structure disposed immediately next to a first sidewall of each of the plurality of first nanostructures, wherein the first sidewall faces a second lateral direction perpendicular to the first lateral direction; the first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls; the active region of the second programming transistor comprising a plurality of second nanostructures, extending along the first lateral direction; the dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures along the second lateral direction; the second gate structure straddling the plurality of second nanostructures; the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and the second gate structure of the second programming transistor straddling the plurality of second nanostructures; wherein the dielectric fin structure laterally and completely separates the first nanostructures from the second nanostructures; wherein the dielectric fin structure is also disposed immediately next to a second sidewall of each of the plurality of second nanostructures, wherein the second sidewall faces the second lateral direction. The ordinary artisan would have been motivated to modify Chen 591 and Kim et al. in the above manner for the purpose of providing layout structure of an antifuse one-time programmable (OTP) memory cell including fork nanosheet (forksheet) device with performance improvement that provide an excellent channel control capability, that optimize effective drive current per unit are, that provide better scalability of area [paragraph [0003]-[0005], [0027]-[0028] of Chen899].
Kim fails to disclose
wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure.
Kim discloses in Fig. 9-11
wherein the first reading transistor [M13 or M23] and the first programming transistor [M12 or M22] share a common source/drain structure.
Chen591 discloses in Fig. 1A
wherein the first programming transistor and the first reading transistor share a common semiconductor source/drain structure [118].
Lilak et al. discloses in Fig. 8C
a source/drain structure [805] of a transistor vertically extending from the substrate [801] to a top surface of a gate structure [813].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lilak et al. and Chen591 into the method of Kim to include wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure. The ordinary artisan would have been motivated to modify Kim in the above manner for the purpose of providing suitable configuration of a source/drain structure [paragraph [0079] of Lilak et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 29, Kim discloses in Figs. 9-11
wherein the common source/drain structure is a first source/drain structure of the first reading transistor [M13 or M23], and the first reading transistor [M13 or M23] includes a second source/drain structure coupled to the bit line.
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Chen591 discloses in Fig. 1A
a first source/drain structure of the first reading transistor is a first semiconductor source/drain structure of the first reading transistor [M13 or M23], and a second source/drain structure of the first reading transistor is a second semiconductor source/drain structure.
Thus, the combination of Kim and Chen591 discloses
wherein the common source/drain structure is a first epitaxial source/drain structure of the first reading transistor, and the first reading transistor includes a second epitaxial source/drain structure coupled to the bit line.
[Notes, the term “epitaxial” directs to process for forming a first and second semiconductor source/drain structures. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Furthermore, "[b]ecause validity is determined based on the requirements of patentability, a patent is invalid if a product made by the process recited in a product-by-process claim is anticipated by or obvious from prior art products, even if those prior art products are made by different processes." Amgen Inc. v. F. Hoffman-La Roche Ltd., 580 F.3d 1340, 1370 n 14, 92 USPQ2d 1289, 1312, n 14 (Fed. Cir. 2009). (MPEP 2113).” Further, per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).]
Claims 1, 7, 9, 24-29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20130077376) in view of Hsiao et al. (US Pub. 20190221653), Chen et al. (US Pub. 20220028899), hereafter Chen899, Weckx et al. (“Novel forksheet device architecture as ultimate logic scaling device towards 2nm”, IEEE 2019) and Lilak et al. (US Pub. 20210296315).
Regarding claim 1, Kim et al. discloses in Figs. 8-11, paragraph [0007], [0018]-[0019], [0051]-[0066] a semiconductor device, comprising:
a first programming transistor [M12 or M22];
a second programming transistor [M15 or M25];
a first reading transistor [M13 or M23] coupled to the first programming transistor [M12 or M22] in series and to a bit line [BL and BLb];
a second reading transistor [M16 or M26] coupled to the second programming transistor [M15 or M25] in series and to the bit line [BL and BLb];
a conduction path configured to form in response to the first programming transistor [M12 or M22] broken down, the conduction path between a gate terminal of the first programming transistor [M12 or M22] and the bit line [BL and BLb][paragraph [0055], [0062]];
wherein a first gate structure [G12 or G22] of the first programming transistor [M12 or M22] is coupled to a word line [WLP].
Notes, the limitation of “programming transistor”, “reading transistor”, and “a conduction path configured to form in response to the first programming transistor broken down, the conduction path between a gate terminal of the first programming transistor and the bit line” direct to intended operation of the device. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 (II). Besides, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
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Kim et al. fails to disclose
a plurality of first nanostructures of the first programming transistor, extending along a first lateral direction;
a plurality of second nanostructures of the second programming transistor, extending along the first lateral direction, the second programming transistor being separated from the first programming transistor along a second lateral direction perpendicular to the first lateral direction;
a dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures, the first sidewall facing the second lateral direction;
a first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls;
a second gate structure of the second programming transistor straddling the plurality of second nanostructures; and
wherein the dielectric fin structure laterally and completely separates the plurality of first nanostructures and the first gate structure of the first programming transistor from the plurality of second nanostructures and the second gate structure of the second programming transistor along the second lateral direction, respectively;
the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure.
Hsiao et al. discloses in Fig. 2C, Fig. 2F
an active region [101A] of the first programming transistor [transistor having gate 133A], extending along a first lateral direction;
an active region [101B] of the second programming transistor [transistor having gate 133B], extending along the first lateral direction, the second programming transistor [transistor having gate 133B] being separated from the first programming transistor [transistor having gate 133A] along a second lateral direction perpendicular to the first lateral direction;
a dielectric fin structure [134’] extending along the first lateral direction;
a first gate structure [133A] of the first programming transistor;
a second gate structure [133B] of the second programming transistor; and
wherein the dielectric fin structure [134’] laterally and completely separates the first gate structure [133A] of the first programming transistor from the second gate structure [133B] of the second programming transistor along the second lateral direction, respectively;
the second gate structure [133B] of the second programming transistor is isolated from the first gate structure [133A] of the first programming transistor by the dielectric fin structure [134’].
Notes, per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).]
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Hsiao et al. into the method of Kim et al. to include an active region of the first programming transistor, extending along a first lateral direction; an active region of the second programming transistor, extending along the first lateral direction, the second programming transistor being separated from the first programming transistor along a second lateral direction perpendicular to the first lateral direction; a dielectric fin structure extending along the first lateral direction; a first gate structure of the first programming transistor; a second gate structure of the second programming transistor; and wherein the dielectric fin structure laterally and completely separates the first gate structure of the first programming transistor from the second gate structure of the second programming transistor along the second lateral direction, respectively; the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable layout structure of transistors to form reliable semiconductor devices at smaller and smaller sizes and having improved carrier mobility [paragraph [0004], [0088], [0095] and [0111] of Hsiao et al.].
Hsiao et al. and Kim et al. fails to disclose
the active region of the first programming transistor comprising a plurality of first nanostructures disposed on a substrate and extending along the first lateral direction;
the active region of the second programming transistor comprising a plurality of second nanostructures disposed on the substrate and extending along the first lateral direction
the dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures along the second lateral direction;
the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and
the second gate structure of the second programming transistor straddling the plurality of second nanostructures;
wherein the dielectric fin structure laterally and completely separates the plurality of first nanostructures and the first gate structure of the first transistor from the plurality of second nanostructures and the second gate structure of the second transistor along the second lateral direction, respectively.
Chen899 discloses in Fig. 9, paragraph [0087]-[0115]
the active region of the first transistor comprising a plurality of first nanostructures [201] disposed on a substrate and extending along a first lateral direction [out of plane direction];
the active region of the second transistor comprising a plurality of second nanostructures [203] disposed on the substrate and extending along the first lateral direction [out of plane direction];
the dielectric fin structure [213] extending along the first lateral direction [out of plane direction] and disposed immediately next to a first sidewall of each of the plurality of first nanostructures [201] along the second lateral direction [horizontal direction];
the first gate structure [223] of the first transistor wrapping around each of the plurality of first nanostructures [201] except for the first sidewalls; and
the second gate structure [224] of the second transistor straddling the plurality of second nanostructures [203];
wherein the dielectric fin structure [213] laterally and completely separates the plurality of first nanostructures [201] and the first gate structure [223] of the first transistor from the plurality of second nanostructures [203] and the second gate structure [224] of the second transistor along the second lateral direction [horizontal direction], respectively.
Chen899 also discloses in Fig. 9
the second gate structure [224] of the second transistor is isolated from the first gate structure [223] of the first transistor by the dielectric fin structure [213].
For further providing support for a known configuration of forksheet transistor, Weckx et al. is cited.
Weckx et al. discloses in Fig. 4, Fig. 5 and Fig. 16
the active region of the first transistor [transistor having p gate] comprising a plurality of first nanostructures [left nanosheets], extending along a first lateral direction;
the active region of the second transistor [transistor having n gate] comprising a plurality of second nanostructures [right nanosheets], extending along the first lateral direction;
the dielectric fin structure [dielectric wall] extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures [left nanosheets] along the second lateral direction;
the first gate structure [p gate] of the first transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and
the second gate structure [n gate] of the second transistor straddling the plurality of second nanostructures;
wherein the dielectric fin structure [dielectric wall] laterally and completely separates the plurality of first nanostructures and the first gate structure [p gate] of the first transistor from the plurality of second nanostructures and the second gate structure [n gate] of the second transistor along the second lateral direction, respectively;
the second gate structure [n gate] of the second transistor is isolated from the first gate structure [p gate] of the first transistor by the dielectric fin structure [dielectric wall].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen899 and Weckx et al. into the method of Hsiao et al. and Kim et al. to include the active region of the first programming transistor comprising a plurality of first nanostructures, extending along the first lateral direction; the active region of the second programming transistor comprising a plurality of second nanostructures, extending along the first lateral direction the dielectric fin structure extending along the first lateral direction and disposed immediately next to a first sidewall of each of the plurality of first nanostructures along the second lateral direction; the first gate structure of the first programming transistor wrapping around each of the plurality of first nanostructures except for the first sidewalls; and the second gate structure of the second programming transistor straddling the plurality of second nanostructures; wherein the dielectric fin structure laterally and completely separates the plurality of first nanostructures and the first gate structure of the first transistor from the plurality of second nanostructures and the second gate structure of the second transistor along the second lateral direction, respectively. The ordinary artisan would have been motivated to modify Hsiao et al. and Kim et al. in the above manner for the purpose of providing a fork nanosheet (forksheet) device having a GAA feature to provide an excellent channel control capability, to optimize effective drive current per unit are, to provide better scalability of area and performance, to achieve extremely scaled PN space using limited additional processing complexity, to scaling SRAM bit cell area and to increase read delay performance [Abstract of Weckx et al. and paragraph [0003]-[0005], [0027]-[0028] of Chen899]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Kim et al. fails to disclose
wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure.
Kim et al. discloses in Fig. 9-11
wherein the first reading transistor [M13 or M23] and the first programming transistor [M12 or M22] share a common source/drain structure.
Hsiao et al. discloses in Fig. 2F, paragraph [0044]
wherein the first programming transistor and the first reading transistor share a common semiconductor source/drain structure [114A].
Lilak et al. discloses in Fig. 8C
a source/drain structure [805] of a transistor vertically extending from the substrate [801] to a top surface of a gate structure [813].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lilak et al. and Hsiao et al. into the method of Kim et al. to include wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable configuration of a source/drain structure [paragraph [0079] of Lilak et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 7, 9, 24-27, Kim et al. fails to disclose
a plurality of third nanostructures of the first reading transistor, extending along the first lateral direction;
a third gate structure of the first reading transistor, straddling the plurality of third nanostructures;
wherein the plurality of third nanostructures and the third gate structure form, in part, the first reading transistor of an anti-fuse memory cell;
a plurality of fourth nanostructures of the second reading transistor, extending along the first lateral direction;
wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction;
a fourth gate structure straddling the plurality of fourth nanostructures, wherein the plurality of fourth nanostructures and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell;
wherein the dielectric fin structure completely separates the plurality of third nanostructures and the third gate structure of the first reading transistor from the plurality of fourth nanostructures and the fourth gate structure of the second reading transistor along the second lateral direction.
Hsiao et al. discloses in Fig. 2C, Fig. 2F
an active region [101C] of the first reading transistor [transistor having gate 133C], extending along the first lateral direction;
a third gate structure [133C] of the first reading transistor [transistor having gate 133C] straddling the active region of the first reading transistor [transistor having gate 133C];
wherein the active region [101C] of the first reading transistor [transistor having gate 133C] and the third gate structure [133C] form, in part, the first reading transistor of an anti-fuse memory cell;
an active region [101D] of the second reading transistor [transistor having gate 133D], extending along the first lateral direction;
a fourth gate structure [133D] straddling the active region of the second reading transistor [transistor having gate 133D],
wherein the active region of the second reading transistor [transistor having gate 133D] and the fourth gate structure [133D] form, in part, the second reading transistor of the anti-fuse memory cell;
wherein the dielectric fin structure [134’] completely separates the third gate structure [133C] of the first reading transistor from the fourth gate structure [133D] of the second reading transistor along the second lateral direction.
Notes, per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).]
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Hsiao et al. into the method of Kim et al. to include an active region of the first reading transistor, extending along the first lateral direction; a third gate structure of the first reading transistor straddling the active region of the first reading transistor; wherein the active region of the first reading transistor and the third gate structure form, in part, the first reading transistor of an anti-fuse memory cell; an active region of the second reading transistor, extending along the first lateral direction; a fourth gate structure straddling the active region of the second reading transistor, wherein the active region of the second reading transistor and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell; wherein the dielectric fin structure completely separates the third gate structure of the first reading transistor from the fourth gate structure of the second reading transistor along the second lateral direction. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable layout structure of transistors to form reliable semiconductor devices at smaller and smaller sizes and having improved carrier mobility [paragraph [0004], [0088], [0095] and [0111] of Hsiao et al.].
Hsiao et al. and Kim et al. fails to disclose
the active region of the first reading transistor comprising a plurality of third nanostructures, extending along the first lateral direction;
the third gate structure of the first reading transistor, straddling the plurality of third nanostructures;
the active region of the second reading transistor comprising a plurality of fourth nanostructures, extending along the first lateral direction;
wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction;
the fourth gate structure of the second reading transistor, straddling the plurality of fourth nanostructures;
wherein the dielectric fin structure completely separates the plurality of third nanostructures of the first reading transistor from the plurality of fourth nanostructures of the second reading transistor along the second lateral direction.
Chen899 discloses in Fig. 9, paragraph [0087]-[0115]
the active region of the third transistor comprising a plurality of third nanostructures [206] extending along the first lateral direction [out of plane direction];
the third gate structure [225] straddling the plurality of third nanostructures [206];
the active region of the fourth transistor comprising a plurality of fourth nanostructures [208] extending along the first lateral direction [out of plane direction];
wherein the plurality of fourth nanostructures [208] extend along the first lateral direction [out of plane direction] and separated from the plurality of third nanostructures [206] along the second lateral direction [horizontal direction];
the fourth gate [226] straddling the plurality of fourth nanostructures [208];
wherein the dielectric fin structure [216] completely separates the plurality of third nanostructures of the first reading transistor from the plurality of fourth nanostructures [208] of the second reading transistor along the second lateral direction.
Weckx et al. also discloses in Fig. 4, Fig. 5 and Fig. 16c
the active region of the third transistor comprising a plurality of third nanostructures extending along the first lateral direction;
the third gate structure straddling the plurality of third nanostructures;
the active region of the fourth transistor comprising a plurality of fourth nanostructures extending along the first lateral direction;
wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction;
the fourth gate straddling the plurality of fourth nanostructures.
wherein the dielectric fin structure [dielectric wall] completely separates the plurality of third nanostructures and the third gate structure of the first reading transistor from the plurality of fourth nanostructures and the fourth gate structure of the second reading transistor along the second lateral direction.
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Incorporating GAA structure disclosed by Chen899 and to formed the first and second reading transistors of the anti- fuse memory cell suggested by Hsiao et al. and Kim et al. would result to the limitation of “wherein the plurality of third nanostructures and the third gate structure form, in part, the first reading transistor of the anti- fuse memory cell” and “wherein the plurality of fourth nanostructures and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen899 and Weckx et al. into the method of Hsiao et al. and Kim et al. to include the active region of the first reading transistor comprising a plurality of third nanostructures, extending along the first lateral direction; the third gate structure of the first reading transistor, straddling the plurality of third nanostructures; wherein the plurality of third nanostructures and the third gate structure form, in part, the first reading transistor of the anti- fuse memory cell; the active region of the second reading transistor comprising a plurality of fourth nanostructures, extending along the first lateral direction; wherein the plurality of fourth nanostructures extend along the first lateral direction and separated from the plurality of third nanostructures along the second lateral direction; the fourth gate structure of the second reading transistor, straddling the plurality of fourth nanostructures, wherein the plurality of fourth nanostructures and the fourth gate structure form, in part, the second reading transistor of the anti-fuse memory cell. The ordinary artisan would have been motivated to modify Hsiao et al. and Kim et al. in the above manner for the purpose of providing a fork nanosheet (forksheet) device having a GAA feature to provide an excellent channel control capability, to optimize effective drive current per unit are, to provide better scalability of area and performance, to achieve extremely scaled PN space using limited additional processing complexity, to scaling SRAM bit cell area and to increase read delay performance [Abstract of Weckx et al. and paragraph [0003]-[0005], [0027]-[0028] of Chen899]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 29, Kim et al. discloses in Figs. 9-11
wherein the common source/drain structure is a first source/drain structure of the first reading transistor [M13 or M23], and the first reading transistor [M13 or M23] includes a second source/drain structure coupled to the bit line.
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Hsiao et al. discloses in Fig. 2F, paragraph [0046]
the common semiconductor source/drain structure is a first epitaxial source/drain structure of the first reading transistor, and the first reading transistor includes a second epitaxial source/drain structure.
Thus, the combination of Kim et al. and Hsiao et al. discloses
wherein the common source/drain structure is a first epitaxial source/drain structure of the first reading transistor, and the first reading transistor includes a second epitaxial source/drain structure coupled to the bit line.
[Notes, the term “epitaxial” directs to process for forming a first and second semiconductor source/drain structures. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Furthermore, "[b]ecause validity is determined based on the requirements of patentability, a patent is invalid if a product made by the process recited in a product-by-process claim is anticipated by or obvious from prior art products, even if those prior art products are made by different processes." Amgen Inc. v. F. Hoffman-La Roche Ltd., 580 F.3d 1340, 1370 n 14, 92 USPQ2d 1289, 1312, n 14 (Fed. Cir. 2009). (MPEP 2113).” Further, per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).]
Claims 12-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20130077376) in view of Weckx et al. (“Novel forksheet device architecture as ultimate logic scaling device towards 2nm”, IEEE 2019) and Chen et al. (US Pub. 20220028899), hereafter Chen899 and Kim et al. (US Pub. 20140001441), hereafter Kim441.
Regarding claims 12-14, and 17, Kim et al. discloses in Fig. 10-Fig. 11, a memory device, comprising:
a plurality of memory cells [OPT cells][paragraph [0036]], each of which includes a first programming transistor [M22] and a first reading transistor [M23] coupled to each other in series, and a second programming transistor [M25] and a second reading transistor [M26] coupled to each other in series;
a plurality of bit lines [Kim discloses one OTP memory cell has at least a bit line, thus plurality of OTP memory cells must have plurality of bit lines], one of which is operatively coupled to both of a source/drain of the first reading transistor [M23] and a source/drain of the second reading transistor [M26]; and
a conduction path configured to electrically connect between a gate terminal of the first programming transistor [M22] and one of the plurality of bit lines [BL and BLb], in response to the first programming transistor [M22] broken down [paragraph [0055], [0062]];
wherein a first gate structure [G22] of the first programming transistor [M22] is coupled to a word line
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Notes, the limitation of “programming transistor”, “reading transistor” and “a conduction path configured to form in response to the first programming transistor broken down, the conduction path between a gate terminal of the first programming transistor and the bit line” direct to intended operation of the device. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 (II). Besides, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Kim et al. fails to disclose
wherein a first channel structure of the first programming transistor has a first sidewall, and a second channel structure of the second programming transistor has a second sidewall facing the first sidewall;
wherein the first sidewall and second sidewall are each in contact with a dielectric fin structure,
wherein the dielectric fin structure laterally and completely separates the first channel structure from the second channel structure and also laterally and completely separates the first gate structure of the first programming transistor from a second gate structure of the second programming transistor;
wherein the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure;
wherein a third channel structure of the first reading transistor has a third sidewall, and a fourth channel structure of the second reading transistor has a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each in contact with the dielectric fin structure;
wherein the first reading transistor and second reading transistor share a common fifth channel structure;
wherein each of the first channel structure and second channel structure includes a plurality of nanostructure vertically spaced apart from one another.
Chen899 discloses in Fig. 9, paragraph [0087]-[0115]
wherein a first channel structure [201] of the first transistor has a first sidewall, and a second channel structure [203] of the second transistor has a second sidewall facing the first sidewall; and
wherein the first sidewall and second sidewall are each in contact with a dielectric fin structure [213];
wherein the dielectric fin structure [213] laterally and completely separates the first channel structure [201] from the second channel structure [203] and also laterally and completely separates the first gate structure [223] of the first transistor from a second gate structure [224] of the second transistor;
wherein the second gate structure [224] of the second transistor is isolated from the first gate structure [223] of the first transistor by the dielectric fin structure [213];
wherein each of the first channel structure [201] and second channel structure [203] includes a plurality of nanostructure vertically spaced apart from one another.
Chen899 further discloses in Fig. 9
wherein a third channel structure [206] has a third sidewall, and a fourth channel structure [208] has a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each in contact with a dielectric fin structure.
Weckx et al. further discloses in Fig. 5, Fig. 10, Fig. 16, Fig. 18
wherein a third channel structure of a third transistor has a third sidewall, and a fourth channel structure of a fourth transistor has a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each in contact with the dielectric fin structure [dielectric wall][Fig. 16];
wherein the third transistor and the fourth transistor share a common fifth channel structure [Fig. 10].
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Chen899 discloses forksheet transistors. Weckx et al. suggests that forksheet transistor can be used in memory device (i.e., SRAM Design). Thus, the forksheet transistors disclosed by Chen899 and Weckx et al. can be used as the first programming transistor, the second programming transistor, the first reading transistor and the second reading transistor.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Weckx et al. and Chen899 into the method of Kim et al. to include wherein a first channel structure of the first programming transistor has a first sidewall, and a second channel structure of the second programming transistor has a second sidewall facing the first sidewall; and wherein the first sidewall and second sidewall are each in contact with a dielectric fin structure and wherein the dielectric fin structure laterally and completely separates the first channel structure from the second channel structure and also laterally and completely separates the first gate structure of the first programming transistor from a second gate structure of the second programming transistor; wherein the second gate structure of the second programming transistor is isolated from the first gate structure of the first programming transistor by the dielectric fin structure; wherein a third channel structure of the first reading transistor has a third sidewall, and a fourth channel structure of the second reading transistor has a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each in contact with the dielectric fin structure; wherein the first reading transistor and second reading transistor share a common fifth channel structure; wherein each of the first channel structure and second channel structure includes a plurality of nanostructure vertically spaced apart from one another. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing forksheet (FSH) device architecture for achieving extremely scaled PN space using limited additional processing complexity; scaling SRAM bit cell area and increasing read delay performance [Abstract of Weckx et al.; paragraph [0004] of Chen899]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Kim et al. fails to disclose
wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure.
Kim et al. discloses in Figs. 9-11
wherein the first reading transistor [M13 or M23] and the first programming transistor [M12 or M22] share a common source/drain structure.
Kim441 discloses in Fig. 1D, paragraph [0029]
a source/drain structure of a transistor comprises a semiconductor source/drain structure [115] vertically extending from the substrate [104] to a top surface of a gate structure [116].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim441 into the method of Kim et al. to include wherein the first reading transistor and the first programming transistor share a common semiconductor source/drain structure vertically extending from the substrate to a top surface of the first gate structure or of the second gate structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable configuration of a source/drain structure [paragraph [0029] of Kim441]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 15, Kim et al. discloses in Fig. 3-Fig. 5, Fig. 8-Fig. 11
a plurality of reading word lines [WLR], one of which is operatively coupled to both of a gate [G3 or G13 or G23] of the first reading transistor [M3 or M13 or M23] and a gate [G6 or G16 or G26] of the second reading transistor [M6 or M16 or M26].
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-7, 9, 12-15, 17, 21, 23-29 have been considered but are moot in view of the new ground of rejection and because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893