DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on 10/29/2025 have been entered and considered. The amendments to claims 1, 15 and 20 and the added claim 21 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim 1 regarding the air gaps have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Itoh US 20110089574 A1 (hereinafter referred to as Itoh), in view of Lee, et al., US 20160133512 A1 (hereinafter referred to as Lee), and in view of Shini et al. US 20210287995 A1 (hereinafter referred to as Shini).
Regarding claim 1, Itoh teaches
An integrated circuit chip (“semiconductor device” para. 0047 FIG. 6A-7B) comprising:
a base layer (“insulating layer 2” para. 0048 FIG. 7A-7B);
a first wiring layer (“first interconnect layer (M1)” para. 0047 FIG. 7A-7B) disposed on the base layer, the first wiring layer including a first wiring structure (“lower-layer interconnect 13” with “first contact via 15, para. 0049-0050 FIG. 7A-7B);
an insulating layer (“insulating layer 22” para. 0049 FIG. 7A-7B) disposed on the first wiring layer, the insulating layer including a first insulating layer (lower portion of “insulating layer 22” as drawn in annotated FIG. 7A below) and a second insulating layer (upper portion of “insulating layer 22” as drawn in annotated FIG. 7A below) disposed on the first insulating layer;
a second wiring layer penetrating the insulating layer (“second interconnect layer (M2)” para. 0047 FIG. 6A-7B) on the first wiring layer, the second wiring layer including a second wiring structure (“intermediate interconnect 23” with “second contact via 25” para. 0050 FIG. 7A-7B), the second wiring structure has a first metal layer (“intermediate interconnect 23”) and a second metal layer (“second contact via 25”) disposed directly on a top surface of the first metal layer, an entirety of the top surface of the first metal layer is flat (the top of “intermediate interconnect 23” appears flat), wherein side surfaces of the first metal layer and the second metal layer are coplanar (side surfaces of “intermediate interconnect 23” and “second contact via 25” are coplanar as seen in FIG. 7A), and the side surfaces of the first metal layer and the second metal layer directly contact the second insulating layer (side surfaces of “intermediate interconnect 23” and “second contact via 25” directly contact upper portion of “insulating layer 22”);
a third wiring layer (“third interconnect layer (M3)” para. 0047 FIG. 6A-7B) disposed on the second wiring layer, the third wiring layer including a third wiring structure (“intermediate interconnect 33” with “third contact via 35”, para. 0050 FIG. 7A-7B).
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However, Itoh fails to teach a plurality of first wiring structures, a plurality of second wiring structures, plurality of third wiring structures, the first metal layer and the second metal layer respectively having different resistivities, wherein each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof, wherein each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof, wherein each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures.
Nevertheless, the semiconductor device in Itoh achieves increased heat dissipation and is used to interconnect semiconductor chips with other devices (para. 0005-0007). As stated in para. 0054, the structure comprising “first interconnect layer M1” connected to “fourth interconnect 43” through the aligned “contact vias 15, 25, 35” increases the thermal conductivity between layers so that heat from “second and third interconnect layers M2, M3” can be more easily dissipated. Semiconductor chips have several connection terminals, from hundreds to hundreds of thousands, such that a plurality of connections are expected to be made with the semiconductor device in Itoh and there are plurality of regions that may benefit of improved heat dissipation. Although Itoh is silent respect to there being a plurality of these interconnect structures, duplication of parts has no patentable significance unless a new and unexpected result is produced, as stated in MPEP 2144.04, V1, B. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that multiple interconnects as seen in FIG. 6A-7B can be used to alleviate the generation of heat in regions across the semiconductor interconnect device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip in Itoh with a plurality of first wiring structures, a plurality of second wiring structures, and a plurality of third wiring structures. Having a plurality of first, second, and third wiring structures allows for a plurality of interconnect structures that can dissipate heat generated across the entire integrated circuit chip.
However, Itoh fails to teach the first metal layer and the second metal layer respectively having different resistivities, wherein each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof, wherein each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof, wherein each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures.
Nevertheless, Lee teaches
the first metal layer (“first wiring pattern 110” para. 0055 FIG. 3, which comprises “tungsten and/or copper”) and the second metal layer respectively having different resistivities (second metal pattern” para. 0077 FIG. 3, which comprises “tungsten and/or copper”. One metal layer may be tungsten, the other copper, or both can have different combinations of tungsten and copper and have different resistivities.)
wherein each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof (“first metal pattern 111” of the “first wiring pattern 110” comprises “tungsten and/or copper”, para. 0055),
wherein each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof (“second metal pattern” comprises “tungsten and/or copper” para. 0077),
wherein each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures (Since the “third conductive pattern 220” can be formed substantially the same way as “second conductive pattern 120” and the “second conducive pattern 120” is made of “tungsten and/or copper’, the “third conductive pattern 220” can be made of copper while the “first conductive pattern 110” can be made of tungsten.).
Itoh and Lee teach multilayer wiring patterns. The interconnects in Itoh are made of copper but can be made with other low resistance materials (0083). The interconnects in Lee are made of copper or tungsten. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that tungsten is a known metal material suitable for use as an alternative to copper for interconnect structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught in Itoh with the wiring structure material taught in Lee. Tungsten or combinations of copper and tungsten are suitable alternative known for use as wiring structures.
However, Itoh, modified by Lee, fail to teach wherein the first wiring layer comprises a first air gap formed between the plurality of first wiring structures, wherein the third wiring layer comprises a second air gap formed between the plurality of third wiring structures, and wherein the second wiring layer does not include an air gap.
Nevertheless, Shini teaches
wherein the first wiring layer (layer with “3-1 layer 3a” and “second layer 2A”, para. 0063 FIG. 6) comprises a first air gap (“insulating space 20” of the “second layer 2A”, para. 0061) formed between the plurality of first wiring structures,
wherein the third wiring layer (layer with “3-4 layer 3d” and “second layer 2B”, para. 0064) comprises a second air gap (“insulating space 20” of the “second layer 2B”, para. 0064) formed between the plurality of third wiring structures, and
wherein the second wiring layer does not include an air gap (layer with “3-2 layer 3b” and “3-3 layer 3c” has no “insulating space 20”).
Itoh, modified by Lee, and Shini teach multilayer wiring patterns. The “insulating spaces 20” reduce the capacitance between adjacent wirings compared to when the spaces contain an insulating material (para. 0079). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “insulating spaces 20” can reduce the capacitance between wirings in “first interconnect layer (M1)” and “third interconnect layer (M3)”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught between Itoh and Lee with the air gaps in Shini. Air gaps in the first and third wiring layers reduce the capacitance between adjacent wirings.
Regarding claim 3, Itoh, modified by Lee and Shini, teaches the integrated circuit chip according to claim 1. Itoh, modified by Lee, further teaches
wherein each of the plurality of third wiring structures comprises Cu, Ir, Rh or Co (“third contact via 35” comprises copper, para. 0050. “Interconnects 11, 21, 31, 41, 51 made of, for example, Cu”, para. 0049, and “intermediate interconnect 33” has the same shading as the “interconnects 31” in the same layer, such that it is understood they comprise the same material.).
Regarding claim 4, Itoh, modified by Lee and Shini, teaches the integrated circuit chip of claim 1 comprising first and second metal layers. As for the limitation “formed through different deposition processes, respectively”, "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted) (Claim was directed to a novolac color developer – (see MPEP 2113 I).
Regarding claim 5, Itoh, modified by Lee and Shini, teaches the first and third wiring structures. As for the limitation “formed though different deposition processes, respectively”, "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted) (Claim was directed to a novolac color developer – (see MPEP 2113 I).
Regarding claim 13, Itoh, modified by Lee and Shini, as teach the integrated circuit chip according to claim 1, further comprising:
a first capping pattern (“first etch stop layer 130”, Lee para. 0056) disposed on the first wiring structures, and a second capping pattern (“capping layer 140”, Lee para. 0059) disposed on the second wiring structures, wherein each of the first and second capping patterns comprises at least one compound selected from SiO2, A1203, TiOx, TaOx, HfOx, ZrOx, MgO, SiN, TiN or TaN (“first etch stop layer 130” and “capping layer 140” comprise silicon nitride, para. 0056 and 0059).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Itoh, modified by Lee and Shini, as applied to claim 1 above, and further in view of Tamura, et al., US 20160233865 A1 (hereinafter referred to as Tamura).
Itoh, modified by Lee and Shini, teaches the integrated circuit chip according to claim 1 but fails to teach wherein each of the plurality of first wiring structures, the first metal layer and the second metal layer comprises an MoW alloy.
Nevertheless, Tamura teaches
each of the plurality of first wiring structures (“wiring layer MA-1”, para. 0061 annotated FIG. 5 below), the first metal layer and the second metal layer comprises an MoW alloy (“wiring layer MA-2”, para. 0061 annotated FIG. 5, can be a stack of conductors, such that it may comprise a two-layer stack, para. 0062. Bottommost layer contacting the “plugs 71” is considered the first metal layer and the topmost layer contacting the “plugs 72” is considered the second metal layer, para. 0094 annotated FIG. 5. Lines across “wiring layer MA-2” elements dividing the stack in annotated FIG. 5 are enlarged for clarity.).
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Itoh, modified by Lee and Shini, and Tamura teach integrated circuit chips. The wiring structures in Tamura comprise an MoW alloy because of the material’s resistance to heat around 400⁰C but can alternatively be made of individual metals such as tungsten, molybdenum, or niobium (para. 0061). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that an MoW alloy is a suitable alternative for the intended purpose of forming wiring structures with high heat resistance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught between Itoh, Lee, and Shini with the wiring layer material taught in Tamura. MoW alloys are a well-known alternative used in the formation of wiring structures that require high temperature tolerance.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Itoh, modified by Lee and Shini, as applied to claim 1 above, in view of Zierath, et al., US 20190393156 A1 (hereinafter referred to as Zierath), and further in view of Kobayashi et al. US 20140087556 A1 (hereinafter referred to as Koabayashi).
Regarding claim 6, Itoh, modified by Lee and Shini, teaches the integrated circuit chip according to claim 1 but fails to teach further comprising: a first seed layer and a first adhesive layer disposed under the plurality of first wiring structures, and a second seed layer and a second adhesive layer disposed under the plurality of second wiring structures, side surfaces of the second seed layer and the second adhesive layer directly contact the insulating layer, wherein each of the first and second seed layers comprises W, Mo, or an alloy thereof and has a thickness in a range of about 0.5 to about 5 nm, wherein each the first and second adhesive layers comprises MoN or WN.
Nevertheless, Zierath teaches
further comprising: a first seed layer (“seed layer 130”, para. 0123 FIG. 1C and 1F) and a first adhesive layer (“barrier/adhesion layer 120”, para. 0123 FIG. 1B and 1F) disposed under the first wiring structure, wherein the first seed layer comprises W, Mo, or an alloy thereof (“seed layer 130” comprises alloys that contain molybdenum or tungsten, para. 0095-0105) and has a thickness in a range of about 0.5 to about 5 nm (“the seed layer 130 may have a thickness less than 3 nanometers”, para. 0046), wherein the first adhesive layer comprises MoN or WN (“barrier/adhesive layer 120” comprises WN, para. 0045).
Itoh, modified by Lee and Zierath teach wiring structures for use in integrated circuits. The examiner understands that the “barrier/adhesion layer 120” promotes improved adhesion between the “dielectric material 102” and the subsequently formed “seed layer 130”. The “seed layer 130” formed over the “barrier/adhesion layer 120” acts as a nucleation site for the fill material of the wiring structure (para. 0046). These features form part of a wiring structure that maintains low resistance and improved reliability (para. 0015). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the use of a Mo or W containing seed layer and WN containing adhesion layer are well-known for the formation of small-scale wiring structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught between Itoh, Lee, and Shini with the adhesion layer and seed layer taught in Zierath. The adhesion layer is a secure surface to bond the seed layer to and the seed layer acts as a nucleation site for the fill material.
However, Zierath fails to expressly teach a first seed layer and a first adhesive layer disposed under the plurality of first wiring structures, and a second seed layer and a second adhesive layer disposed under the plurality of second wiring structures, wherein each of the first and second seed layers comprises W, Mo, or an alloy thereof and has a thickness in a range of about 0.5 to about 5 nm, wherein each the first and second adhesive layers comprises MoN or WN. Zierath teaches a seed layer and adhesive layer under a single wiring structure.
Nevertheless, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the seed layer and the adhesive layer in Zierath can be duplicated and applied to a plurality of first wiring structures and plurality of second wiring structures to obtain the same benefit. Although Zierath does not teach a plurality of first and second wiring structures, mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see MPEP 2144.04.VI.B).
However, Itoh, modified by Lee, Shini, and Zieranth, fails to teach side surfaces of the second seed layer and the second adhesive layer directly contact the insulating layer.
Nevertheless, Kobayashi teaches the formation of wiring layers through a semi-additive process where a seed is deposited on an “resin layer 31”, then a “plating resist 16” is formed in portions of the “seed layer 22a” while gaps of exposed seed layer, then “metal plating layer 22b” is formed on the exposed “seed layer 22a”, and finally the “plating resist 16” is removed (para. 0059-0063). Each level of wirings is covered by an insulating “resin layer”, as shown in FIG. 9, such that side surfaces of the “seed layer 22a” and “metal plating layer 22b” contact the “resin layer” formed over the wiring. This semi-additive method is particularly suitable for forming thin wirings (para. 0064). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a semi-additive method is suitable for forming wiring structures having small dimensions. This method results in the adhesive layer, the seed layer, and the wiring structure contacting the insulating layer formed around them.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught between Itoh, Lee, Shini, and Zierath with the semi-additive method taught in Kobayashi. The method is suitable when fine wiring structures are desired.
Regarding claim 7, Itoh, modified by Lee, Shini, Zierath, and Kobayashi teaches the integrated circuit chip according to claim 6 and further teaches
wherein the first seed layer (“seed layer 130” in Zierath) is disposed directly under a corresponding of first wiring structure (“fill material 140”, para. 0123 FIG. 1F).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Itoh, modified by Lee and Shini, as applied to claim 1 above, and further in view of Yang, US 9793156 B1 (hereinafter referred to as Yang).
Itoh, modified by Lee and Shini, teaches the integrated circuit chip according to claim 1 but fails to teach wherein a width of each of the plurality of first wiring structures and a width of each of the plurality of second wiring structures is in a range of about 12 nm or less.
Nevertheless, Yang teaches
wherein a width (“W1”, col 5 line 18 FIG. 1) of a first wiring structure (“first metal line 146”, col 4 line 35 FIG. 1) and a width (W2” col 5 line 21 FIG. 1) a second wiring structure (“second metal line 154”, col 4 line 50 FIG. 1) is in a range of about 12 nm or less (“the width W1 of the first metal line 146 is in a range of about 5 nm to about 100 nm, and more preferably, in a range of about 10 nm to about 50 nm. Similarly, the width W2 of the second metal line 154 is in a range of about 5 nm to about 100 nm, and more preferably, in a range of about 10 nm to about 50 nm.”, col 5 lines 18-23)
Itoh, modified by Lee and Shini, and Yang teach interconnect structures for integrated circuits. Yang teaches that the cross-sectional area perpendicular to the current flow, the height times the width, of the “first metal line 146” and “second metal line 154” affects the resistance of the metal line (col 5 lines 28-41). A reduction in cross-section by reducing the width or the height increases the resistance of the metal line. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the width of a first and second wiring structures is a result effective variable. The width can be chosen based on the materials and performance desired from the integrated circuit chip.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught between Itoh and Lee with the width of a first and second wiring structure widths as taught in Yang. The width of the wiring lines is a result effective variable that affects the resistance through the wiring structures.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Itoh, modified by Lee and Shini, as applied to claim 1 above, and further in view of Law et al. US 20190021176 A1 (hereinafter referred to as Law).
Itoh, modified by Lee, teaches the integrated circuit according to claim 1 but fails to teach wherein a first via penetrates through a portion of the first insulating layer disposed between the first and second wiring layers to connect one of the plurality of first wiring structures and one of the plurality of second wiring structures, wherein a second via penetrates through the second insulating layer and another portion of the first insulating layer, extending from the portion of the first insulating layer disposed between the first and second wiring layers, to connect one of the plurality of first wiring structures and one of the plurality of third wiring structures.
Nevertheless, Law teaches
wherein a first via (“via structure V1” para. 0017 FIG. 6) penetrates through a portion of the first insulating layer (silicon nitride “ILD layer 105′ ” para. 0017 FIG. 6) disposed between the first (“metal layer M1” para. 0017) and second wiring layers (“metal layer M2” para. 0018) to connect one of the plurality of first wiring structures (right structure of “metal layer M1”) and one of the plurality of second wiring structures (middle structure of “metal layer M2”),
wherein a second via (portion of “skip via structure 170” including “via structure 135’ “ and portion of “metal 110” ” in “via structure 165’ “ para. 0025-0026 FIG. 5-6) penetrates through the second insulating layer (silicon nitride “capping layer 115’ “ para. 0019) and another portion of the first insulating layer (“via structure 135’ “ penetrates “ILD layer 105’ ”), extending from the portion of the first insulating layer disposed between the first and second wiring layers (“via structure 135’ ” extends from a lower portion of “ILD layer 105”), to connect one of the plurality of first wiring structures (left structure in “metal layer M1”) and one of the plurality of third wiring structures (upper portion of “metal 110” ”, at same level as “M3” in FIG. 6).
Itoh, modified by Lee, and Law teach layers of wiring structures. The “skip via structure 170” with via portion of “metal material 110” in Law is useful for routing through and avoiding a wiring structure in a way that lowers resistance and capacitance (para. 0003). Meanwhile, “via M1” can connect the adjacent layers “metal layer M1” and “metal layer M2”. Both vias interconnect different metal layers that are separated by insulating layers between them. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a skip via structure can be used to route a signal between non-adjacent wiring layers and maintain favorable electrical performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit chip taught between Itoh and Lee with the via structures taught in Law. The via structures connect wiring layers that are spaced apart by insulating layers. The second via in particular can connect directly to a wiring structure in the third wiring layer while bypassing the second wiring layer and it is a connection with improved resistance and capacitance characteristics.
Art not relied upon but relevant to applicant’s disclosure
Mignot et al US 20210082747 A1 teaches vias from first to second wiring layer and first to third wiring layer.
Zhang et al US 20180130699 A1 teaches a via from first to second wiring layer and a via from first to third wiring layer that passes through the second wiring layer.
Lur et al. US 20040097013 A1 teaches air gaps that span multiple layers in height.
Matsunaga et al. US 20080296775 A1 teaches air gaps in multiple adjacent wiring layers
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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supervisor, Julio Maldonado can be reached on (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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