Attorney’s Docket Number: QCOM-4545US (2102678)
Filing Date: 9/15/2021
Inventors: Chen et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 4/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis for a rejection as subjected to pre-AIA instead will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 17, mailed on 2/23/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submissions filed on 4/23/2026 and 5/22/2026 have been entered.
Amendment Status
The RCE submission filed on 4/23/2026 as an amendment in reply to the Office action in paper no. 17 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-26.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 4 and 14 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claims 4 and 14 recite that the first and second solders include an intermetallic compound (IMC). The specification, as originally filed, does not provide an adequate written description of a solder including an IMC. The specification states that the solder may include IMC that may be formed when metal from the pad and/or the pillar diffuses into the interconnect (see par. 0038). However, the specification does not describe the IMC with sufficient detail to reasonably convey to a person of ordinary skill in the art that the inventor had possession of a solder including an IMC at the time of filing. In particular, no drawing illustrates the IMC, no specific IMC composition, structure, or representative species is identified. No common structural features or characteristics of the IMC are described. The disclosure uses permissive language, “may include,” “may be formed”, rather than describing an embodiment in which the solder affirmatively includes an IMC as required by the claims. The claims require that the solder includes an IMC. The specification’s limited and conclusory reference to a possible IMC formation does not demonstrate possession of the claimed subject matter across the full scope of the limitation. A mere mention of a possible feature, without adequate descriptive support, is insufficient to satisfy the written description requirement. See MPEP § 2163; Ariad v. Eli Lilly.
Claims 4 and 14 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The claims require that the solder includes an IMC. However, the specification provides no working examples of a solder that includes an IMC, and provides no process parameters, e.g., temperature ranges, time ranges, alloy compositions, pad/pillar metallurgies, that would guide formation of the IMC. It provides no guidance as to how to control, ensure, or verify the presence of the IMC within the solder, and does not identify any particular IMC or class of IMCs encompassed by the claims.
Formation of intermetallic compounds in solder systems depends on multiple variables, including solder alloy composition, metallurgy of adjacent structures, thermal reflow profile, diffusion conditions, and interface chemistry. In view of the breadth of the claim and the limited guidance in the specification, a person of ordinary skill in the art would be required to engage in undue experimentation to determine how to reliably produce a solder that includes an IMC across the full scope of the claimed invention.
While intermetallic compounds in solder systems may be generally known in the art, the enablement requirement is not satisfied by general knowledge alone where the specification fails to provide sufficient guidance commensurate in scope with the claims. See MPEP § 2164.
Accordingly, the specification does not enable the full scope of the claimed limitation requiring that the solder includes an IMC.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-13, 15-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsao (US 2016/0148891).
Regarding claim 1, Tsao (see, e.g., figs. 1 and 7C) shows all aspects of the instant invention including an integrated device comprising:
A die portion 102 comprising:
Pads 1022
Under bump metallization interconnects (UBMs) 1021 coupled to the pads
Pillar interconnects coupled to the UBMs and including first and second pillar interconnects 103, and
First and second solder interconnects 105/104
wherein:
The first pillar comprises first 1031 and second 1032 pillar portions
The first pillar portion 1031 has a first width and is coupled to and touches a first UBM 1021
The second pillar portion 1032 comprises a second width greater than the first width
The first 1031 and second 1032 pillar portions are made of the same material
The second pillar portion 1032 has a surface that faces in a direction of the die portion
The surface of the second pillar portion 1032 that faces the die portion does not touch any UBM
The second pillar 103 comprises third 1031 and fourth 1032 pillar portions
The third pillar portion 1031 has a third width and is coupled to and touches a second UBM 1021
The fourth pillar portion 1032 comprises a fourth width greater than the third width
The fourth pillar portion 1032 is coupled to and touches the third pillar portion 1031
The first solder 105/104 is coupled to and touches the second portion 1032, and
The second solder 105/104 is coupled and touches the fourth portion 1032
Regarding claim 11, Tsao (see, e.g., figs. 1 and 7C) shows all aspects of the instant invention including a package 100 comprising:
A substrate 101, and
An integrated device 102 coupled to the substrate through a plurality of pillar 103 and solder 105/104 interconnects
wherein:
A plurality of pads 1022
The device comprises UBMs 1021 coupled to the pillars and pads
The pillars 103 includes first and second pillars
The first pillar includes first 1031 and second 1032 pillar portions
The first pillar portion 1031 has a first width
The second pillar portion 1032 has a second width greater than the first width
The first 1031 and second 1032 pillar portions are made of the same material
The second pillar portion 1032 comprises a surface that faces in a direction of a die portion of the device and does not touch any UBMs 1021
The second pillar portion 1032 is directly coupled to and touching a first solder 105/104
The second pillar comprises third 1031 and fourth 1032 pillar portions
The third pillar portion 1031 has a third width and is coupled to and touches an UBM 1021
The fourth pillar portion 1032 has a fourth width greater than the third width
The fourth pillar potion 1032 is coupled to and touches the third pillar portion 1031
The fourth pillar portion 1032 does not touch any UBM 1021
The fourth pillar portion 1032 is directly coupled and touches a second solder 105/104
Regarding claims 2 and 12, Tsao (see, e.g., figs. 1 and 7C) shows that the surface of the second portion 1032 is a horizontal surface that is parallel to a horizontal surface of a first pad 1022, and faces away from the substrate 101.
Regarding claims 3 and 13, Tsao (see, e.g., par.0028) teaches that the first interconnect 103 is configured to provide an electrical path for input/output signals to and/or from the device 102.
Regarding claim 5, Tsao (see, e.g., fig. 7C) shows that the first pillar portion 1031 touches the second pillar portion 1032 and the first UBM 1021.
Regarding claim 15, Tsao (see, e.g., fig. 7C) shows that the third pillar portion 1031 touches the fourth pillar portion 1032 and the UBM 1021.
Regarding claims 6 and 16, Tsao (see, e.g., par.0028) shows that the second pillar 103 is configured to provide an electrical path for power to the device 102.
Regarding claims 7 and 17, Tsao (see, e.g., fig. 7C) shows that the first interconnect 103 comprises a cross-section side profile having a T shape.
Regarding claim 9, Tsao (see, e.g., par.0028) shows the device wherein:
The first interconnect 103 is configured to provide an electrical path for input/output signals to and/or from the device 102
The second interconnect 103 is configured to provide an electrical path for power to the device 102
Regarding claim 10, Tsao shows the die portion 102 comprising:
A die substrate (see, e.g., par.0024/ll.1-4)
Transistors formed in and/or over the die substrate (see, e.g., par.0024/ll.11-12)
An interconnect portion located over the die substrate (see, e.g., par.0025/ll.1-3 and par.0026/1-5)
Regarding claim 20, Tsao (see, e.g., figs. 1 and 7C) shows the package 100 wherein:
A plurality of pads comprises a first pad 1022
A first UBM 1021 is coupled to and touches the first pad 1022
The surface of the second portion 1032 includes a horizontal surface that does not touch the first UBM interconnect 1021
The surface of the second portion 1032 does not touch any passivation layer 1023 and/or any dielectric layer of the device
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Shah (US 2020/0365543).
Regarding claims 8 and 18, (see, e.g., figs. 1, 8 and 9) Tsao discloses a semiconductor device 100 including a semiconductor chip 102 having conductive pillar interconnects 103 for electrically connecting the chip to a substrate 101 through solder 104/105. Further, Fig. 9 illustrates a top view of the semiconductor structure and shows a plurality of conductive traces 107 associated with the conductive interconnection structure. Tsao: ¶¶ [0039]-[0040]. Although Figs. 1, 8, and 9 depict only two conductive pillar/solder structures 103/104, the figures are directed to illustrate the configuration of the interconnection structure and do not indicate that the chip 102 is limited to exactly two pillar interconnects.
Tsao, however, does not expressly illustrate a third pillar interconnect in the particular view relied upon for the rejection, wherein the third pillar comprises:
A fifth pillar portion comprising the third width, and
A sixth pillar portion comprising the fourth width
wherein
the fifth portion is coupled and touches a third UBM
the sixth portion is coupled to and touches the fifth portion
the sixth portion does not touch the third UBM
the sixth portion is directly coupled to and touches a third solder
Shah teaches providing multiple conductive pillars on a semiconductor chip. In particular, paragraph [0034] explains that a semiconductor chip includes “multiple conductive pillars,” two of which are identified as conductive pillars 23 and 25. Shah further expressly states that, although only a few conductive pillars are depicted in the drawings, it should be understood that the pillars may number in the hundreds or thousands (Shah: ¶[0034]). Thus, Shah expressly teaches that the conductive pillars depicted are merely representative of a larger plurality of conductive pillars and that a semiconductor chip may include numerous additional conductive pillars beyond those individually illustrated.
It would have been obvious to one of ordinary skill in the art, at the time of the invention, to modify the semiconductor structure of Tsao to include an additional, i.e., third, conductive pillar interconnect, as taught by Shah. A person having ordinary skill in the art (PHOSITA) would have been motivated to provide additional conductive pillar interconnects in the semiconductor chip in order to increase the number of electrical connections between the chip and substrate and thereby provide greater interconnection density, data throughput, and flexibility in the interconnection arrangement. Indeed, Shah expressly recognizes that greater packing density in terms of conductive pillars is desirable and that larger numbers of conductive pillars can provide greater data throughput and additional flexibility in bump patterns (Shah: ¶ [0029]).
Accordingly, the combination of Tsao and Shah would have resulted in the semiconductor device of Tsao having at least a first pillar interconnect, a second pillar interconnect, and a third pillar interconnect, as recited by claim 8. The addition of the third pillar interconnect represents the use of a known arrangement of multiple conductive pillars for its known purpose of providing additional electrical connections and increased data throughput and interconnection density. Therefore, the claimed third pillar interconnect would have been an obvious modification of the semiconductor device of Tsao in view of the teachings of Shah.
Regarding claim 19, see the comments above in paragraph 24, with respect to claim 9, which are considered repeated here.
Response to Arguments
The applicants argue:
The metal cap layer 105 of Tsao is a component separate from both the conductive bump 103 and the solder 104. It is a barrier layer intended to prevent diffusion between the conductive bump 103 and the solder 104. The metal cap layer 105 cannot be considered part of the claimed solder interconnect because if it were, it could not perform its barrier function. Tsao further teaches that the solder 104 contacts only the metal cap layer 105 and does not contact the conductive bump 103 directly.
The examiner responds:
The argument is not persuasive because the rejection does not require that Tsao expressly identify the combination of the metal cap layer 105 and conductor 104 as a component denominated a “solder interconnect.” Rather, the rejection is based on the structure actually disclosed by Tsao and the scope of the claim.
As disclosed in paragraph [0023] of Tsao, conductor 104 is a solder and is used to bond the substrate 101 to the conductive bump 103. Paragraph [0029] further discloses that metal cap layer 105 is formed between conductor 104 and conductive bump 103. Thus, the combination of conductor 104 and metal cap layer 105 is positioned between and provides the connection between the conductive bump 103 and the substrate 101. Moreover, Tsao (¶0029/l.11) expressly discloses that the metal cap layer 105 may comprise Sn or SnPb, both of which are disclosed alternatives for the metal cap layer 105.
Accordingly, Tsao expressly discloses embodiments in which the conductive structure that couples the conductive bump 103 to the substrate includes solder 104 and a metal cap layer 105 comprising a solder material such as Sn or SnPb. In such an embodiment, the solder interconnect comprising the metal cap layer 105 and the solder 104 is directly between and in contact with the conductive bump 103. The fact that Tsao also describes the metal cap layer 105 as capable of functioning as a diffusion barrier does not preclude the layer from being part of the claimed solder interconnect. Nothing in the claim requires the solder interconnect to consist exclusively of solder materials with no diffusion barrier properties.
Applicant’s assertion that the metal cap layer 105 cannot be considered part of the solder interconnect because it performs a diffusion-barrier function is, therefore, not persuasive. A component may perform a diffusion-barrier function while nevertheless forming part of a larger claimed interconnect structure. The relevant inquiry is whether the structure disclosed by Tsao satisfies the limitations of the claim, not whether Tsao uses the same terminology as the claim to describe the structure.
Furthermore, Applicant’s argument that solder 104 is not designed to touch conductive bump 103 does not distinguish the claimed subject matter. The claim requires the first solder interconnect to be coupled to and touch the second pillar portion. In Tsao, therefore, the solder interconnect comprising the metal cap layer 105 and the conductor 104 provides the claimed contact between the solder interconnect and the conductive bump 103.
Additionally, Tsao’s disclosure of Sn and SnPb as possible materials for metal cap layer 105 provides an express disclosure of a configuration in which the portion of the solder interconnect contacting conductive bump 103 comprises a solder material. Thus, Applicant’s assertion that Tsao’s metal cap layer 105 barrier properties necessarily excludes it from the claimed solder interconnect is not supported by Tsao.
Accordingly, Applicant has not identified a limitation of the claim that is absent from Tsao, and the rejection under 35 U.S.C. § 102 is maintained.
The applicants argue:
Tsao does not disclose that the first pillar interconnect portion and the second pillar interconnect portion are made of the same metal material. The conductive bump 103 and metal cap layer 105 are made of different materials because the metal cap layer 105 functions as a diffusion barrier, and, therefore, Tsao does not disclose the claimed first and second pillar interconnect portions comprising the same metal material.
The examiner responds:
The argument is not persuasive. Applicant’s argument improperly equates the two claimed pillar interconnect portions with the conductive bump 103 and the metal cap layer 105. The rejection, however, maps the claimed first and second pillar interconnect portions to the first and second portions of Tsao’s conductive bump 103, respectively, rather than to the conductive bump 103 and the metal cap layer 105.
Tsao (fig. 7C) expressly discloses that conductive bump 103 comprises a plurality of bump segments, including a first segment 1031 and a second segment 1032. Tsao further describes both segments as portions of the same conductive bump 103. In particular, paragraph [0033] describes the first and second portions 1031 and 1032 as segments of conductive bump 103, while paragraph [0028] identifies the material of conductive bump 103 as being selected from copper, gold, silver, zinc, bismuth, magnesium, antimony, indium, and alloys thereof.
Thus, Tsao’s disclosure of conductive bump 103 encompasses the first and second segments 1031 and 1032 as portions of the same conductive bump structure. The material disclosure for conductive bump 103, therefore, applies to the conductive bump portions, including the first and second portions 1031 and 1032. The fact that metal cap layer 105 may comprise a different material from conductive bump 103 is irrelevant to whether the first and second portions of conductive bump 103 comprise the same metal material.
The applicants argue:
The intermetallic compound (IMC) recited in the claims is inherent in the claimed solder interconnects. IMCs are formed during solder reflow when metal from the pillar interconnect and/or substrate interconnect diffuses into the solder. Formation of IMCs is well known to those of ordinary skill in the art and therefore the absence of an illustration or further description of the IMC in the specification does not prevent the claims from satisfying the requirements of 35 U.S.C. § 112(a).
The examiner responds:
The argument is not persuasive. The Examiner acknowledges that the specification (¶¶0038,0039) discloses that the solder “may include” an IMC and that the IMC “may be formed when metal from the pad and/or the pillar diffuses into the interconnect.” Thus, the issue is not whether the specification contains any reference to an IMC. Rather, the issue is whether the originally filed specification reasonably conveys to a person of ordinary skill in the art that the inventor was in possession of the claimed subject matter, namely, a solder that includes an IMC.
The Examiner has considered the JEDEC definition of “intermetallic compound (IMC),” which is being made part of the record. JEDEC defines an IMC as a substance formed when solder comes into contact with another metal at elevated temperatures. The definition further explains that the IMC is composed of constituents from the solder and the other metal. This technical definition is consistent with the specification’s disclosure that an IMC may form when metal from the pillar and/or substrate interconnect diffuses into the solder.
Importantly, however, the JEDEC definition does not establish that an IMC is necessarily present merely because solder and an adjacent metal structure are disclosed. Rather, the definition describes an IMC as a substance formed under particular circumstances, including contact between solder and another metal at elevated temperature. Thus, the definition supports the conclusion that the mere existence of a solder interconnect and adjacent metal does not, by itself, establish that the solder necessarily includes an IMC.
Here, the specification does not disclose the temperature at which the solder is processed or otherwise establish that the disclosed solder necessarily undergoes conditions resulting in formation of an IMC. Although the specification discloses solder reflow, it does not disclose a reflow temperature or other processing conditions that establish that an IMC necessarily forms.
Moreover, the specification itself characterizes IMC formation as a possibility. It states that the solder “may include” an IMC and that the IMC “may be formed” when metal diffuses into the solder. Such permissive language does not establish that the IMC necessarily exists in the disclosed embodiments.
Applicant’s assertion that IMC formation is inherent therefore is not persuasive. The fact that IMC formation is known to occur in solder structures, or that an IMC may form during solder reflow under appropriate conditions, does not establish that an IMC necessarily exists in the particular solder interconnects disclosed by the application.
A feature is not inherent merely because it is possible or commonly encountered. For inherency to establish the claimed limitation, the characteristic must necessarily be present in, or necessarily result from, the disclosed structure or process. Applicant has not established that the disclosed solder interconnects necessarily contain an IMC.
Accordingly, Applicant has therefore not demonstrated possession of the claimed solder including an IMC.
The applicants argue:
IMCs are formed during solder reflow when metal from the pillar and/or substrate interconnect diffuses into the solder and that such behavior is standard and well understood by those of ordinary skill in the art. The applicants therefore contend that no additional disclosure concerning formation of the IMC is necessary.
The examiner responds:
The argument is not persuasive.
The Examiner does not dispute that IMCs are known in the solder and semiconductor packaging arts. The JEDEC definition being made part of the record further confirms the technical understanding of an IMC as a material formed from constituents of solder and another metal under elevated-temperature conditions.
However, the general knowledge that IMCs can form during solder processing does not establish that an IMC necessarily forms in the particular solder interconnects disclosed in the present application.
As discussed above, the specification merely states that the solder “may include” an IMC and that the IMC “may be formed” when metal from the pillar and/or substrate interconnect diffuses into the solder. The specification does not identify the conditions under which the IMC necessarily forms.
Likewise, although the specification discloses solder reflow, it does not disclose the reflow temperature or other processing conditions sufficient to establish that the disclosed process necessarily produces the claimed IMC.
Thus, Applicant’s reliance upon the known nature of IMC formation establishes, at most, that IMC formation is a known possibility in solder processing. It does not establish that the IMC necessarily occurs in the disclosed embodiments or that the inventor possessed the claimed solder including an IMC as of the filing date.
Accordingly, Applicant’s reliance upon general knowledge in the art does not overcome the written-description rejection.
The applicants argue:
With respect to enablement, the claims merely require that the solder include an IMC and do not require any particular composition, morphology, thickness, or formation conditions for the IMC. The applicants therefore contend that a person of ordinary skill in the art would be able to make and use the claimed invention without undue experimentation.
The examiner responds:
The argument is not persuasive. The Examiner agrees that the claims do not expressly require a particular IMC composition, morphology, thickness, or formation condition. However, the absence of such additional limitations does not eliminate the requirement that the specification enable a person of ordinary skill in the art to make and use a solder that includes an IMC, as expressly required by the claims.
The JEDEC definition establishes the ordinary technical meaning of “IMC” and identifies circumstances associated with its formation. In particular, the definition identifies contact between solder and another metal at elevated temperature as the circumstance in which an IMC is formed. The application, however, does not provide sufficient guidance for determining or ensuring that the disclosed solder interconnects actually contain the claimed IMC.
The specification does not identify a particular IMC, does not provide a working example demonstrating a solder containing an IMC, and does not provide process conditions sufficient to ensure formation of an IMC. Although the specification discloses solder reflow, it does not disclose the reflow temperature or other conditions establishing that the claimed result will necessarily be obtained.
Applicant’s assertion that the claims do not require control of the IMC’s composition, morphology, thickness, or formation conditions therefore does not resolve the enablement deficiency. The issue is not whether Applicant must control every characteristic of the IMC. Rather, the issue is whether the specification provides sufficient guidance to enable the skilled artisan to make and use the claimed solder having the required characteristic, i.e., that the solder includes an IMC, without undue experimentation.
The fact that IMCs are known in the art does not, by itself, establish enablement of the full scope of the claimed subject matter. The specification must provide sufficient teaching to enable the claimed invention, and here the specification identifies only a possible mechanism for formation of an IMC without providing sufficient guidance to ensure that the claimed condition is obtained.
Accordingly, the applicants have not demonstrated that the limited disclosure concerning possible IMC formation enables the full scope of the claimed invention without undue experimentation. The enablement rejection under 35 U.S.C. § 112(a) is therefore maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp
September 6, 2026
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