DETAILED ACTION
This office action is in response to the amendments filed on October 2, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
Applicant’s amendments filed on October 2, 2025, in response to the office action mailed on 7/2/2025 have been fully considered. Accordingly, claims 1, 5-12 and 15-20 are currently pending in this application. Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Furthermore, claims 2-4 and 13-14 have been canceled.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/4/2021, 4/12/2023 and 10/18/2023 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-8, 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rho (US 2023/0307304).
With respect to Claim 1, Rho shows (Fig. 4) all aspects of the current invention including a substrate for a microelectronic assembly, comprising:
a core comprised of a single bulk glass (21; par 55)
a blind cavity (28) in the core (par 57)
an integrated circuit (IC) die (40) seated in the cavity (par 60)
a conductive via (inner vias 23 comprising conductive layers 241) through the core between the blind cavity and a side of the core (par 98-101)
a dielectric (253) and conductive traces (251) through the dielectric on either side of the core (par 103,137-138)
one or more conductive through-glass via (TGV) (outer vias 23 in opening 231) through the core (par 99-101)
With respect to Claim 6, Rho shows (Fig. 4) wherein the conductive traces comprise layers of metal through the dielectric and conductive vias coupling the layers.
With respect to Claim 7, Rho shows (Fig. 4) wherein at least one layer comprises a seed layer (282) in contact with the core
With respect to Claim 8, Rho shows (Fig. 4) wherein the conductive traces further comprise conductive pads (271) on exposed surfaces of the substrate configured to couple to another IC die or another substrate.
With respect to Claim 10, Rho shows (Fig. 4) further comprising conductive vias (252) through the dielectric on either side of the core electrically coupling the TGV with a first exposed surface (upper) of the substrate and an opposite second exposed surface (lower) of the substrate.
Claims 1, 6, 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2011/0304999)
With respect to Claim 1, Yu shows (Fig. 8) all aspects of the current invention including a substrate for a microelectronic assembly, comprising:
a core (30) comprised of a single bulk glass (32) (par 15)
a blind cavity (54) in the core (par 22)
an integrated circuit (IC) die (50) seated in the cavity (par 22)
a conductive via (inner vias 40) through the core between the blind cavity and a side of the core
a dielectric (10/18) and conductive traces (RDL 14/16) through the dielectric on either side of the core
one or more conductive through-glass via (TGV) (outer vias 40) through the core
With respect to Claim 6, Yu shows (Fig. 8) wherein the conductive traces (RDL 14/16) comprise layers of metal through the dielectric and conductive vias coupling the layers.
With respect to Claim 8, Yu shows (Fig. 8) wherein the conductive traces further comprise conductive pads (upper pads on top surface of dielectric 18) on exposed surfaces of the substrate configured to couple to another IC die or another substrate (46) (par 19)
With respect to Claim 9, Yu shows (Fig. 7) wherein a substrate having a core comprised of glass (glass core 30), the core comprises a blind cavity (54) including an integrated circuit (IC) die (50), conductive traces (interconnect structure 12) further comprise conductive pads (metal lines 14) on exposed surfaces of the substrate configured to couple to another IC die or another substrate, wherein the conductive pads on one exposed surface (upper surface) comprises copper pillars (vias 16) configured to form hybrid direct bonds with another IC die (see par 19) and the conductive pads (60) on another exposed surface (lower surface) comprises bond pads configured for flip-chip bumps (42).
With respect to Claim 10, Yu shows (Fig. 8) further comprising conductive vias (20) through the dielectric (10/18) on either side of the core electrically coupling the TGV with a first exposed surface (upper) of the substrate and an opposite second exposed surface (lower) of the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 11-12, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2011/0304999) in view of Pietambaram (US 2020/0006232).
With respect to Claim 5, Yu shows (Fig. 8) most aspects of the current invention. However, Yu fails shows wherein the IC die comprises through-silicon vias (TSVs) configured to electrically couple a surface of the substrate and an opposing surface of the substrate.
On the other hand, and in the same field of endeavor, Pietambaram teaches (See Fig 1) a substrate having a core comprised of glass (glass core 130), the core comprises a cavity (opening in glass) configured to seat an integrated circuit (IC) die (140), wherein the IC die comprises through-silicon vias (TSVs) (146) configured to electrically couple a surface of the substrate and an opposing surface of the substrate. Pietambaram teaches through-silicon vias (TSVs) are used to electrically couple circuitry on a first side of the integrated circuit (IC) die to an oppose side of the integrated circuit (IC) die through the integrated circuit (IC) die (par 148).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to include wherein the IC die comprises through-silicon vias (TSVs) configured to electrically couple a surface of the substrate and an opposing surface of the substrate in the device of Yu, as taught by Pietambaram because the through-silicon vias (TSVs) are used to electrically couple circuitry on a first side of the integrated circuit (IC) die to an oppose side of the integrated circuit (IC) die through the integrated circuit (IC) die.
Furthermore, one of ordinary skill in the art would have known that through-silicon vias (TSVs) are typically used in the packaging industry to provide electrical connections between circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to use through-silicon vias (TSVs) as claimed in the device of Yu, because through-silicon vias (TSVs) are well-known in the semiconductor art for their use as means to provide electrical connections between circuitry, as taught by Pietambaram, and implementing the through-silicon vias (TSVs) for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 11, Yu shows (Fig. 8) most aspects of the current invention including a substrate for a microelectronic assembly, comprising:
a substrate having a core (30) comprised of a single bulk glass (32) (par 15)
the core comprises a blind cavity (54) (par 22)
an integrated circuit (IC)/first die (50) located in the blind cavity (par 22)
one or more conductive vias (inner vias 40) between the blind cavity and a surface (bottom surface) of the core facing away from the first side of the substrate
the core further comprises one or more conductive through-glass via TGVs (outer vias 40) that facilitates electrical coupling between the first side of the substrate and an opposing second side (bottom side) of the substrate
However, Although Yu shows a second die (46) coupled to a first side (top side) of the substrate, Yu does not show a first IC die and a second IC die coupled to a first side of the substrate.
On the other hand, and in the same field of endeavor, Pietambaram teaches (See Fig 1) a substrate having a core comprised of glass (glass core 130), a first IC die (150A) and a second IC die (150b) coupled to a first side (top side) of the substrate, an integrated circuit (IC)/third die (140) located in a blind cavity (opening in glass), and wherein the IC die comprises through-silicon vias (TSVs) (146) configured to electrically couple a surface of the substrate and an opposing surface of the substrate. Pietambaram teaches the first IC die and the second IC die are used to communicatively couple each other by conductive traces within the third die (par 38).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to include a first IC die and a second IC die coupled to a first side of the substrate in the device of Yu, as taught by Pietambaram because the first IC die and the second IC die are used to communicatively couple each other by conductive traces within the third die.
With respect to Claim 12, Pietambaram teaches (Fig. 1) wherein the third IC die comprises a third side (upper) proximate to the first side and an opposing fourth side (lower) proximate to the second side, and the third IC die comprises a TSV (vias 146) providing electrical coupling between the third side and the fourth side
With respect to Claim 16, Pietambaram teaches (Fig. 1) wherein the first IC die and the second IC die are coupled to the substrate with first-level interconnects (FLI) (152; bumps) comprising hybrid direct bonds or flip-chip bumps (par 38).
With respect to Claim 17, Pietambaram teaches (Fig. 1) wherein the substrate is configured to be coupled to a component on the second side (bottom side) with mid-level interconnects (MLI) or second-level interconnects (SLI) (see par 40; build up layer 120 with conductive traces 125)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2011/0304999) in view of Pietambaram (US 2020/0006232) and in further view of Liu (US 2023/0063304).
With respect to Claim 15, Yu in view of Pietambaram shows most aspects of the current invention. However, the combination of references do not show wherein the first IC die is different from the second IC die in at least one functionality.
On the other hand, and in the same field of endeavor, Liu teaches (See Fig 1N) a substrate having a core comprised of glass (glass core 421), a first IC die (701) and a second IC die (702) coupled to a first side (top side) of the substrate, wherein the core comprises a cavity (opening in glass), and a third IC die (50) is located within the cavity, wherein the first IC die is different from the second IC die in at least one functionality (See par 65). Liu teaches the first die may be a central processing unit die, and the second die may include a graphic processing unit die to provide at least one high bandwidth memory die (par 65).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to include wherein the first IC die is different from the second IC die in at least one functionality in the device of Yu in view of Pietambaram, as taught by Liu because the first die may be a central processing unit die, and the second die may include a graphic processing unit die to provide at least one high bandwidth memory die.
Furthermore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to use wherein the first IC die is different from the second IC die in at least one functionality in the device of Yu in view of Pietambaram, because IC dies are well-known in the semiconductor art for their use as means to provide high speed communication between devices, as taught by Liu, and implementing the IC dies for their conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant's amendments filed on October 2, 2025, in response to the office action mailed on 7/2/2025 have been fully considered but they are not persuasive. Applicant’s arguments with respect to claims 1, 5-12, 15-17 have been considered but are moot because the new ground of rejections provided above which teaches the matters specifically challenged in the arguments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814