10DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, subspecies A (claims 1-4, 8-9, 11 and 13) in the reply filed on December 30, 2024 is acknowledged.
Claims 5-7, 10, 12 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 30, 2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on December 30, 2021 and May 22, 2023 were filed before the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, 2 are objected to because of the following informalities:
Claim 1, line 10, “a source contact and a drain contact” should be changed to --a source contact or a drain contact--;
Claim 2, line 2, “the source contact and the drain contact” should be changed to --the source contact or the drain contact--;
Claim 2, lines 3-4, “the source contact and the drain contact” should be changed to --the source contact or the drain contact--;
Claim 8, line 2, “the source contact and the drain contact” should be changed to --the source contact or the drain contact--; and
Claim 9, line 2, “the source contact and the drain contact” should be changed to --the source contact or the drain contact--.
These changes are necessary to resolve the grammatical incongruity caused by use of the phrase “one of a” with the conjunction “and.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-9 11 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2011/0084314 A1 to Or-Bach et al. (hereinafter “Or-Bach”).
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Figure 1: Annotated Fig. 51D of Or-Bach
Examiner is including an annotated Fig. 51D of Or-Bach for ease of reference and clarity regarding elements not labeled in the cited reference.
Regarding Claim 1, Or-Bach teaches an integrated circuit (IC) device, comprising: a support structure (Figs. 51C, D upper or lower Ox layers); a channel layer (Fig. 51D upper or lower STI oxide layers) over the support structure, the channel layer including a thin-film semiconductor material (Fig. 51D upper PMOS layer or lower NMOS layer); a first thin-film transistor (TFT) (Fig. 51D left 5102 or 5104 transistors); and a second TFT (Fig. 51D right 5102 or 5104 transistors), wherein: a channel region of the first TFT includes a first portion of the channel layer (Fig. 51D PMOS or NMOS layer below right 5102 or 5104, respectively), a channel region of the second TFT includes a second portion of the channel layer (Fig. 51D PMOS or NMOS layer below left 5102 or 5104, respectively), and one of a source contact and a drain contact of the first TFT is a shared contact that is also one of a source contact or a drain contact of the second TFT (Fig. 51D 5108 or 5110).
Regarding Claim 2, Or-Bach teaches the IC device according to claim 1, wherein the shared contact is in contact with a third portion of the channel layer (Fig. 51D PMOS region under 5108 or NMOS region under 5110), a second one of the source contact and the drain contact of the first TFT is in contact with a fourth portion of the channel layer (Fig. 51D 5114/PMOS region under left 5102 or NMOS region under left 5104), and a second one of the source contact and the drain contact of the second TFT is in contact with a fifth portion of the channel layer (Fig. 51D 5114/PMOS region under right 5102 or NMOS region under right 5104), and wherein the third portion of the channel layer is between the fourth portion of the channel layer and the fifth portion of the channel layer (Fig. 51D upper and lower sets of transistors 5102 and 5104, contact regions for 5108 and 5110 are between contact regions for 5114).
Regarding Claim 3, Or-Bach teaches the IC device according to claim 2, wherein the third portion of the channel layer is between the support structure and the shared contact (Fig. 51D upper transistors - channel region is between upper Ox layer and contact 5108).
Regarding Claim 4, Or-Bach teaches the IC device according to claim 2, wherein the shared contact is between the support structure and the third portion of the channel layer (Fig. 51D lower transistors - contact 5110 is between channel region and upper Ox layer).
Regarding Claim 8, Or-Bach teaches the IC device according to claim 2, wherein the fourth portion of the channel layer is between the support structure and the second one of the source contact and the drain contact of the first TFT (Fig. 51D lower transistors - NMOS region under left 5104 is between contact 5114 and lower Ox layer).
Regarding Claim 9, Or-Bach teaches the IC device according to claim 2, wherein the fifth portion of the channel layer is between the support structure and the second one of the source contact and the drain contact of the second TFT (Fig. 51D lower transistors - NMOS region under right 5104 is between contact 5114 and lower Ox layer).
Regarding Claim 11, Or-Bach teaches the IC device according to claim 1, wherein the first portion of the channel layer is between the support structure and a gate stack of the first TFT (Fig. 51D channel region below upper or lower left transistors 5102/5104 and upper or lower Ox layers, respectively).
Regarding Claim 13, Or-Bach teaches the IC device according to claim 1, wherein the second portion of the channel layer is between the support structure and a gate stack of the second TFT (Fig. 51D channel region below upper or lower right transistors 5102/5104 and upper or lower Ox layers, respectively).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0352256 A1 to Su et al. teaches a shared drain contact (Fig. 7 266).
US 2020/0126987 A1 to Rubin et al. teaches a shared drain contact (at least Fig. 1A 152/154).
US 11,114,471 B2 to Doyle et al. also teaches a shared drain contact (at least Fig. 3C 324).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Megan Parrish whose telephone number is (703)756-1983. The examiner can normally be reached Monday through Friday ET.
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MEGAN PARRISH
Examiner
Art Unit 2812
/Megan Parrish/Examiner, Art Unit 2812
/REEMA PATEL/Primary Examiner, Art Unit 2812
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