DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on June 10th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on June 10th, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 7-9, with respect to the rejections of claims 1-20 under 35 U.S.C 102 (a)(1) and/or 35 U.S.C 103(a) have been considered but are not persuasive in view of the following reasons.
Applicant argues that the insulator fins 355 of Sharma are separate and distinct from one another and Sharma fails to disclose each of the plurality of insulator fins continuous with one another (see pg. 9). The Examiner respectfully disagrees because Sharma discloses insulator structure 354 having one or more dielectric fins 355 and the exposed portion of insulator structure 354 connecting at least two dielectric fins 355 (see Sharma, Fig. 3B and [0036], [0040]). Therefore, each of dielectric fins 355 are continuous with one another by the exposed portion of insulator structure 354. For the above reasons, the examiner respectfully submits that Sharma discloses “each of the plurality of insulator fins continuous with one another” as recited in claims 1, 6, 11 and 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6, 9, and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHARMA et al. (WO 2019/182597) with Pub. No.: US 2020/0335635 A1 (for rejection purpose), hereinafter as Sharma.
Regarding claim 1, Sharma discloses an integrated circuit structure in Figs. 3A-3E, comprising: a plurality of insulator fins (pair of dielectric fins 355) above a substrate (substrate 352) (see Figs. 3A-3B and [0036]), each of the plurality of insulator fins continuous with one another (each of dielectric fins 355 continuous with one another by the exposed portion of the insulator structure 354) (see Fig. 3B and [0040]); a two-dimensional (2D) material layer (channel material layer 356 has at least 2 dimension in Fig. 3B) over the plurality of insulator fins (see Fig. 3B and [0036]); a gate dielectric layer (gate dielectric layer 364) on the 2D material layer (see Figs. 3B-3D and [0036-0037]); a gate electrode (gate electrode 358) on the gate dielectric layer; a first conductive contact (first conductive contact 374 at the front side in Fig. 3C) on the 2D material layer adjacent to a first side of the gate electrode (front side) (see Fig. 3C and [0040]); and a second conductive contact (second conductive contact 374 at the back side in Fig. 3C) on the 2D material layer adjacent to a second side of the gate electrode (back side), the second side opposite the first side (see Fig. 3C and [0040]).
Regarding claim 4, Sharma discloses the integrated circuit structure of claim 1, wherein the gate dielectric layer comprises a high-k gate dielectric layer in direct contact with the 2D material layer (see Fig. 3B and [0043]).
Regarding claim 6, Sharma discloses an integrated circuit structure in Figs. 3A-3E, comprising: a first gate electrode (gate electrode 362’) above a substrate (substrate 352) (see Figs. 3A-3B and [0036]), the first gate electrode comprising a plurality of conductive fins (a pair of protrusions of gate electrode 362’) over a plurality of insulator fins (pair of dielectric fins 355) (see Figs. 3A-3B and [0036]), each of the plurality of insulator fins continuous with one another (each of dielectric fins 355 continuous with one another by the exposed portion of the insulator structure 354) (see Fig. 3B and [0040]); a first gate dielectric layer (gate dielectric 364’) on the first gate electrode (see Figs. 3B, 3E and [0036], [0040-0041]); a two-dimensional (2D) material layer (channel material layer 356 has at least 2 dimensions in Fig. 3B) on the first gate dielectric layer (see Fig. 3B and [0036]); a second gate dielectric layer (gate dielectric 364) on the 2D material layer (see [0036]); a second gate electrode (gate electrode 362) on the second gate dielectric layer (see [0036]); a first conductive contact (first conductive contact 374 at front side in Fig. 3C) on the 2D material layer adjacent to a first side of the gate electrode (front side) (see Fig. 3C and [0040]); and a second conductive contact (second conductive contact 374 at back side in Fig. 3C) on the 2D material layer adjacent to a second side of the gate electrode (back side), the second side opposite the first side (see Fig. 3C and [0040]).
Regarding claim 9, Sharma discloses the integrated circuit structure of claim 6, wherein the gate dielectric layer comprises a high-k gate dielectric layer in direct contact with the 2D material layer (see Fig. 3B and [0043]).
Regarding claim 11, Sharma discloses a computing device (computing device 800), comprising: a board (motherboard 802); and a component (processor 804) coupled to the board (see Fig. 8 and [0095-0098]), the component including an integrated circuit structure in Figs. 3A-3E, comprising: a plurality of insulator fins (pair of dielectric fins 355) above a substrate (substrate 352) (see Figs. 3A-3B and [0036]), each of the plurality of insulator fins continuous with one another (each of dielectric fins 355 continuous with one another by the exposed portion of the insulator structure 354) (see Fig. 3B and [0040]); a two-dimensional (2D) material layer (channel material layer 356 has at least 2 dimension in Fig. 3B) over the plurality of insulator fins (see Fig. 3B and [0036]); a gate dielectric layer (gate dielectric layer 364) on the 2D material layer (see Figs. 3B-3D and [0036-0037]); a gate electrode (gate electrode 358) on the gate dielectric layer; a first conductive contact (first conductive contact 374 at front side in Fig. 3C) on the 2D material layer adjacent to a first side of the gate electrode (front side) (see Fig. 3C and [0040]); and a second conductive contact (second conductive contact 374 at back side in Fig. 3C) on the 2D material layer adjacent to a second side of the gate electrode (back side), the second side opposite the first side (see Fig. 3C and [0040]).
Regarding claim 12, Sharma discloses the computing device of claim 11, further comprising: a memory (DRAM/ROM) coupled to the board (see Fig. 8 and [0096]).
Regarding claim 13, Sharma discloses the computing device of claim 11, further comprising: a communication chip (communication chip 806) coupled to the board (see Fig. 8 and [0097]).
Regarding claim 14, Sharma discloses the computing device of claim 11, computing device of claim 11, further comprising: a camera coupled to the board (see Fig. 8 and [0096]).
Regarding claim 15, Sharma the computing device of claim 11, wherein the component is a packaged integrated circuit die (IC device 600) (see Fig. 6 and [0076-0078]).
Regarding claim 16, Sharma discloses a computing device (computing device 800), comprising: a board (motherboard 802); and a component (processor 804) coupled to the board (see Fig. 8 and [0095-0098]), the component including an integrated circuit structure in Figs. 3A-3E, comprising: a first gate electrode (gate electrode 362’) above a substrate (substrate 352) (see Figs. 3A-3B and [0036]), the first gate electrode comprising a plurality of conductive fins (a pair of protrusions of gate electrode 362’) over a plurality of insulator fins (pair of dielectric fins 355) (see Figs. 3A-3B and [0036]), each of the plurality of insulator fins continuous with one another (each of dielectric fins 355 continuous with one another by the exposed portion of the insulator structure 354) (see Fig. 3B and [0040]); a first gate dielectric layer (gate dielectric 364’) on the first gate electrode (see Figs. 3B, 3E and [0036], [0040-0041]); a two-dimensional (2D) material layer (channel material layer 356 has at least 2 dimension in Fig. 3B) on the first gate dielectric layer (see Fig. 3B and [0036]); a second gate dielectric layer (gate dielectric 364) on the 2D material layer (see [0036]); a second gate electrode (gate electrode 362) on the second gate dielectric layer (see [0036]); a first conductive contact (first conductive contact 374 at front side in Fig. 3C) on the 2D material layer adjacent to a first side of the gate electrode (front side) (see Fig. 3C and [0040]); and a second conductive contact (second conductive contact 374 at back side in Fig. 3C) on the 2D material layer adjacent to a second side of the gate electrode (back side), the second side opposite the first side (see Fig. 3C and [0040]).
Regarding claim 17, Sharma discloses the computing device of claim 16, further comprising: a memory (DRAM/ROM) coupled to the board (see Fig. 8 and [0096]).
Regarding claim 18, Sharma discloses the computing device of claim 16, further comprising: a communication chip (communication chip 806) coupled to the board (see Fig. 8 and [0097]).
Regarding claim 19, Sharma discloses the computing device of claim 16, computing device of claim 11, further comprising: a camera coupled to the board (see Fig. 8 and [0096]).
Regarding claim 20, Sharma the computing device of claim 16, wherein the component is a packaged integrated circuit die (IC device 600) (see Fig. 6 and [0076-0078]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over SHARMA et al. (WO 2019/182597) with Pub. No.: US 2020/0335635 A1 (for rejection purpose), hereinafter as Sharma as applied to claims 1 and 6 above, and in view of AFALIAN et al. (Pub. No.: US 2022/0115523 A1), hereinafter as Afalian.
Regarding claim 2, Sharma the integrated circuit structure of claim 1, but fails to disclose wherein the 2D material layer comprises a sulfide material selected from the group consisting of molybdenum sulfide (MoS2) and tungsten sulfide (WS2).
Afalian discloses an integrated circuit structure in Fig. 4 comprising a 2D material layer (semiconductor layer 20), wherein the 2D material layer comprises IGZO or a sulfide material selected from the group consisting of molybdenum sulfide (MoS2) and tungsten sulfide (WS-2) (see [0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the materials MoS2 or WS-2 of 2D material layer of Afalian for making the 2D material layer of Sharma because the disclosure of Afalian teaching that the material MoS2 or WS-2 can be alternative manufacturing choice for IGZO which was being used for 2D material layer of Sharma.
Regarding claim 3, Sharma the integrated circuit structure of claim 1, but fails to disclose wherein the 2D material layer comprises a selenide material selected from the group consisting of molybdenum selenide (MoSe2), tungsten selenide (WSe2), and indium selenide, or comprises MoTe2.
Afalian discloses an integrated circuit structure in Fig. 4 comprising a 2D material layer (semiconductor layer 20), wherein the 2D material layer comprises a selenide material selected from the group consisting of molybdenum selenide (MoSe2) and tungsten selenide (WSe2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the materials MoSe2 or WSe-2 of 2D material layer of Afalian for making the 2D material layer of Sharma because the disclosure of Afalian teaching that the material MoSe2 or WS-e2 can be alternative manufacturing choice for IGZO which was being used for 2D material layer of Sharma.
Regarding claim 7, Sharma the integrated circuit structure of claim 6, but fails to disclose wherein the 2D material layer comprises a sulfide material selected from the group consisting of molybdenum sulfide (MoS2) and tungsten sulfide (WS2).
Afalian discloses an integrated circuit structure in Fig. 4 comprising a 2D material layer (semiconductor layer 20), wherein the 2D material layer comprises IGZO or a sulfide material selected from the group consisting of molybdenum sulfide (MoS2) and tungsten sulfide (WS-2) (see [0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the materials MoS2 or WS-2 of 2D material layer of Afalian for making the 2D material layer of Sharma because the disclosure of Afalian teaching that the material MoS2 or WS-2 can be alternative manufacturing choice for IGZO which was being used for 2D material layer of Sharma.
Regarding claim 8, Sharma the integrated circuit structure of claim 6, but fails to disclose wherein the 2D material layer comprises a selenide material selected from the group consisting of molybdenum selenide (MoSe2), tungsten selenide (WSe2), and indium selenide, or comprises MoTe2.
Afalian discloses an integrated circuit structure in Fig. 4 comprising a 2D material layer (semiconductor layer 20), wherein the 2D material layer comprises a selenide material selected from the group consisting of molybdenum selenide (MoSe2) and tungsten selenide (WSe2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the materials MoSe2 or WSe-2 of 2D material layer of Afalian for making the 2D material layer of Sharma because the disclosure of Afalian teaching that the material MoSe2 or WS-e2 can be alternative manufacturing choice for IGZO which was being used for 2D material layer of Sharma.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over SHARMA et al. (WO 2019/182597) with Pub. No.: US 2020/0335635 A1 (for rejection purpose), hereinafter as Sharma as applied to claims 1 and 6 above, and in view of LILAK et al. (Pub. No.: US 2020/0006573 A1), hereinafter as Lilak.
Regarding claim 5, Sharma the integrated circuit structure of claim 1, but fails to disclose wherein the 2D material layer has a thickness at a location beneath the first and second conductive contacts that is greater than a thickness at a location beneath the gate electrode.
Lilak discloses an integrated circuit structure in Figs. 2A-2C comprising a 2D material layer (channel material 206 and source/drain regions 252) has a thickness at a location beneath first and second conductive contacts (thickness of source/drain regions 252) that is greater than a thickness at a location (thickness of channel material 206) beneath a gate electrode (gate electrode 212) (see Fig. 2B/2C and [0033-0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of 2D material layer (channel layer 356) of Sharma to have larger thickness beneath the first and second conductive contacts than beneath the gate electrode as same as the thickness of 2D material layer of Lilak because the modified structure would improve the contact structure for the source and drain and reduce leakage current in the channel during operation.
Regarding claim 10, Sharma the integrated circuit structure of claim 6, but fails to disclose wherein the 2D material layer has a thickness at a location beneath the first and second conductive contacts that is greater than a thickness at a location beneath the gate electrode.
Lilak discloses an integrated circuit structure in Figs. 2A-2C comprising a 2D material layer (channel material 206 and source/drain regions 252) has a thickness at a location beneath first and second conductive contacts (thickness of source/drain regions 252) that is greater than a thickness at a location (thickness of channel material 206) beneath a gate electrode (gate electrode 212) (see Fig. 2B/2C and [0033-0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of 2D material layer (channel layer 356) of Sharma to have larger thickness beneath the first and second conductive contacts than beneath the gate electrode as same as the thickness of 2D material layer of Lilak because the modified structure would improve the contact structure for the source and drain and reduce leakage current in the channel during operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818