DETAILED ACTION
This office action is in response to the amendment filed 10/16/2025.
Currently, claims 17-23 and 25 are pending. Claim 24 has been canceled.
Claim Objections
Applicant is advised that should claim 17 be found allowable, claim 25 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 17-23 and 25 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor had possession of the claimed invention.
Both independent claims 17 and 25 have been amended to recite “the line widths of respective lines of the plurality of parallel conductive lines being non-uniform with respect to one another”. This feature is not supported in the original disclosure.
Applicant cites para. [0042] in the remarks filed 10/16/2025 as supporting the claimed feature. However, para. [0042] is silent with regards to any difference in widths of the conductive lines. Rather, para. [0042] states that the spacings between conductive lines may be non-uniform. From para. [0042]: “The conductive lines 702 are shown as being evenly spaced, but it should be understood that other spacings are possible, and may be set according to the thickness and positioning of the sidewall spacers 402 and the thickness of the conductive lines 702.” This concept can be visualized with respect to FIG. 7. As seen in the annotated figure below, the spacing between conductive lines A and B is determined by the thickness of the spacers 402, while the spacings between conductive lines B and C is determined by the thickness of the lines 702. These thicknesses may be adjusted independently to create a line pattern with non-uniform spacings between conductive lines. The thicknesses of the lines themselves, however, would always be uniform. Thus, the cited limitation is considered to be new matter.
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Claims 17-23 and 25 are also rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The disclosure does not provide any description that would enable one of ordinary skill in the art to arrive at a structure in which the line widths of respective lines of the plurality of parallel conductive lines being non-uniform with respect to one another, as claimed. The line widths are determined in the step shown in FIG. 6 in which a conductive layer 602 is conformally deposited over spacers 402. From para. [0038] of the specification: “A conductive layer 602 is formed with a consistent thickness over the sidewall spacers 402.” In order for the line widths to be different, layer 602 would have to be deposited in a manner that results in some of the vertical portions of layer 602 having a thickness that is different than other vertical portions of layer 602. That would require a specialized process that is not disclosed. Thus, considering layer 602 is deposited conformally with a uniform thickness, one of ordinary skill in the art would not be enabled to arrive at a structure in which some of the conductive lines would have widths that are different from other conductive lines.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20, 22-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al. (US 2022/0336352) in view of Chen et al. (US 2020/0135537).
Pertaining to claim 17, Bae shows, with reference to FIG. 4, an integrated chip comprising:
an etch stop layer (201) (para. [0034]) on an underlying layer (200); and
a plurality of parallel conductive lines (210F-1, 210W-1) that are formed directly on a surface of the etch stop layer, each of the plurality of parallel conductive lines having a line width that is consistent to within one Angstrom (para. [0071], lines 3-4; the deposition process to form the parallel conductive lines may be ALD (para. [0060]) which, due to its self-limiting nature, controls the thickness of the deposited film at a singular molecular level; para. [0060] also states that the thickness of conductive layer 270, which defines line width, is “uniform along the outer surfaces of the various patterns”; the conductive lines thus have a controlled width that would not allow deviation from the straightness of the mandrel utilizes for the self-alignment), the line width being parallel to the surface of the etch stop layer and orthogonal to a height of the plurality of conductive lines (Bae shows the line width in a left-to-right direction, which is parallel to the surface of the etch stop layer and orthogonal to the height of the plurality of conductive lines), the line widths of respective lines of the plurality of parallel conductive lines being non-uniform with respect to one another (210F-1 vs. 210W-1).
Pertaining to claim 25, Bae shows an integrated chip comprising:
an etch stop layer (201) (para. [0034]);
an underlying layer (200); and
a plurality of parallel conductive lines (210F-1) that are formed directly on a surface of the etch stop layer, each of the plurality of parallel conductive lines having a line width that is consistent to within one Angstrom (para. [0071], lines 3-4; the deposition process to form the parallel conductive lines may be ALD (para. [0060]) which, due to its self-limiting nature, controls the thickness of the deposited film at a singular molecular level; para. [0060] also states that the thickness of conductive layer 270, which defines line width, is “uniform along the outer surfaces of the various patterns”; the conductive lines thus have a controlled width that would not allow deviation from the straightness of the mandrel utilizes for the self-alignment), the line width being parallel to the surface of the etch stop layer and orthogonal to the height of the plurality of conductive lines (Bae shows the line width in a left-to-right direction, which is parallel to the surface of the etch stop layer and orthogonal to the height of the plurality of conductive lines), the line widths of respective lines of the plurality of parallel conductive lines being non-uniform with respect to one another (210F-1 vs. 210W-1).
Bae fails to show, pertaining to both claims 17 and 25, a plurality of dielectric spacers, each between adjacent conductive lines of the plurality of parallel conductive lines.
However, Chen teaches in e.g. FIG. 5 that, for a similar fine-pitched metal line array, dielectric spacers comprising dielectric material 24 and air gaps 26 are formed in between the metal lines.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form dielectric spacers between the metal lines of Bae, as taught by Chen, with the motivation that such structures result in a lower capacitance between the tightly pitched metal lines (para. [0021]).
Pertaining to claim 18, Chen teaches the plurality of dielectric spacers are air-gapped spacers, each of the air-gapped spacers including a respective cavity (26) that is enclosed by pinched-off dielectric material (24) (para. [0046]).
Pertaining to claim 19, Chen teaches that the formation of the metal lines as a conformally deposited layer on sidewalls of a sacrificial structure allows for dimensions and pitches that are not attainable using photolithography (para. [0021] – [0022]).
Even so, the limitation “each conductive line of the plurality of parallel conductive lines has a respective thickness that is less than a minimum feature size of a photolithographic process used to fabricate the integrated chip” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Pertaining to claim 20, Bae shows the underlying layer includes one or more devices (NMOS, PMOS) that electrically interface with the parallel conductive lines (via contacts CNT).
Pertaining to claim 22, Bae shows the integrated chip has a plurality of layers connected by a set of vias (CNT).
Pertaining to claim 23, Bae shows the plurality of conductive lines include conformally deposited ruthenium (para. [0060], [0064]).
Pertaining to claim 24, Bae shows the plurality of conductive lines have a line width thickness that is equal to a pitch between two adjacent conductive lines (para. [0063]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Chen as applied to claim 17 above, and further in view of Gupta et al. (US 11,456,208).
Bae in view of Chen teaches the integrated chip of claim 17, wherein the plurality of dielectric spacers include a respective cavity (26) that is enclosed by pinched-off dielectric material (24) (Chen, para. [0046]).
Although Bae in view of Chen does not explicitly teach the plurality of dielectric spacers to be relative vacuum spacers, Gupta teaches in col. 14, lines 25-29 and FIG. 3E that air gap spacers formed by sealing off spaces between adjacent conductive lines with a pinched-off dielectric material may be either filled with a gaseous material or may be filled with nothing, creating a vacuum.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try the vacuum spacer, as taught by Gupta, for the air gap spacer of Bae in view of Chen, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Response to Arguments
The arguments with respect to the previous rejections under 35 U.S.C. 112 have been considered but are moot because the claims have been amended to remove the limitation “self-alignment”, which was associated with straightness.
Applicant's arguments with respect to the rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Applicant argues that Bae does not teach “the line widths of respective lines of the plurality of parallel conductive lines being non-uniform with respect to one another”, citing Bae’s preference for lines of uniform thickness.
In response, the cited passages only discuss one subset of the conductive lines. As seen in FIG. 4, there are other conductive lines that do not have the same width. Reference is made to the rejection above for further discussion.
Applicant further argues that Chen teaches conformal deposition, leading to uniform thicknesses. Applicant specifically states “A conformal deposition would not be non-uniform” (p. 8, line 2).
In response, Chen is not relied upon to teach the non-uniform thicknesses, as Bae already teaches such a feature. Furthermore, the Examiner agrees that a conformal deposition would not be non-uniform, and notes that conformal deposition is the same technique used in Applicant’s invention to deposit the metal for the metal lines. See FIG. 6 and para. [0038], specifically “A conductive layer 602 is formed with a consistent thickness over the sidewall spacers 402.” As indicated in the 35 U.S.C. 112(a) rejections above, Applicant does not disclose the non-uniform thicknesses, nor would one of ordinary skill in the art be enabled to arrive at such a feature.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896