DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments and amendments, see communication of 26 January 2026, with respect to the rejection(s) of the claim(s) in the previous Office action have been fully considered and are persuasive. Therefore, the previous rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kangguo Cheng et al. (US 9716170 B1), the details of which are presented below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, 13-14, 21-24, and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Kangguo Cheng et al. (US 9716170 B1; hereinafter D1) in view of Kangguo Cheng et al. (US 2017/0373162 A1; hereinafter D2).
PNG
media_image1.png
582
737
media_image1.png
Greyscale
Regarding Claim 1, D1 teaches a semiconductor structure (Annotated Fig. 10), comprising:
at least one vertical fin (206: C6:L58--C7:L14);
a bottom source/drain layer (402; C7:L23-L34) disposed on a semiconductor substrate (202; silicon; C6:L43--L57), the bottom source/drain layer (402) being adjacent a bottom portion (bottom) of the at least one vertical fin (206), wherein the bottom source/drain layer (402) comprises a plurality of different heights, and wherein the plurality of different heights comprise a first height (h1) and a second height (h2) greater than the first height;
a bottom spacer layer (702; C7:L49--L53); and
a gate structure (802/804; C7:L34--L48) disposed on one or more sides of the at least one vertical fin (206), wherein a portion of the at least one vertical fin (upper portion of 206) contacts a top spacer layer (902; C8:L13--L16) disposed on the gate structure (802/804),
wherein an upper surface of the at least one vertical fin (upper surface of 206) is disposed below an upper surface of at least a portion of the top spacer layer (top of 902), and wherein a bottom surface of the at least one vertical fin (bottom of 206) is disposed below an upper surface of the bottom spacer layer (top of 702) and above the bottom surface of the bottom spacer layer (bottom of 702) disposed on a portion of the bottom source/drain layer (402)(as shown in annotated Fig. 10);
wherein the second height (h2) is one of at and below a lowermost surface of the gate structure (h2 is at or below the lowermost surface of 802/804); and
wherein the second height (h2) corresponds to a portion of the bottom source/drain layer (402) disposed under and contacting the bottom surface of the at least one vertical fin (h2 corresponds to the bottom of 206 contacting the top of 402).
D1 is silent regarding wherein the bottom source/drain layer (402) is an epitaxial layer, and
wherein a contact structure disposed on the epitaxial layer, wherein the contact structure is disposed on respective surfaces of the epitaxial layer at the plurality of different heights;
a shallow trench isolation region disposed on opposite sidewalls of the epitaxial layer and the semiconductor substrate and below a bottom surface of a bottom spacer layer.
PNG
media_image2.png
485
694
media_image2.png
Greyscale
In the same vertical FET field of endeavor, D2 teaches a similar vertical FET (annotated Fig. 12; ¶0007). D2 teaches a lower epitaxial source/drain (120; ¶0037) including a plurality of different heights (including protruding portions 145 {¶0092} which correspond to a height of the epitaxial source/drain {S/D} under the fin 141 {¶0049}; as shown in view of Fig. 9 and Fig. 7), wherein a contact structure (230; ¶0095) is disposed on respective surfaces of the epitaxial layer at the plurality of different heights (height of 120 and 145, respectively, as shown in Fig. 12);
a shallow trench isolation region (130; ¶0038) disposed on opposite sidewalls of the epitaxial layer (120) and the semiconductor substrate (110; ¶0036) and below a bottom surface of a bottom spacer layer (170; ¶0059).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize epitaxy for the bottom source/drain layer (402) of D1 (as done in D2) because of the art-recognized suitability and interchangeability between epitaxial in-situ doping and ex-situ doping (D2; ¶0037) for the purpose of a bottom source/drain feature of a vertical FET.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the protrusions and contact structure features of D2 above in the device of D1 in order to increase the contact area between the contact structure and epitaxial S/D compared to a flat interface (D2; ¶0095).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a shallow trench isolation region disposed on opposite sidewalls of the epitaxial layer and the semiconductor substrate and below a bottom surface of a bottom spacer layer (as in D2) in the device of D1 in order to provide electrical isolation to the bottom source/drain regions for individual vertical fin FETs (as disclosed in D2; ¶0038).
Regarding Claim 2, modified D1 teaches the semiconductor structure of claim 1, wherein the epitaxial layer (402) comprises a bottom source/drain region of at least one vertical transport field-effect transistor (402 is a bottom source/drain region and as modified by D2 is epitaxial).
Regarding Claim 3, modified D1 teaches the semiconductor structure of claim 2, further comprising an additional epitaxial layer (1002/1004; C8:L17—L32) disposed on a top portion of the at least one vertical fin (top of 206), wherein the top S/D layer comprises a top source/drain region of the at least one vertical transport field-effect transistor (as described in C8:L17—L32).
Regarding Claim 4, modified D1 teaches the semiconductor structure of claim 3, wherein the gate structure (802/804) is disposed between the bottom (402) and top (1002/1004) source/drain regions (as shown in D1 Fig. 10).
Regarding Claim 6, modified D1 teaches the semiconductor structure of claim 1, wherein a width of the portion of the epitaxial layer (402) disposed under and contacting the bottom surface of the at least one vertical fin (206) is the same or substantially the same as a width of the at least one vertical fin (206) (as shown in D1 annotated Fig. 10).
Regarding Claim 7, modified D1 teaches the semiconductor structure of claim 1, wherein the first height (h1) corresponds to a portion of the epitaxial layer (402) disposed between the at least one vertical fin (left 206) and at least one other vertical fin (216).
Regarding Claim 8, modified D1 teaches the semiconductor structure of claim 7, wherein the bottom spacer layer (702) is disposed on the portion of the epitaxial layer (402) between the at least one vertical fin (206) and the at least one other vertical fin (216) (as shown in annotated D1 Fig. 10).
Regarding Claim 9, modified D1 teaches the semiconductor structure of claim 1, wherein the first height (h1) and the second height (h2) are arranged in a repetitive pattern comprising the first height (h1) followed by the second height (h2) along a given direction of the epitaxial layer (402) (as shown in D1 annotated Fig. 10; wherein the pattern from left to right is h1→ h2 → h1…).
Regarding Claim 10, D1 teaches a vertical transport field-effect transistor structure (annotated D1 Fig. 10), comprising:
at least one vertical channel region (206: C6:L58--C7:L14);
a bottom source/drain region (402; C7:L23-L34) adjacent a bottom portion of the at least one vertical channel region (bottom portion of 206), wherein the bottom source/drain region (206) comprises a plurality of different heights, and wherein the plurality of different heights comprise a first height (h1) and a second height (h2) greater than the first height (h1);
a top source/drain region (1002/1004; C8:L17—L32) disposed on a top portion of the at least one vertical channel region (top of 206);
a gate structure (802/804; C7:L34--L48) disposed on one or more sides of the at least one vertical channel region (206), wherein a portion of the at least one vertical channel region (top of 206) contacts a top spacer layer (902; C8:L13--L16) disposed on the gate structure (802/804), wherein an upper surface of the at least one vertical channel region (top of 206) is disposed below an upper surface of at least a portion of the top spacer layer (top of 902), and wherein a bottom surface of the at least one vertical channel region (bottom of 206) is disposed below an upper surface of a bottom spacer layer (upper surface of a bottom spacer 702; C7:L49--L53) and above a bottom surface of the bottom spacer layer (bottom of 702) disposed on a portion of the bottom source/drain region (402) (as shown in annotated Fig. 10);
a semiconductor substrate (202; silicon; C6:L43--L57);
wherein the second height (h2) is one of at and below a lowermost surface of the gate structure (bottom of 802/804); and
wherein the second height (h2) corresponds to a portion of the bottom source/drain region (402) disposed under and contacting the bottom surface of the at least one vertical channel region (bottom of 206) (as shown in annotated Fig. 10).
D1 is silent regarding a contact structure disposed on the bottom source/drain region (402), wherein the contact structure is disposed on respective surfaces of the bottom source/drain region at the plurality of different heights; and a shallow trench isolation region disposed on opposite sidewalls of an epitaxial layer (wherein the bottom source/drain region 402 is an epitaxial layer) and the semiconductor substrate and below a bottom surface of a bottom spacer layer.
In the same vertical FET field of endeavor, D2 teaches a similar vertical FET (annotated Fig. 12; ¶0007). D2 teaches a lower epitaxial source/drain (120; ¶0037) including a plurality of different heights (including protruding portions 145 {¶0092} which correspond to a height of the epitaxial source/drain {S/D} under the fin 141 {¶0049}; as shown in view of Fig. 9 and Fig. 7), wherein a contact structure (230; ¶0095) is disposed on respective surfaces of the epitaxial layer at the plurality of different heights (height of 120 and 145, respectively, as shown in Fig. 12);
a shallow trench isolation region (130; ¶0038) disposed on opposite sidewalls of the epitaxial layer (120) and the semiconductor substrate (110; ¶0036) and below a bottom surface of a bottom spacer layer (170; ¶0059).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize epitaxy for the bottom source/drain layer (402) of D1 (as done in D2) because of the art-recognized suitability and interchangeability between epitaxial in-situ doping and ex-situ doping (D2; ¶0037) for the purpose of a bottom source/drain feature of a vertical FET.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the protrusions and contact structure features of D2 above in the device of D1 in order to increase the contact area between the contact structure and epitaxial S/D compared to a flat interface (D2; ¶0095).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a shallow trench isolation region disposed on opposite sidewalls of the epitaxial layer (that is the bottom source/drain region) and the semiconductor substrate and below a bottom surface of a bottom spacer layer (as in D2) in the device of D1 in order to provide electrical isolation to the bottom source/drain regions for individual vertical fin FETs (as disclosed in D2; ¶0038).
Regarding Claim 11, modified D1 teaches the vertical transport field-effect transistor structure of claim 10, wherein the first height (h1) and the second height (h2) are arranged in a repetitive pattern comprising the first height (h1) followed by the second height (h2) along a given direction (from left to right) of the bottom source/drain region (402) (as shown in D1 annotated Fig. 10; wherein the pattern from left to right is h1→ h2 → h1…).
Regarding Claim 13, modified D1 teaches the vertical transport field-effect transistor structure of claim 10, wherein the first height (h1) corresponds to a portion of the bottom source/drain region (402) disposed between the at least one vertical channel region (206) and at least one other vertical channel region (216).
Regarding Claim 14, modified D1 teaches the vertical transport field-effect transistor structure of claim 13, further comprising the bottom spacer layer (702) disposed on the portion of the bottom source/drain region (402) between the at least one vertical channel region (206) and the at least one other vertical channel region (216) (as shown in annotated D1 Annotated Fig. 10).
Regarding Claim 21, D1 teaches a semiconductor structure (Annotated Fig. 10), comprising:
at least one vertical fin (206: C6:L58--C7:L14);
a bottom source/drain layer (402; C7:L23-L34) disposed on a semiconductor substrate (202; silicon; C6:L43--L57), the bottom source/drain layer (402) being adjacent a bottom portion (bottom) of the at least one vertical fin (206), wherein the bottom source/drain layer (402) comprises a first height (h1) and a second height (h2) greater than the first height;
a bottom spacer layer (702; C7:L49--L53); and
a gate structure (802/804; C7:L34--L48) disposed on one or more sides of the at least one vertical fin (206), wherein a portion of the at least one vertical fin (upper portion of 206) contacts a top spacer layer (902; C8:L13--L16) disposed on the gate structure (802/804), wherein an upper surface of the at least one vertical fin (upper surface of 206) is disposed below an upper surface of at least a portion of the top spacer layer (top of 902), and wherein a bottom surface of the at least one vertical fin (bottom of 206) is disposed below an upper surface of the bottom spacer layer (top of 702) and above the bottom surface of the bottom spacer layer (bottom of 702) disposed on a portion of the bottom source/drain layer (402)(as shown in annotated Fig. 10);
wherein the second height (h2) is one of at and below a lowermost surface of the gate structure (h2 is at or below the lowermost surface of 802/804); and
wherein the second height (h2) corresponds to a portion of the bottom source/drain layer (402) disposed under and contacting the bottom surface of the at least one vertical fin (h2 corresponds to the bottom of 206 contacting the top of 402).
D1 is silent regarding wherein the bottom source/drain layer (402) is an epitaxial layer, and
wherein a contact structure disposed on the epitaxial layer, wherein the contact structure is disposed on respective surfaces of the epitaxial layer at the first height and the second height;
a shallow trench isolation region disposed on opposite sidewalls of the epitaxial layer and the semiconductor substrate and below a bottom surface of the bottom spacer layer.
In the same vertical FET field of endeavor, D2 teaches a similar vertical FET (annotated Fig. 12; ¶0007). D2 teaches a lower epitaxial source/drain (120; ¶0037) including a plurality of different heights (including protruding portions 145 {¶0092} which correspond to a height of the epitaxial source/drain {S/D} under the fin 141 {¶0049}; as shown in view of Fig. 9 and Fig. 7), wherein a contact structure (230; ¶0095) is disposed on respective surfaces of the epitaxial layer at the plurality of different heights (height of 120 and 145, respectively, as shown in Fig. 12);
a shallow trench isolation region (130; ¶0038) disposed on opposite sidewalls of the epitaxial layer (120) and the semiconductor substrate (110; ¶0036) and below a bottom surface of a bottom spacer layer (170; ¶0059).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize epitaxy for the bottom source/drain layer (402) of D1 (as done in D2) because of the art-recognized suitability and interchangeability between epitaxial in-situ doping and ex-situ doping (D2; ¶0037) for the purpose of a bottom source/drain feature of a vertical FET.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the protrusions and contact structure features of D2 above in the device of D1 in order to increase the contact area between the contact structure and epitaxial S/D compared to a flat interface (D2; ¶0095).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a shallow trench isolation region disposed on opposite sidewalls of the epitaxial layer and the semiconductor substrate and below a bottom surface of a bottom spacer layer (as in D2) in the device of D1 in order to provide electrical isolation to the bottom source/drain regions for individual vertical fin FETs (as disclosed in D2; ¶0038).
Regarding Claim 22, modified D1 teaches the semiconductor structure of claim 21, wherein the epitaxial layer (402) comprises a bottom source/drain region of at least one vertical transport field-effect transistor (as described in D1 C7:L23-L34).
Regarding Claim 23, modified D1 teaches the semiconductor structure of claim 2, further comprising an additional epitaxial layer (1002/1004; C8:L17—L32) disposed on a top portion of the at least one vertical fin (top of 206), wherein the top S/D layer comprises a top source/drain region of the at least one vertical transport field-effect transistor (as described in C8:L17—L32).
Regarding Claim 24, modified D1 teaches the semiconductor structure of claim 21, wherein the first height (h1) corresponds to a portion of the epitaxial layer (402) disposed between the at least one vertical fin (206) and at least one other vertical fin (216).
Regarding Claim 26, modified D1 teaches the semiconductor structure of claim 21, wherein the first height (h1) and the second height (h2) are arranged in a repetitive pattern comprising the first height (h1) followed by the second height (h2) along a given direction of the epitaxial layer (402) (as shown in D1 annotated Fig. 10; wherein the pattern from left to right is h1→ h2 → h1…).
Regarding Claim 27, modified D1 teaches the semiconductor structure of claim 21, wherein a width of the portion of the epitaxial layer (402) disposed under and contacting the bottom surface of the at least one vertical fin (206) is the same or substantially the same as a width of the at least one vertical fin (206) (as shown in annotated D1 Fig. 10).
Regarding Claim 28, modified D1 teaches the semiconductor structure of claim 23, wherein the gate structure (802/804) is disposed between the bottom source/drain region (402) and the top source/drain region (1002/1004) (as shown in D1 Fig. 10).
Regarding Claim 29, modified D1 teaches the vertical transport field-effect transistor structure of claim 10, wherein a width of the portion of the bottom source/drain (402) region disposed under and contacting the bottom surface of the at least one vertical channel region (206) is the same or substantially the same as a width of the at least one vertical channel region (206) (as shown in Fig. 10).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898