DETAILED ACTION
Claims 1, 3-9, 11-15, and 18-32 are pending.
Claims 1, 3-9, 18, and 30-32 have been examined.
Claims 11-15 and 19-29 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 6, 2025, has been entered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections/Recommendations
Claim 1 is objected to because of the following informalities:
In lines 7-9, the grammar is incorrect because the action of loading data does not contain…data. The loaded data would contain the data. Applicant could reword to --that loading data in excess of…will load the designated data…--, or to
--…that data loaded in excess of…will contain the designated data…--.
Insert --and-- at the end of part (a)(i).
Insert --and-- at the end of the last line on page 2.
In part (b), the use of “determine that” and “if so” appears to conflict because “determine that” is confirming that the condition is true and does not leave open the possibility of it being false. Applicant can either continue using “determine that” and delete “if so,”, or applicant can replace “that” with --whether--.
In claim 6, if the given load claimed is the same as that in claim 1, it is recommended that applicant claim --the given-- instead of “a given”.
In claim 8, it is recommended that applicant replace “to be loaded by” with --of-- to match the language used in claim 1 (unless applicant is referring to another given load instruction than the one set forth in claim 1).
Claim 18 is objected to because of the following informalities:
Insert --and-- at the end of line 9.
Claim 18 also includes similar issues as claim 1. Please similarly correct. Note, however, that applicant should amend to remove “if so” as opposed to changing “that” to --whether-- because the latter will result in a contingent limitation in a method claim, which may open the claim up to additional and/or broader prior art rejections (MPEP 2111.04(II)).
Withdrawn claims 11-15 and 19-29 are objected to because the claim text is not shown, as required by 37 CFR 1.121(c).
In claim 30, while “the load data memory address of the designated data” is currently clear, it may become unclear if applicant resolves 112(b) issues in a manner recommended below. As such, it is recommended that applicant review this language after other changes are made to make sure it is clear which memory address and designated data applicant is referring to.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claims 1 and 18, “a fat load storage structure holding a plurality of enrolled data”. From page 9 of applicant’s response, this structure corresponds to the combination of FIGs.6-7. From FIGs.6-7 and pages 18 and 20 of the specification, the structure is interpreted to include a memory to store data (FIG.6) and registers, and equivalents thereof. If applicant does not wish to be so limited, the examiner recommends that applicant claim a “fat load storage” (omit the generic “structure”) or a “fat load storage circuit” since use of “circuit” avoids 112(f) interpretation (MPEP 2181(I)(A)).
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Referring to claim 18, even though a given run of the method may choose only one of a normal load and a fat load, the method still requires that the architecture choose between these two types of loads. That is, both loads must be implemented in the system and a choice among them must occur.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 31-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 31-32 now set forth that the fat load storage structure is non-cache memory. As far as the examiner can tell, this is new matter not originally supported by the specification. In particular, it appears that applicant’s fat load storage structure can be considered cache memory based on the broad definition of cache, which per Merriam-Webster (see attached), is defined as “a computer memory with very short access time used for storage of frequently or recently used instructions or data” (p.1) and/or as “a part of a computer's memory where information is kept so that the computer can find it very quickly” (p.3). It is the examiner’s understanding that additional data from cache memory is stored in the fat load storage structure so that the data can be more quickly accessed by a subsequent load in the future, thereby allowing the subsequent load to skip accessing the cache memory. In other words, the fat load storage structure acts as a faster, lower-level cache than the claimed cache memory. By definition, the structure is therefore cache memory. Just because applicant doesn’t explicitly label the structure as cache doesn’t mean it can’t be considered cache. The examiner recommends positively claiming disclosed characteristics of the structure that are different from what would be found in a traditional cache.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-6, 7-9, and 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 1, lines 7-8, “the designated data of the given load instruction”. Designated data of the given load instruction was not previously set forth. Only designated data of a load instruction was set forth in lines 3-4. There is no clear link between the given load instruction and the load instruction of lines 3-4. The examiner’s recommendation would be to claim --processing circuitry operating to receive a plurality of load instructions, each of the plurality of load instructions specifying a load data memory address of a designated data to be loaded from the cache memory to a specified destination register in the processor;--. Then, applicant could insert --of the plurality of load instructions-- after “a given load instruction” in lines 6-7. By stating that the given load is of the plurality, there will be basis for the designated data of the given load because each load of the plurality specifies an address of a designated data.
In claim 1, lines 8-9, “the designated data of another load instruction”, for similar reasoning. Assuming applicant adopts the recommendation above, applicant could similarly insert --of the plurality of load instructions-- after “another load instruction” in line 9.
In claim 1, line 11, “the enrolled data” since there is a plurality of enrolled data followed by an enrolled data in line 10. Applicant could claim this as a first enrolled data, or a given enrolled data.
In claim 11, lines 15-16 and again in lines 18-19, each instance of “the designated data for the first load instruction” for similar reasoning given above.
In claim 1, line 20, “the additional data”, since there is additional data in part (a)(i) and more additional data in part (a)(ii)(a). The examiner recommends rewording to --the additional data for another load instruction--, or claiming this additional data as --first additional data--.
In claim 1, lines 20-21, “the load data memory address of a load instruction using the additional data”. No such address for this particular load instruction was previously set forth.
In claim 1, line 21, “the data of the fat load” since the fat load includes designated data and additional data. It appears applicant means “the designated data for the first load instruction of the fat load”, which itself lacks basis as asserted above. Nevertheless this is how “the data” is interpreted for purposes of prior art examination.
In claim 1, on page 2, last line, “the additional data” for similar reasoning given above.
In claim 1, last paragraph, each instance of “the designated data of the second load instruction” for similar reasoning given above.
In claim 4, “the given load instruction”, which could refer to that in line 2-3 or to that in claim 1. The examiner recommends replacing “a” with --the-- in line 2.
In claim 5, “the given load instruction”, which could refer to that in line 2-3 or to that in claim 1. The examiner recommends replacing “a prediction value for a given” with --the prediction value for the given-- in line 2.
In claims 7-8, each instance of “the given load instruction” for similar reasoning given above.
In claim 8, each instance of “the execution of the given load instruction” since there is an execution in line 3, but also an earlier execution in claim 7.
In claim 18, line 5, “the processor”.
In claim 18, any term listed above in claim 1 that is also in claim 18. Basis is lacking for similar reasoning.
In claim 30, “the load instruction” because there are multiple load instructions in claim 1.
In claim 30, “the identity of the base register”. What is the identity of the base register and how does it differ from the base register itself?
Claim 18 is further indefinite because applicant is not clearly claiming a method, let alone a method of operating an architecture. Instead applicant is claiming an architecture and a method whose effect is causing the architecture to perform actions. However, no method step(s) to realize the effect is/are claimed. Thus, the scope of the method is unknown. One possible fix would be to change line 12 to --the method comprising:-- and change (a) and (b) to recite
--processing, by the computer architecture, a…load instruction…--.
Claims 3-9 and 30-32 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 18, and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Eyole et al., U.S. Patent Application Publication No. 2021/0349721 A1, in view of Alexander et al., U.S. Patent No. 6,131,155.
Referring to claim 1, Eyole has taught an architecture of a computer processor (e.g. FIG.2A, 50) having registers (from FIG.2A, registers exist so they can be read by register read stage 62) and operating in conjunction with a cache memory (from paragraph [0040], a cache hit would cause data to be retrieved from data cache), the architecture comprising:
processing circuitry operating to receive a load instruction specifying a load data memory address of a designated data to be loaded from the cache memory to a specified destination register in the processor (see the abstract and paragraph [0040]. The processing circuitry will receive a load instruction which loads designated data to a register from a specified memory address);
a prediction circuit (e.g. FIG.2A, 66) operating to generate a prediction value for a given load instruction (abstract), the prediction value indicating a likelihood that loading data in excess of the designated data of the given load instruction from the cache memory will contain the designated data of another load instruction (the prediction value indicates whether a given load is likely to coalesce with another load (e.g. FIG.6, 202)). If so, the given load is sent to the pending loads buffer 68 (FIG.6, 204). If a given load is predicted to coalesce with another load, this means that extra data in the cache line loaded by this load is likely to be used by the other load, thereby allowing for suppression of the other load (FIG.6, 210) (see paragraphs [0036] and [0040]-[0042]);
a fat load storage structure holding a plurality of enrolled data (from FIG.2A and paragraph [0040], fat load storage structure (at least 80, 82, and 84) stores data, some of which is the extra data loaded by the given load. With respect to 112(f) interpretation, the buffer portion 80/84 is deemed an equivalent of registers, which corresponds to how applicant’s structure has been interpreted. From MPEP 2183, a buffer such as that taught by Eyole is not excluded by applicant’s specification and it performs the claimed function of holding data in substantially the same way as applicant’s structure (in both cases, data can be quickly read and written in multi-bit storage));
wherein the processing circuitry operates to:
(a) process a first load instruction according to its prediction value to choose between:
(i) a normal load loading from the cache memory the designated data for the first load instruction into the specified destination register (from paragraphs [0025] and [0038], when a first load instruction is not predicted to coalesce, it bypasses the pending loads buffer and is handled directly by the load unit 72);
(ii) a fat load loading from the cache memory: (a) the designated data for the first load instruction into the specified destination register (when the first load instruction is predicted to coalesce, it goes to the pending loads buffer. When it becomes the oldest load in the buffer, and its indicator (FIG.2B, 92) is not set, it performs a fat load, where a cache line chunk with a series of data items, including the designated item, is loaded (e.g. paragraphs [0017], [0036], [0041], [0049], etc.). As is known with a load, the designated data is stored to a destination register) and (b) additional data for another load instruction and placing the additional data into the fat load storage structure (as described, the first load is a fat load that also loads additional data for another load and stores that data into the fat load storage structure);
wherein the processing circuitry performs a fat load without requiring a comparison using the load data memory address of a load instruction using the additional data, and without using the data of the fat load (a fat load is performed by the oldest load in the pending loads buffer whose indicator 92 is also not set. This fat load is performed simply due to the age and indicator, and not based on a comparison to another memory address and without using the data of the fat load (i.e., since the fat load causes the fat data to be loaded, the fat data cannot be used to perform the fat load (since it doesn’t yet have access to the fat data that is not yet loaded));
(b) process a second load instruction to determine that the designated data of the second load instruction is in the fat load storage structure and if so, to obtain the designated data for the second load instruction from the fat load storage structure without accessing the cache memory (the second load instruction would be one that is coalesced with the first load in pending loads buffer 68. For instance, from FIG.2B, the first load would be that in the bottom (oldest) entry of the buffer, and the second load would be in one of the other entries of the buffer whose address matches the address in the bottom entry. In such a case, when the second load becomes the oldest load (moves to bottom entry), its coalesce bit 92 is detected as being set, and the processing circuitry gets the designated data for the second load from buffer 80, which stores the fat load of data loaded by the first load. The designated data is extracted from that buffer and sent to multiplexer 86 (see at least paragraphs [0041]-[0043]). Because the data is obtainable from buffer 80, the cache memory access that would otherwise be performed by the second load is suppressed (FIG.6, 210)).
Eyole has not taught an enrolled data linked to a data identifier providing a data memory address for the enrolled data, where the additional data placed into the fat load storage structure is placed together with a data identifier of the additional data, and where the second load is processed by consulting a data identifier linked to a data in the fat load storage structure to determine that the designated data of the second load instruction is in the fat load storage structure. Eyole is generally silent on how the data in the buffer is matched to a current load such that the current load’s cache access can be suppressed. However, Alexander has taught a similar system in which buffer details are set forth. Specifically, when a load in Alexander reads consecutive additional data beyond its own data from memory (fat load), the additional data is stored in a buffer 201 and an address of the first data item of the additional data is stored in register 207 (since the additional data is consecutive, each of the additional data is each located at a different offset from the address of the first data item within the buffer) (see column 7, lines 51-67). This address is stored so that it may be consulted (i.e., compared to a subsequent load address) to determine if the subsequent load’s data is in the buffer (column 6, lines 20-32, and FIG.4, top step in the right column of steps). One of ordinary skill in the art would have recognized that, among a series of additional data loaded, a subsequent load must somehow be linked to one of the additional data so as to correctly load what is necessary. Alexander provides a simple approach of storing a single data identifier that provides a memory address that represents all consecutive additional data items in the buffer. As a result, in order to use minimal storage to link the additional data in the buffer to their addresses so as to correctly pair them with a subsequent load that indicates one of those addresses, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Eyole such that an enrolled data is linked to a data identifier providing a data memory address for the enrolled data, where the additional data placed into the fat load storage structure is placed together with a data identifier of the additional data, and where the second load is processed by consulting a data identifier linked to a data in the fat load storage structure to determine that the designated data of the second load instruction is in the fat load storage structure. In the resulting combination, note that the address register (Alexander 207) would be considered part of the fat load storage structure of Eyole. Regarding 112(f) interpretation, this address register is memory, which corresponds to how applicant’s structure has been broadly interpreted.
Eyole has also not taught that the normal load loads without loading additional data from the cache memory to the fat load storage structure. It is not entirely clear, but every load in Eyole may load additional data in a cache line chunk (paragraphs [0017], [0036], [0041], and [0049]), though paragraph [0017] merely says this is typical. However, Alexander has taught that when a given load is not predicted to satisfy a subsequent load by loading additional data, the given load is performed normally without loading additional data (see column 7, lines 51-67, and column 8, lines 8-27). One of ordinary skill in the art would have recognized this teaching’s applicability to Eyole in that, where a load in Eyole is not expected to coalesce with a subsequent load, loading additional data would be a waste of power to lookup, transfer, and store additional data. As such, to save power, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Eyole such that the normal load loads without loading additional data from the cache memory to the fat load storage structure.
Referring to claim 3, Eyole, as modified, has taught the architecture of claim 1 wherein the prediction circuit provides a prediction table linking multiple sets of prediction values and load instructions (see FIG.4A and paragraph [0044]. Each load’s prediction will be accessed, if it exists, by providing a portion of the load instruction address to the predictor).
Referring to claim 4, Eyole, as modified, has taught the architecture of claim 1 wherein the prediction circuit operates to generate the prediction value for a given load instruction by monitoring spatiotemporal locality for previous executions of the given load instruction (see paragraph [0017]. Basically, the predictor is to predict loads in close address (spatial) proximity to one another. The loads that are close in memory addresses must also be close enough in time (temporal) such that they will be in the pending loads buffer at the same time. Thus, for a given load, if past executions of the given load indicate that the given load cannot satisfy a subsequent load by loading additional data, a non-coalescing prediction value will be generated; otherwise, a coalescing prediction will be generated).
Referring to claim 5, Eyole, as modified, has taught the architecture of claim 3 wherein the prediction circuit accesses the prediction table to obtain a prediction value for a given load instruction using a program counter value of the given load instruction (see FIG.4A. The program counter value (instruction address) of a load is used to obtain its prediction).
Referring to claim 6, Eyole, as modified, has taught the architecture of claim 5 wherein the prediction circuit uses a representation of the respective program counter value of a given load instruction insufficient to map to a unique program counter value to access the prediction table (see FIG.4A. Instead of using the full program counter value, only a portion thereof (bits 17:2) is used (omitting bits 1:0). Such a compressed version of the program counter cannot be mapped to a unique program counter value because the compressed version will always map to four program counter values (i.e., the four program counter values having the same 17:2 bits but having different 1:0 bits).
Referring to claim 7, Eyole, as modified, has taught the architecture of claim 1 wherein the prediction value for a given load instruction is based on a measurement of load instructions subsequent to an earlier execution of the given load instruction having spatial proximity to the given load instruction in a measurement interval (see paragraphs [0044]-[0047] for various predictor embodiments. A prediction may be based on history, i.e., whether a given load coalesces with spatially-proximate subsequent loads during an interval between given load executions. Or, a prediction may be based on a load addresses from the coalescer and those in the instruction queue. Thus, the instructions in question must be close enough so as to be in the coalescer and instruction queue during a given time window (measurement interval). Or, a prediction may be based on dependencies between co-pending load instructions, which means they have to be spatially closed enough so as to be co-pending. Thus, the measurement interval is a co-pendency interval).
Referring to claim 8, Eyole has taught the architecture of claim 7 wherein, for a given load instruction, the measurement interval is selected from the group consisting of: (a) a time between an execution of the given load instruction and a completion of processing of the given load instruction; (b) a number of instructions executing subsequent to the execution of the given load instruction (as stated above, the prediction is based on loads that follow a given load. So, the measurement interval includes a number of instructions after the given load that are co-pending with the given load); and (c) a number of clock cycles of the computer processor after the execution of the given load instruction (where the measurement interval is between two executions of a given load, this corresponds to a number of cycles); wherein execution of the given load instruction corresponds to a time of determination of a load data memory address of the designated data to be loaded by the given load instruction (since execution involves using the memory address, it can be said that execution corresponds to a time of determining the memory address (“corresponds” is broad)).
Claim 18 is rejected for similar reasoning as claim 1.
Referring to claim 31, Eyole, as modified, has taught the architecture of claim 1 wherein the fat load storage structure is non-cache memory (the structure comprises buffers 80/84, but not cache memory. Cache memory is accessed to move data from cache into these buffers).
Claim 32 is rejected for similar reasoning as claim 31.
Claims 9 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Eyole in view of Alexander and the examiner’s taking of Official Notice.
Referring to claim 9, Eyole, as modified, has taught the architecture of claim 1 wherein the processor further includes a translation lookaside buffer holding page table data used for translation between virtual and physical addresses (see paragraph [0040]); and wherein the processing circuitry processes the first load instruction to load data from the cache memory (see the reasoning in the rejection of claim 1).
Eyole has not taught that the processing circuitry processes the first load instruction to also load translation lookaside buffer data to the processor. However, a TLB miss is known in the art. That is, a TLB is a cache of address translations. When a translation for a memory request is cached in the TLB, the memory request can be quickly translated and performed more quickly. However, when the translation is not caches, a TLB miss occurs and the processor must access other memory to obtain the translation and then store it in the TLB. This could occur if the TLB is too small and/or this translation has not been used in some time, both known normal factors to consider in the art of caching. As a result, in order to translate a memory request whose translation is not in the TLB, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Eyole such that the processing circuitry processes the first load instruction to also load translation lookaside buffer data to the processor.
Referring to claim 30, Eyole, as modified, has taught the architecture of claim 1 but has not taught wherein the load data memory address of the designated data is determined by adding a value to the contents of a base register specified in the load instruction and the data identifier of the additional data in (a)(ii) is linked to the identity of the base register. However, Official Notice is taken that base+offset addressing was well known in the art before applicant’s invention. Here, the base could represent the beginning of, for an example, an array, stack, or struct, and the offset will allow a load to access a particular memory of that array/stack/struct. One of ordinary skill in the art would have recognized that any addressing mode could be used in Eyole and, thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Eyole such that the load data memory address of the designated data is determined by adding a value (offset/displacement) to the contents of a base register specified in the load instruction. Given this modification, since the load address would be based on the base register, and the address register (Alexander 207) stores the load address, which is the data identifier of the additional data, then the data identifier is linked to the base register.
Response to Arguments
On pages 12-13 of applicant’s response, applicant argues that Eyole fails to teach an enrolled data linked to a data identifier and to store, together with the additional data in the structure, a data identifier of the additional data.
While the examiner believes that some identifier is necessary in Eyole to be able to pick which additional data needs to be loaded from the structure based on the oldest load in the pending loads buffer, Eyole is generally silent in this regard. However, Alexander has been found in an updated search and has been combined with Eyole so as to provide an explicit teaching of that which is claimed.
On page 13 of the response, applicant also argues that Eyole has not taught that the fat load is performed without requiring a comparison using the load data memory address of a load instruction using the additional data.
The examiner believes this point was previously discussed and the examiner is still not persuaded. The fat load can be said to be performed only based on when the load performing the fat load is the oldest in the pending loads buffer and does not have its coalescing bit set. Comparisons occur while loads are in the pending loads buffer, but this is only to set a subsequent load’s coalescing bit. The fat load performed by a previous load does not depend on the claimed comparison.
On page 13 of the response, applicant argues that Subramoney uses the data of the fat load to perform a fat load and, thus, does not anticipate the claims.
The examiner agrees assuming applicant means “the designated data for the first load instruction” when referring to “the data”. This needs to be clarified in the claim, but the Subramoney rejection has been withdrawn based on the examiner’s assumption.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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