DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 8/13/2025 have been fully considered but they are not persuasive.
On page of the remarks filed on 8/13/2025, the applicant argues that Pietambaram et al. fails to disclose the sub-layers that are on “opposite” sides of the first metal layer or the second metal layer. However, the “opposite” limitation is not present in the claim language of 1. Furthermore, “third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers” limitation could be arrived in Fig. 2 of Pietanbaram et al, especially since the Fig. 2 could be taken in a flipped orientation or 90 degrees rotated limitation. Please note that this is the case since in real manufacturing environment, the device could be assembled in any orientation. Furthermore, the claim language does not tie the above or below to the other claim limitations. The applicant is urged to set an interview for further explanation. The examiner is readily available for an interview.
Examiner is including Ozkan et al. (2023/008649) and Zhang et al. (201603033803) as pertinent prior art documents that disclose high speed packaging structure with dielectric layers of different dielectric constants.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5-9 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pietambaram et al. (20200075473).
Regarding Claim 1, in Fig. 2 and paragraphs 0025-0027, Pietambaram et al. discloses an apparatus, comprising: a semiconductor chip package substrate comprising alternating metal 204/206/208 and dielectric layers 210/212/214, wherein, first and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage (see paragraph 0067) structures have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) (see paragraphs 0040 and 0146) than third and fourth ones (see paragraphs 0055-0057 for additional dielectric bi-layers/conductive layers which would read on the third and fourth dielectric layers) of the dielectric layers that are directly above and directly below a second of the metal layers that is patterned to have signal wires that are to transport signals having a pulse width of Ins or less (see paragraphs 0016, 0041, 0079, 0087, 0147 and 0148 for RF/optical (interconnect) related signals where the pulse width duration is “typically” less than 1 ns or less. This “typically” language appears in paragraph 0015 of the instant application as published. From the understanding/interpretation of the, these signals refer to RF/optical interconnect signals, which is disclosed by Pietambaram et al.)
Regarding Claim 2, the semiconductor chip package substrate comprises a top stack of alternating metal and dielectric layers and a bottom stack of alternating metal and dielectric layers separated by one or more core dielectric layers (see paragraphs 0055-0057)
Regarding Claim 5, in paragraphs 0016, 0027, 0039, 0049 and 0079, the third and fourth ones of the dielectric layers comprise non polar (organic polymeric) molecular structures.
Regarding Claim 6, in paragraphs 0016, 0027, 0039, 0049 and 0079 the non polar molecular structures (organic polymeric) comprise non-polar cross-linkers.
Regarding Claim 7, in paragraphs 0016, 0027, 0039, 0049 and 0079 the non polar molecular structures (organic polymeric) comprise non-polar polymer backbone material.
Regarding Claim 8, in Figs. 2, 22 and 23 and paragraphs 0025-0027, Pietambaram et al discloses a computer comprising:a solid state drive interface; a networking interface; a system memory; and, a processor packaged withLa semiconductor chip package substrate (see Figs. 22 and 23), the semiconductor chip package substrate comprising alternating metal and dielectric layers, wherein, first and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage structures (see paragraph 0067) have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) than third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers (see paragraphs 0040 and 0146) than third and fourth ones (see paragraphs 0055-0057 for additional dielectric bi-layers/conductive layers which would read on the third and fourth dielectric layers) that is patterned to have signal wires that are to transport signals having a pulse width of ins or less (see paragraphs 0016, 0041, 0079, 0087, 0147 and 0148 for RF/optical (interconnect) related signals where the pulse width duration is “typically” less than 1 ns or less. This “typically” language appears in paragraph 0015 of the instant application as published. From the understanding/interpretation of the, these signals refer to RF/optical interconnect signals, which is disclosed by Pietambaram et al.)
Regarding Claim 9, in paragraphs 0040, 0055-0057, 0146, semiconductor chip package comprises a top stack of alternating metal and dielectric layers and a bottom stack of alternating metal and dielectric layers separated by one or more core dielectric layers.
Regarding Claim 12, in paragraphs 0016, 0027, 0039, 0049 and 0079 the third and fourth ones of the dielectric layers (organic/polymeric) comprise non polar molecular structures.
Regarding Claim 13, in paragraphs 0016, 0027, 0039, 0049 and 0079the non polar molecular structures (organic/polymeric) comprise non-polar cross-linkers.
Regarding Claim 14, in paragraphs 0016, 0027, 0039, 0049 and 0079, wherein the non polar molecular structures (organic/polymeric) comprise non-polar polymer backbone material.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram et al. (20200075473) in view of Son (20130161826)
Regarding Claim 3, Pietambaram et al. discloses everything except to disclose the limitation where the third and fourth ones of the dielectric layers have air pockets therein. However, Son discloses a semiconductor package structure where in Figs. 3-5 and paragraphs 0052, 0056, 0060 and 0093, the required limitation with respect to air pockets (airgaps) are disclosed.
It would have been obvious to one of having ordinary skill in the art at the time of effective filing to have the required air pockets in Pietambaram et al. as taught by Son in order to modulate the dielectric constant/dissipation factor/loss tangent/shunt for high speed design purposes
Regarding Claim 4, in Figs. 3-5 and paragraphs 0052, 0056, 0060 and 0093 of Son, the air pockets are formed with hollow particles that are embedded in the third and fourth ones of the dielectric layers
Regarding Claim 10, in Figs. 3-5 and paragraphs 0052, 0056, 0060 and 0093 of Son, the third and fourth ones of the dielectric layers have air pockets therein.
Regarding Claim 11, in Figs. 3-5 and paragraphs 0052, 0056, 0060 and 0093 of Son, the air pockets are formed with hollow particles that are embedded in the dielectric layers
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 10/23/2025