DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed April 7, 2026. Claims 1, 8, and 10 are amended. Claims 11, 14, and 18-20 are cancelled. Claims 21-25 are newly added. The Examiner notes that claims 1-10, 12-13, 15-17, and 21-25 are examined.
Response to Arguments
Applicant’s arguments with respect to claims 1-10, 12-13, and 15-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. A different interpretation of Yu is relied upon to reject the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 10, 13, 17, 23, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2018/0226349 A1).
With respect to claim 1, Yu teaches in Fig. 10:
A microelectronic assembly (first package region 100), comprising:
a package substrate (package substrate 150);
a first die (passive device 118), having a first surface (bottom surface) and an opposing second surface (top surface), in a first layer over the package substrate; a redistribution layer (first redistribution structure 114) on the first layer,
wherein the RDL (114) is electrically coupled to the second surface (bottom surface) of the first die (118) by solder interconnects (para. 26 “conductive connectors 122 may include forming solder balls in the openings 117, and reflowing the solder balls in the openings 117),
the solder interconnects (122) directly coupled to conductive contacts of the RDL (114),
and a second die (substrate 106 of integrated circuit die 104B, does not include dielectric 110 or die connectors 108) in a second layer on the RDL (on bottom side of 114), wherein the second die is electrically coupled to the RDL by non-solder interconnects (die connectors 108, described in 15 as conductive pillars that may be formed by plating),
the RDL (114) is between the first layer (layer including 118) and the second layer (layer containing chip 104),
the first die (118) is between the package substrate (150) and the second die (106 of 104B) (see Fig. 10);
and an insulating material (dielectric 110) between the RDL (114) and a surface of the second die (106 of 104B) facing the RDL.
With respect to claim 2, Yu further teaches:
wherein the first die (118) is electrically coupled (para. 24 “The passive device 118 may be electrically connected to one or more of the integrated circuit dies 104 through the first redistribution structure 114”) to the second die (106 of 104B) by the solder interconnects (122), conductive pathways in the RDL (114), and the non-solder interconnects (108).
With respect to claim 3, Yu further teaches:
wherein the non-solder interconnects include metal-to-metal interconnects (metal 108 is connected to metal conductive lines within 114)
With respect to claim 6, Yu further teaches:
wherein the first layer and the second layer include one or more insulating materials (first and second layers include encapsulants 130 and 112, respectively).
With respect to claim 7, Yu further teaches:
wherein the solder interconnects (122) are first solder interconnects, and the package substrate (150) is electrically coupled to the first surface of the first die (bottom of 118) by second solder interconnects (para. 35 “the conductive connectors 136 are formed by initially forming a layer of solder through methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like”).
With respect to claim 8, Yu further teaches:
wherein the non-solder interconnects (108) are first non- solder interconnects, and the microelectronic assembly further comprises: a conductive pillar in the first layer (conductive vias 116), wherein the conductive pillar is coupled to the RDL (114) by second non-solder interconnects (para 22 teaches that the vias 116 are formed and connected to 114 by plating, not solder).
With respect to claim 23, Yu further teaches:
wherein the second die is a memory die (para. 13 “The integrated circuit dies 104 may each have a single function (e.g., a memory die)”).
With respect to claim 25, Yu further teaches:
wherein the second die is a bumped die. (106 has connectors 108 extending away from the die. The instant application recites “the dies 114-1, 114-2, 114-3, and 114-4 are depicted as having conductive contacts extending away from a surface of the die, and may be referred to herein as "a bumped die" or "a micro-bumped die." The Examiner therefor considers the structures to be substantially identical.)
With respect to claim 10, Yu teaches in Fig. 10:
A microelectronic assembly (first package region 100), comprising:
a package substrate (package substrate 150);
a first die (passive device 118), having a first surface (bottom) with first conductive contacts (connectors 124) and an opposing second surface (top) with second conductive contacts (bumps 120), in a first layer over the package substrate (150);
a redistribution layer (redistribution structure 114), having a first surface with third conductive contacts (bottom surface with conductive lines formed within) and an opposing second surface with fourth conductive contacts (top surface with conductive lines formed within), on the first layer,
wherein the third conductive contacts on the first surface of the RDL are electrically coupled to the second conductive contacts on the first die by solder interconnects (122),
the solder interconnects in direct contact with the third conductive contacts on the first surface of the RDL (see Fig. 10),
a second die (substrate 106 of integrated circuit die 104B, not including dielectric 110 or connector 108), having a surface with fifth conductive contacts (bottom surface with die connectors 108), in a second layer on the second surface of the RDL (114),
wherein the RDL (114) is between the first layer (layer containing 118) and the second layer (layer containing 104A and 104B),
the first layer (including 118) is between the second layer (including 104A and 104B) and the package substrate (150), and the fifth conductive contacts (108) on the second die are electrically coupled to the fourth conductive contacts on the RDL by non-solder interconnects (conductive lines within 114);
and an insulating material (dielectric 110) between the RDL (114) and a surface of the second die (106 of 104B) facing the RDL.
With respect to claim 13, Yu further teaches:
wherein the first die (118) is electrically coupled (para. 24 “The passive device 118 may be electrically connected to one or more of the integrated circuit dies 104 through the first redistribution structure 114”) to the second die (106 of 104B) by the solder interconnects (122), conductive pathways in the RDL (114), and the non-solder interconnects (108).
With respect to claim 17, Yu further teaches:
wherein the solder interconnects (122) are first solder interconnects, and the package substrate (150) is electrically coupled to the first surface of the first die (bottom of 118) by second solder interconnects (para. 35 “the conductive connectors 136 are formed by initially forming a layer of solder through methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 9, 12, 15-16, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0226349 A1) in view of Elsherbini (US 2019/0385977 A1).
With respect to claim 4, Yu teaches all limitations of claim 1 upon which claim 4 depends. Yu is silent to the pitch between the solder interconnects and therefore does not teach:
wherein a pitch of the solder interconnects is between 10 and 100 microns
Elsherbini teaches:
wherein a pitch of the solder interconnects is between 7 and 100 microns (para. 40 “the DTD interconnects 130 disclosed herein may have a pitch between 7 microns and 100 microns”)
The Examiner notes that although the solder interconnects of claim 4 refer to the interconnect between 114-3 and 148 which is referred to as a die-to-RDL (DTRDL) interconnect by Elsherbini and para. 40 refers to die-to-die interconnects, Fig. 5 shows that the pitch of the interconnects in the DTRDL connection between 114-3 and 148 is the same as the pitch of the DTD interconnect of, for example, 114-11 and 114-3. Therefore, the examiner determines that Elsherbini also teaches solder interconnects of the DTRDL layer with a pitch between 7 microns and 100 microns.
The range of Elsherbini overlaps with the claimed range of 10 to 100 microns. It would be obvious for the ordinary artisan to modify Yu with the teachings of Elsherbini to include a pitch of the solder interconnects in the claimed range for the purpose of managing stress on the dies due to heat expansion (para. 40 of Elsherbini) and/or because “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” (MPEP 2144.05(I)).
With respect to claim 5, Yu teaches all limitations of claim 1 upon which claim 5 depends. Yu is silent to the pitch between the solder interconnects and therefore does not teach:
wherein a pitch of the non-solder interconnects is between 50 and 150 microns
Elsherbini teaches:
wherein a pitch of the non-solder interconnects (ML interconnects 152) is between 100 and 300 microns (para. 25 “the ML interconnects 152 disclosed herein may have a pitch between 100 microns and 300 microns”)
The range 100 microns to 300 microns overlaps with the claimed range of 50 to 150 microns. It would be obvious for an ordinary artisan to modify Yu with the teachings of Elsherbini to have a pitch of the non-solder interconnects in the claimed range. The ordinary artisan would be motivated to arrive in the claimed range for the purpose of “improving the performance of the microelectronic assembly by increasing bandwidth, by reducing resistance, by lowering parasitics, and/or by more efficiently delivering power from the package substrate” (para. 25 of Elsherbini) and/or because “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” (MPEP 2144.05(I)).
With respect to claim 9, Yu teaches all limitations of claim 1 upon which claim 9 depends. Yu fails to teach:
a third die, having a first surface, an opposing second surface, and through-substrate vias (TSVs) between the first and second surfaces, in the first layer within a footprint of the second die, wherein the third die is electrically coupled to the RDL by solder interconnects.
Elsherbini teaches:
a first die (114-3)
a second die (114-2)
a third die (die 114-10), having a first surface (top), an opposing second surface (bottom), and through-substrate vias (TSVs) between the first and second surfaces (para. 29 “double-sided die refers to a die that has connections on both surfaces. In some embodiments, a double-sided die may include through silicon vias (TSVs)”), in the first layer (104-3) within a footprint of the second die (114-2), wherein the third die (114-10) is electrically coupled to the RDL (148) by solder interconnects (DTRDL interconnects 155-3, para 64 “Any suitable technique may be used to form the DTRDL interconnects 155 disclosed herein, such as plating techniques, solder techniques”).
With respect to claim 22, Yu teaches all limitations of claim 1 upon which claim 22 depends. Yu fails to teach:
wherein the first die is a processing die.
Elsherbini teaches a similar stacked die structure in which the bottom die may be a processing die (para. 78 “the die 114-1 in a microelectronic assembly 100 may be a processing device (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.”)). It would be obvious to modify Yu to replace passive die 118 with a processing die to meet the limitation:
wherein the first die is a processing die.
The limitation is rejected under a rationale of “Use of known technique to improve similar devices (methods, or products) in the same way;” The Graham factual inquiries for this rationale are:
(1) a finding that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an “improvement;”
(2) a finding that the prior art contained a “comparable” device (method, or product that is not the same as the base device) that has been improved in the same way as the claimed invention;
(3) a finding that one of ordinary skill in the art could have applied the known “improvement” technique in the same way to the “base” device (method, or product) and the results would have been predictable to one of ordinary skill in the art; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Yu teaches a base device which is a stacked die structure used for memory applications. Elsherbini teaches a similar structure in which a die at the bottom of the stack is a processing die. One of ordinary skill of the art could have applied the improvement of including a processing day below the memory dies in place of the passive or partially passive die 118 of Yu with predictable result of improving the integration of the device by including processing die that interfaces with the memory dies.
With respect to claim 24, Yu teaches all limitations of claim 1 upon which claim 24 depends. Yu fails to teach:
further comprising an underfill between the solder interconnects, wherein the underfill is not in contact with a sidewall of the first die, the sidewall between the first surface and the second surface.
Elsherbini teaches:
further comprising an underfill (underfill material 127) between the solder interconnects (solder interconnects which may include the interconnects 150 or interconnects 130), wherein the underfill is not in contact with a sidewall of the first die, the sidewall between the first surface and the second surface (underfill is only on surfaces that include solder interconnects and does not extend to sidewall of any of the dies).
Yu teaches the claimed invention except for location of the underfill in relation to the dies. Elsherbini teaches that underfill may be placed between the solder interconnects but not on the sidewall of the dies. It would have been obvious to one of ordinary skill in the art at the time of the invention to include the underfill structure of Elsherbini in the device of Yu. The ordinary artisan would be motivated to do so for the purpose of assisting with soldering the dies (para. 35 of Elsherbini) and because Yu teaches that the specific shape of the underfill is not critical to the function of the device as Yu teaches in para. 32 that the underfill may be omitted and the encapsulant may instead provide structural support.
With respect to claim 12, Yu teaches all limitations of claim 10 upon which claim 12 depends. Yu fails to teach:
wherein the fifth conductive contacts extend away from the surface of the second die.
Elsherbini teaches:
wherein the fifth conductive contacts extend away from the surface of the second die. (para. 23 “conductive contacts may be recessed in, flush with, or extending away from a surface of a component.”)
Yu teaches the claimed invention except for the shape of the conductive contacts relative to the surface of the second die. Elsherbini teaches that conducive contacts that are recessed or extending away from a surface of a component may be used interchangeably. It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the flush contacts of Yu for extending contacts of Elsherbini because they are known equivalents and it would have yielded the predictable result providing a connection between the second die and the RDL. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 15, Yu teaches all limitations of claim 10 upon which claim 15 depends. Yu is silent to the pitch between the solder interconnects and therefore does not teach:
wherein a pitch of the solder interconnects is between 10 and 100 microns
Elsherbini teaches:
wherein a pitch of the solder interconnects is between 7 and 100 microns (para. 40 “the DTD interconnects 130 disclosed herein may have a pitch between 7 microns and 100 microns”)
The Examiner notes that although the solder interconnects of claim 4 refer to the interconnect between 114-3 and 148 which is referred to as a die-to-RDL (DTRDL) interconnect by Elsherbini and para. 40 refers to die-to-die interconnects, Fig. 5 shows that the pitch of the interconnects in the DTRDL connection between 114-3 and 148 is the same as the pitch of the DTD interconnect of, for example, 114-11 and 114-3. Therefore, the examiner determines that Elsherbini also teaches solder interconnects of the DTRDL layer with a pitch between 7 microns and 100 microns.
The range of Elsherbini overlaps with the claimed range of 10 to 100 microns. It would be obvious for the ordinary artisan to modify Yu with the teachings of Elsherbini to include a pitch of the solder interconnects in the claimed range for the purpose of managing stress on the dies due to heat expansion (para. 40 of Elsherbini) and/or because “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” (MPEP 2144.05(I)).
With respect to claim 16, Yu teaches all limitations of claim 1 upon which claim 16 depends. Yu is silent to the pitch between the solder interconnects and therefore does not teach:
wherein a pitch of the non-solder interconnects is between 50 and 150 microns
Elsherbini teaches:
wherein a pitch of the non-solder interconnects (ML interconnects 152) is between 100 and 300 microns (para. 25 “the ML interconnects 152 disclosed herein may have a pitch between 100 microns and 300 microns”)
The range 100 microns to 300 microns overlaps with the claimed range of 50 to 150 microns. It would be obvious for an ordinary artisan to modify Yu with the teachings of Elsherbini to have a pitch of the non-solder interconnects in the claimed range. The ordinary artisan would be motivated to arrive in the claimed range for the purpose of “improving the performance of the microelectronic assembly by increasing bandwidth, by reducing resistance, by lowering parasitics, and/or by more efficiently delivering power from the package substrate” (para. 25 of Elsherbini) and/or because “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” (MPEP 2144.05(I)).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0226349 A1).
With respect to claim 21, Yu teaches all limitations of claim 1 upon which claim 21 depends. Yu fails to teach:
wherein the first die is thicker than the second die.
Yu differs from the claimed invention only in the relative sizes of the dies. The Examiner determines that the thickness of the dies is not critical to the function of the microelectronic assembly and that the ordinary artisan would expect the device of Yu to function similarly if the first die were thicker than the second die. It would have been an obvious matter of design choice to modify Yu to make the first die thicker than the second die, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. The ordinary artisan would be modified to make such a change in order to accommodate necessary components on the first die and optimize the layout of the dies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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