Prosecution Insights
Last updated: July 05, 2026
Application No. 17/481,257

MOAT PROTECTION TO PREVENT CRACK PROPAGATION IN GLASS CORE SUBSTRATES OR GLASS INTERPOSERS

Non-Final OA §103
Filed
Sep 21, 2021
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
4 (Non-Final)
46%
Grant Probability
Moderate
4-5
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 46% of resolved cases
46%
Career Allowance Rate
6 granted / 13 resolved
-21.8% vs TC avg
Strong +42% interview lift
Without
With
+41.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
46 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
84.4%
+44.4% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 13 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 6-10, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ganesan et al. (“Ganesan” US 2021/00335911) and Cho et al. (“Cho” US 2016/0128186). Regarding claim 1, Ganesan discloses an electronic package (Figure 1), comprising: a core (120), wherein the core comprises glass (see para. [0018]); a hole (leftmost via hole, through which the leftmost via 121 extends) through a thickness of the core (120, see Figure 1); a first via (leftmost via 121 in Figure 1, see also annotated Figure 1 below); a second via (via 121 in the center of the core 120, see also annotated Figure 1 below) through the core (120), wherein the second via (center 121) comprises a conductive material (copper, see para. [0019]) in contact with the glass of the core (120, see Figure 1 which shows direct physical contact between the second via, center 121, and the core 120): first layers (upper portion of encapsulation layer 180 that is above the glass core 120) over the core (120, see Figure 1), wherein the first layers comprise a dielectric material (see para. [0023], which discloses dielectric materials used for the encapsulant); and second layers (lower portion of encapsulation layer 180 that is below the glass core 120) under the core (120, see Figure 1), wherein the second layers comprise the dielectric material (the first and second layers comprise the same encapsulant, dielectric material, see para. [0023] and Figure 1). Ganesan does not disclose: a plug filling the hole, wherein the plug comprises a polymeric material, and wherein the plug has an uppermost surface at a same level as an uppermost surface of the core, and the plug has a bottommost surface at a same level as a bottommost surface of the core; a first via through the plug, wherein the first via comprises a conductive material in contact with the polymeric material of the plug. Cho discloses in Figure 4, however, a plug (“groover part” 15 and “protection layer” 155) filling the hole (holes in core 10 through which the via material 150 extends and through which the groove part 15 portion of the plug), wherein the plug (15/155) comprises a polymeric material (see para. [0050] which discloses the plug 155 comprises an epoxy resin which is a polymeric material and para. [0022] which discloses the plug portion 15 is a resin, which is a polymeric material, additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07), and wherein the plug (15/155) has an uppermost surface (top short edge surfaces of the plug 155) at a same level as an uppermost surface of the core (10, top surface of the core 10 is coplanar with the uppermost surface of the plug 155, see Figure 4), and the plug (15/155) has a bottommost surface (bottom short edge surfaces of the plug 155) at a same level as a bottommost surface of the core (10, bottom surface of the core 10 is coplanar with the bottommost surface of the plug 155, see Figure 4); a first via (150) through the plug (via 150 goes through the portion 155 of the plug, the via 150 also goes between the adjacent plug portions 15, thus through the plug portion 15 also, see Figure 4), wherein the first via (150) comprises a conductive material (copper, see para. [0038]) in contact with the polymeric material of the plug (155, see direct physical contact between the via 150 and the plug portion 155, the via 150 is also in physical contact with the polymeric material of the plug portion 15 through the core 10 and the other portion of the plug 155, in Figure 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Cho into the teachings of Ganesan to include the features above for the purpose of providing a protective layer between the glass core and a via that alleviates the difference in thermal expansion coefficients (Cho, para. [0050]). Regarding claim 2, Ganesan discloses a plurality of holes (see plurality of holes through which all the vias 121 extend). Ganesan does not disclose a plurality of plugs. Cho discloses a plurality of plugs (15/155, see Figure 4 which shows two plugs specifically, one 155 portion, one 15 portion, see also Figure 1B). Regarding claim 3, Cho discloses wherein the plurality of plugs (15/155) are positioned proximate to a perimeter of the core (10, see Figure 4 and Figure 1B). Regarding claim 6, Ganesan discloses a bridge die (140) embedded in the first layers (upper portion of encapsulation layer 180 that is above the glass core 120) over the core (120, see Figure 1); a first die (110); and a second die (111), wherein the bridge die (140) communicatively couples the first die (110) to the second die (111, see para. [0018], which discloses the bridge die 140 couples the dies 110/111). Regarding claim 7, Ganesan discloses wherein through silicon vias are formed through the bridge die (140, see para. [0022], which discloses that the bridge die includes a plurality of through silicon vias, TSVs). Regarding claim 8, Cho discloses wherein a coefficient of thermal expansion (CTE) of the plug (15/155, specifically the CTE of the 155 portion of the plug) is between a CTE of the core (10) and a CTE of copper. Cho discloses that the purpose of the plug (155) is to alleviate differences in thermal expansion coefficients of the glass core (10) and the via (150) which is made of copper (see para. [0038]). Thus, the CTE of the plug (155) is between the CTE of the glass core and the CTE of the copper via in order to alleviate the differences in CTE. Regarding claim 9, Cho discloses wherein the plug (15/155) is a resin or an epoxy (see para. [0022], [0050]). Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07. Regarding claim 10, Cho discloses wherein a crack (see crack in core 10 shown in Figure 4) in the core (10) initiates at a via (150) through the core (10, para. [0025]) and ends at the plug (155, Figure 4). While Cho does not explicitly disclose a crack in this specific area of the core (initiated at a via, through the core, and ended at the plug), there is a crack disclosed in the perimeter area of the core which is stopped from propagating by the plug portion 15, which is the same material as the plug portion 155. Thus, the intended function of the claim is met by Cho because the plug portion 15 would also function to keep a crack in the core that initiates at the via 150, i.e. the crack extends between the via 150 and the plug portion 15, from propagating further. It would have been obvious to incorporate these teachings of Cho into the teachings of Ganesan for the purpose of providing crack prevention measures in the core of the device (see Cho, para. [0004]). Regarding claim 18, Ganesan discloses an electronic system (Figure 1), comprising: a board (102); a package substrate (encapsulant 180, core 120, and vias 121) coupled to the board (102, see conductive interconnects 123 coupling the package substrate to the board), wherein the package substrate (180/120/121) comprises: a core (120), wherein the core comprises glass (see para. [0018]); a hole (via holes, through which vias 121 extend) through a thickness of the core (120, see Figure 1); a first via (leftmost via 121); a second via (central via 121) through the core (120), wherein the second via (center 121) comprises a conductive material (copper, see para. [0019]) in contact with the glass of the core (120, see Figure 1 which shows direct physical contact between the second via, center 121, and the core 120): first layers (upper portion of encapsulation layer 180 that is above the glass core 120) over the core (120, see Figure 1), wherein the first layers comprise a dielectric material (see para. [0023], which discloses dielectric materials used for the encapsulant); and second layers (lower portion of encapsulation layer 180 that is below the glass core 120) under the core (120, see Figure 1), wherein the second layers comprise the dielectric material (the first and second layers comprise the same encapsulant, dielectric material, see para. [0023] and Figure 1), and a die (110) coupled to the package substrate (180/120/121, see Figure 1). Ganesan does not disclose: a plug filling the hole, wherein the plug comprises a polymeric material, and wherein the plug has an uppermost surface at a same level as an uppermost surface of the core, and the plug has a bottommost surface at a same level as a bottommost surface of the core; a first via through the plug, wherein the first via comprises a conductive material in contact with the polymeric material of the plug. Cho discloses in Figure 4, however, a plug (“groover part” 15 and “protection layer” 155) filling the hole (holes in core 10 through which the via material 150 extends and through which the groove part 15 portion of the plug), wherein the plug (15/155) comprises a polymeric material (see para. [0050] which discloses the plug 155 comprises an epoxy resin which is a polymeric material and para. [0022] which discloses the plug portion 15 is a resin, which is a polymeric material, additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07), and wherein the plug (15/155) has an uppermost surface (top short edge surfaces of the plug 155) at a same level as an uppermost surface of the core (10, top surface of the core 10 is coplanar with the uppermost surface of the plug 155, see Figure 4), and the plug (15/155) has a bottommost surface (bottom short edge surfaces of the plug 155) at a same level as a bottommost surface of the core (10, bottom surface of the core 10 is coplanar with the bottommost surface of the plug 155, see Figure 4); a first via (150) through the plug (via 150 goes through the portion 155 of the plug, the via 150 also goes between the adjacent plug portions 15, thus through the plug portion 15 also, see Figure 4), wherein the first via (150) comprises a conductive material (copper, see para. [0038]) in contact with the polymeric material of the plug (155, see direct physical contact between the via 150 and the plug portion 155, the via 150 is also in physical contact with the polymeric material of the plug portion 15 through the core 10 and the other portion of the plug 155, in Figure 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Cho into the teachings of Ganesan to include the features above for the purpose of providing a protective layer between the glass core and a via that alleviates the difference in thermal expansion coefficients (Cho, para. [0050]). PNG media_image1.png 464 782 media_image1.png Greyscale Response to Arguments Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The Examiner would also like to note, regarding Applicant’s arguments against Cho ‘186, Applicant cited to Figure 6F of Cho, when the rejection relied on Figure 4 of Cho ‘186, which is a different embodiment. See page 8 of Remarks, filed February 2 2026. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Show 5 earlier events
Jul 08, 2025
Response after Non-Final Action
Aug 05, 2025
Notice of Allowance
Oct 02, 2025
Response after Non-Final Action
Oct 19, 2025
Response after Non-Final Action
Nov 05, 2025
Non-Final Rejection mailed — §103
Feb 02, 2026
Response Filed
Apr 07, 2026
Final Rejection mailed — §103
Jun 03, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12667010
SEMICONDUCTOR DEVICE
3y 6m to grant Granted Jun 23, 2026
Patent 12525517
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
46%
Grant Probability
88%
With Interview (+41.7%)
3y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 13 resolved cases by this examiner. Grant probability derived from career allowance rate.

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