DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments/amendments, see Remarks/Claims, filed 10 October 2025, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Kwon and (Fang Chen et al. US 2019/0371933 A1; hereinafter Chen), as necessitated by the amendments. The updated rejection in view of Kwon and Chen is presented below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-5, 8-9, 14-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Taehong Kwon et al. (US 2021/0066281 A1; hereinafter Kwon) in view of Fang Chen et al. (US 2019/0371933 A1; hereinafter Chen) and Sara Rigante et al. (US 2015/0268189 A1; hereinafter Rigante).
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Regarding Claim 1, Kwon teaches a memory device (Fig. 1 and Fig. 7A), comprising:
an array of memory cells (110; ¶0022); and
a plurality of peripheral circuits (120, 130, 140, 150; ¶0022) coupled to the array of memory cells (110) and configured to control the array of memory cells (as shown in Fig. 7A; ¶0021-¶0028),
wherein:
a first peripheral circuit (130) of the plurality of peripheral circuits configured to interface the array of memory cells (110) with a memory controller (150) in a bi-directional manner (¶0028) and comprises a first three-dimensional (3D) transistor (BLSLT; which is a fin-type transistor; ¶0057) and an other 3D transistor (adjacent BLSLT; hereinafter BLSLT2) formed in a device layer of a second semiconductor structure (layer where transistors BLSLT exist in second semiconductor structure C1), the first 3D transistor (BLSLT) and the other 3D transistor (BLSLT2) in the second semiconductor structure (C1) being coupled with the array of memory cells (110) of a first semiconductor structure (C2) through a hybrid bonding between a first bonding layer (layer containing metal bonding structures DBP2/BP2 and dielectric DL2; ¶0049) of the first semiconductor structure (C2) and a second bonding layer (layer containing DBP1/BP1 and dielectric DL1; ¶0052) of the second semiconductor structure (C1) (this limitation is satisfied by the dielectric-dielectric and metal-metal bonds between the above bonding layers without any intermediate bonding layers, as defined by and commensurate in scope with Applicant’s specification at ¶0061);
wherein a gate structure (¶0041) of the first 3D transistor (BLSLT) and an other gate structure (¶0041, each BLSLT has a gate) of the other 3D transistor (BLSLT2), disposed over respective 3D semiconductor bodies, are in a face-to-face configuration with the array of memory cells (110) (as shown in Fig. 7A), with an interconnect layer (M1/M2/BL) arranged between the device layer (layer containing BLSLT/BLSLT2) and the array of memory cells (110), and through the interconnect layer and the first and second bonding layers, the first 3D transistor and the other 3D transistor are respectively coupled to the array of memory cells (as shown in Fig. 7A).
Even though the features are well known in a 3D semiconductor, Kwon is silent regarding the specific details of the fin-type 3D transistors (BLSLT and BLSLT2) comprising:
wherein the first 3D transistor comprises a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body, the gate structure comprising a gate dielectric and a gate electrode, and a top surface of the 3D semiconductor body of the first 3D transistor being flush with an entire top surface of a source and a drain of the first 3D transistor;
the other 3D transistor comprises an other 3D semiconductor body and an other gate structure in contact with a plurality of sides of the other 3D semiconductor body, the other gate structure comprising an other gate dielectric and an other gate electrode,
the gate electrode of the first 3D transistor comprises a metal;
the 3D semiconductor body and the other 3D semiconductor body are physically connected to form a connected semiconductor body extending in a first direction and the 3D semiconductor body and the other 3D semiconductor body are adjacent in the first direction and remain a same width in a second direction perpendicular to the first direction, a trench isolation being located at a side of the connected semiconductor body; and
the gate structure of the first 3D transistor and the other gate structure of the other 3D transistor are physically separated in the first and second directions and are respectively disposed over the 3D semiconductor body and the other 3D semiconductor body having the same width in the second direction.
In the same field of endeavor, Chen teaches a 3D transistor configuration (Fig. 12A/14/15) applicable for integration into memory devices (¶0028) comprising:
wherein a first 3D transistor (left FinFET; ¶0001, ¶0028) comprises a 3D semiconductor body (left fin 206; ¶0020) and a gate structure (220) in contact with a plurality of sides of the 3D semiconductor body (¶0025, ¶0038), the gate structure (220) comprising a gate dielectric (232; ¶0038) and a gate electrode (234; ¶0038), and a top surface of the 3D semiconductor body of the first 3D transistor being flush with an entire top surface of a source and a drain (pair of S/D’s 212 at either side of gate 220 are flush with an entire top surface of the fin 206; ¶0029) of the first 3D transistor (as shown in Fig. 14);
the other 3D transistor (right FinFET; ¶0001, ¶0028) comprises an other 3D semiconductor body and an other gate structure in contact with a plurality of sides of the other 3D semiconductor body, the other gate structure comprising an other gate dielectric and an other gate electrode (as same as in the first 3D transistor above),
the gate electrode (234) of the first 3D transistor comprises a metal (¶0038);
the 3D semiconductor body (206 left) and the other 3D semiconductor body (206 right) are physically connected to form a connected semiconductor body extending in a first direction (they are physically connected as being physically a part of, and extending from, the substrate 202; ¶0020 and extend in the x-direction) and the 3D semiconductor body and the other 3D semiconductor body are adjacent in the first direction (X-direction) and remain a same width in a second direction perpendicular (Y-direction; as shown in view of Fig. 2A) to the first direction, a trench isolation (204; ¶0016) being located at a side of the connected semiconductor body (as shown in Fig. 2A and other figures, 204 is at a side of the connected semiconductor body); and
the gate structure (220) of the first 3D transistor (left FinFET) and the other gate structure (220) of the other 3D transistor (right FinFET) are physically separated in the first (X) and second (Y) directions and are respectively disposed over the 3D semiconductor body and the other 3D semiconductor body having the same width in the second direction (as shown in Fig. 8A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures having the 3D transistor configuration of Chen in the semiconductor device of Kwon in order to enhance the circuit performance and reliability of the memory circuit (Chen; ¶0001).
Chen’s 3D transistor FinFET configuration does not explicitly show in the figures “the gate structure(s) (220) are contacting a plurality of sides of the 3D semiconductor body (fin 206 of the respective FinFETs)”.
Nevertheless, reference Rigante from the same field of endeavor shows this well-known feature of the FinFET in Fig. 1.A. Rigante shows gate is in contact with a plurality of sides (top and both sides) of the 3D semiconductor body (102; ¶0055). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures such that the gate structures (220) of Chen would contact a plurality of sides of the 3D semiconductor body (Chen; fin 206 of the FinFET) in the manner of Riangte in order to improve scaling while improving channel control (Rigante; ¶0004-¶0005).
Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The combined disclosures hereinafter “modified Kwon”.
Regarding Claim 2, modified Kwon teaches the memory device of claim 1, wherein a top surface of the gate structure of the first 3D transistor is curved (as modified by and shown in view of the gate of Fig. 1.A. of Rigante).
Regarding Claim 4, modified Kwon teaches the memory device of claim 1, wherein the first 3D transistor is a multi-gate transistor (wherein the FinFET 3D transistor is a multi-gate transistor wherein the gate contacts multiple sides of the 3D semiconductor body, and/or a multi-bridge-channel-type transistor; Kwon; ¶005).
Regarding Claim 5, modified Kwon teaches the memory device of claim 1, wherein the gate dielectric (Chen; 232) of the first 3D transistor comprises a high dielectric constant (high-k) dielectric (Chen; ¶0038).
Regarding Claim 8, modified Kwon teaches the memory device of claim 1, further comprising a first voltage source (voltage is provided to the gate of BLSLT of 130; ¶0041; therefore a voltage source is coupled) coupled to the first peripheral circuit (130).
Kwon is silent regarding the voltage source being configured to provide a first voltage to the first 3D transistor, wherein the first voltage is between 0.9 V and 1.2 V.
However, the voltage applied to the device is directed toward the operation of the device, and the manner of operating the device does not differentiate the apparatus claim from the prior art (MPEP 2114 II).
Regarding Claim 9, modified Kwon teaches the memory device of claim 1, wherein the first peripheral circuit (130) is an input/output (I/O) circuit (as shown in Kwon Fig. 1).
Regarding Claim 14, modified Kwon teaches the memory device of claim 1, wherein a third peripheral circuit (Kwon; 140) of the plurality of peripheral circuits comprises a planar transistor (Kwon; Fig. 7A; transistor PGMTR of third peripheral circuit 140 is a planar-type transistor, ¶0057).
Regarding Claim 15, modified Kwon teaches the memory device of claim 1, wherein the array of memory cells (110) comprises an array of 3D NAND memory strings (Kwon; as shown in Fig. 2/7A and described in ¶0024, ¶0030).
Regarding Claim 16, Kwon teaches a memory device (Fig. 1, Fig. 4, and Fig. 7A), comprising:
an array of memory cells (110; ¶0022); and
an input/output (I/O) circuit (130; ¶0022) coupled to the array of memory cells (110) and configured to interface the array of memory cells with a memory controller (as shown in Fig. 7A; ¶0021-¶0028), wherein the I/O circuit (130) comprises a plurality of three-dimensional (3D) transistors (plurality of BLSLT, which is a fin-type transistor; ¶0057), the plurality of 3D transistors comprising a first 3D transistor (BLSLT) and a second 3D transistor (hereinafter, BLSLT2) in a device layer of the I/O circuit (layer where transistors BLSLT exist in second semiconductor structure C1),
wherein:
the first 3D transistor (BLSLT) and the second 3D transistor (BLSLT2) are coupled with the array of memory cells (110) through a plurality of bonding layers in a hybrid bonding configured to bond a first semiconductor structure (C2; ¶0049) comprising the array of memory cells (110) and a second semiconductor structure (C1; ¶0049) comprising the I/O circuit (130 as shown in Fig. 7A) (layer containing metal bonding structures DBP2/BP2 and layer containing dielectric DL2; ¶0049 of the first semiconductor structure {C2}, and a second bonding layer {layer containing DBP1/BP1 and dielectric layer DL1; ¶0052} of the second semiconductor structure {C1}, wherein this limitation is satisfied by the direct dielectric-dielectric and metal-metal bonds between the above bonding layers bonding C1/C2 without any additional intermediate bonding layers, as defined by and commensurate in scope with Applicant’s specification at ¶0061);
wherein a gate structure (¶0041) of the first 3D transistor (BLSLT) and a second gate structure (¶0041, each BLSLT has a gate) of the other 3D transistor (BLSLT2), disposed over the respective 3D semiconductor bodies, are in a face-to-face configuration with the array of memory cells (110) (as shown in Fig. 7A), with an interconnect layer (M1/M2/BL) arranged between the device layer (layer containing BLSLT/BLSLT2) and the array of memory cells (110), and through the interconnect layer and the plurality of bonding layers, the first 3D transistor and the second 3D transistor are respectively coupled to the array of memory cells (as shown in Fig. 7A).
Even though the features are well-known in a 3D semiconductor, Kwon is silent regarding the specific details of the fin-type 3D transistors (BLSLT and BLSLT2) comprising:
wherein the first 3D transistor and second 3D transistor each comprises a 3D semiconductor body and a gate structure in contact with a plurality of sides of a corresponding 3D semiconductor body, and a top surface of the 3D semiconductor body of the first 3D transistor is flush with an entire top surface of a source and a drain of the first 3D transistor;
the 3D semiconductor bodies of the first and second 3D transistors are physically connected to form a connected semiconductor body extending in a first direction and the 3D semiconductor bodies of the first and second 3D transistors are adjacent in the first direction and remain a same width in a second direction perpendicular to the first direction, a trench isolation being located at a side of the connected semiconductor body; and
the gate structure of the first 3D transistor and the gate structure of the second 3D transistor are physically separated in the first and second directions and are respectively disposed over the 3D semiconductor bodies of the first and second 3D transistors.
In the same field of endeavor, Chen teaches a 3D transistor configuration (Fig. 12A/14/15) applicable for integration into memory devices (¶0028) comprising:
wherein a first 3D transistor (left FinFET; ¶0001, ¶0028) and second 3D transistor (right FinFET; ¶0001, ¶0028) each comprises a 3D semiconductor body (respective fins 206; ¶0020) and a gate structure (220) in contact with a plurality of sides of a corresponding 3D semiconductor body (¶0025, ¶0038), and a top surface of the 3D semiconductor body of the first 3D transistor is flush with an entire top surface of a source and a drain (pair of S/D’s 212 at either side of gate 220; ¶0029) of the first 3D transistor (as shown in Fig. 14);
the 3D semiconductor bodies of the first and second 3D transistors are physically connected to form a connected semiconductor body extending in a first direction (respective 206’s are physically connected as physically being a part of, and extending from, the substrate 202; ¶0020) and the 3D semiconductor bodies of the first and second 3D transistors are adjacent in the first direction (X) and remain a same width in a second direction (Y) perpendicular to the first direction (as shown in view of Fig. 2A), a trench isolation (204; ¶0016) being located at a side of the connected semiconductor body (as shown in Fig. 2A and other figures, wherein 204 is located at a side of 206); and
the gate structure (220) of the first 3D transistor (left FinFET) and the gate structure (220) of the second 3D transistor (right FinFET) are physically separated in the first and second directions and are respectively disposed over the 3D semiconductor bodies of the first and second 3D transistors (as shown in Fig. 8A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures having the 3D transistor configuration of Chen in the semiconductor device of Kwon in order to enhance the circuit performance and reliability of the memory circuit (Chen; ¶0001).
Chen’s 3D transistor FinFET configuration does not explicitly show in the figures “the gate structure(s) (220) are contacting a plurality of sides of the 3D semiconductor body (fin 206 of the respective FinFETs)”.
Nevertheless, reference Rigante from the same field of endeavor shows this well-known feature of the FinFET in Fig. 1.A. Rigante shows gate is in contact with a plurality of sides (top and both sides) of the 3D semiconductor body (102; ¶0055). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures such that the gate structures (220) of Chen would contact a plurality of sides of the 3D semiconductor body (Chen; fin 206 of the FinFET) in the manner of Riangte in order to improve scaling while improving channel control (Rigante; ¶0004-¶0005).
Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The combined disclosures hereinafter “modified Kwon”.
Modified Kwon is silent regarding the exact operating voltage of one of the plurality of 3D transistors of the I/O circuit (130) is configured to work under a voltage ranging from 0.9V to 1.2V.
However, the voltage applied to the device is directed toward the operation of the device, and the manner of operating the device does not differentiate the apparatus claim from the prior art (MPEP 2114 II).
Regarding Claim 19, modified Kwon teaches the memory device of claim 16, wherein the array of memory cells (110) comprises an array of 3D NAND memory strings (Kwon; as shown in Fig. 2/7A and described in ¶0024, ¶0030).
Regarding Claim 20, Kwon teaches a system (Figs. 1-7A), comprising:
a memory device (Fig 7A) configured to store data (¶0024) and comprising:
an array of memory cells (110; ¶0022); and
an input/output (I/O) circuit (130; ¶0022) coupled to the array of memory cells (110) and configured to interface the array of memory cells with a memory controller (as shown in Fig. 7A; ¶0021-¶0028), wherein the I/O circuit (130) comprises a plurality of three-dimensional (3D) transistors (plurality of BLSLT, which is a fin-type transistor; ¶0057), the plurality of 3D transistors comprising a first 3D transistor (BLSLT) and a second 3D transistor (hereinafter, BLSLT2) in a device layer of the I/O circuit (layer where transistors BLSLT exist in second semiconductor structure C1);
wherein:
the first 3D transistor (BLSLT) and the second 3D transistor (BLSLT2) are coupled with the array of memory cells (110) through a plurality of bonding layers in a hybrid bonding configured to bond a first semiconductor structure (C2; ¶0049) comprising the array of memory cells (110) and a second semiconductor structure (C1; ¶0049) comprising the I/O circuit (130 as shown in Fig. 7A) (layer containing metal bonding structures DBP2/BP2 and layer containing dielectric DL2; ¶0049 of the first semiconductor structure {C2}, and a second bonding layer {layer containing DBP1/BP1 and dielectric layer DL1; ¶0052} of the second semiconductor structure {C1}, wherein this limitation is satisfied by the direct dielectric-dielectric and metal-metal bonds between the above bonding layers bonding C1/C2 without any additional intermediate bonding layers, as defined by and commensurate in scope with Applicant’s specification at ¶0061), and
the memory controller coupled to the memory device and configured to control the array of memory cells (110) through the I/O circuit (130) (as described in ¶0021-¶0028);
wherein a gate structure (¶0041) of the first 3D transistor (BLSLT) and a second gate structure (¶0041, each BLSLT has a gate) of the other 3D transistor (BLSLT2), disposed over respective 3D semiconductor bodies, are in a face-to-face configuration with the array of memory cells (110) (as shown in Fig. 7A), with an interconnect layer (M1/M2/BL) arranged between the device layer (layer containing BLSLT/BLSLT2) and the array of memory cells (110), and through the interconnect layer and the plurality of bonding layers, the first 3D transistor and the second 3D transistor are respectively coupled to the array of memory cells (as shown in Fig. 7A).
Even though the features are well-known in a 3D semiconductor, Kwon is silent regarding the specific details of the fin-type 3D transistors (BLSLT and BLSLT2) comprising:
wherein the first 3D transistor and second 3D transistor each comprises a 3D semiconductor body and a gate structure in contact with a plurality of sides of a corresponding 3D semiconductor body, and a top surface of the 3D semiconductor body of the first 3D transistor is flush with an entire top surface of a source and a drain of the first 3D transistor;
the 3D semiconductor bodies of the first and second 3D transistors are physically connected to form a connected semiconductor body extending in a first direction and the 3D semiconductor bodies of the first and second 3D transistors are adjacent in the first direction and remain a same width in a second direction perpendicular to the first direction, a trench isolation being located at a side of the connected semiconductor body; and
the gate structure of the first 3D transistor and the gate structure of the second 3D transistor are physically separated in the first and second directions and are respectively disposed over the 3D semiconductor bodies of the first and second 3D transistors.
In the same field of endeavor, Chen teaches a 3D transistor configuration (Fig. 12A/14/15) applicable for integration into memory devices (¶0028) comprising:
wherein a first 3D transistor (left FinFET; ¶0001, ¶0028) and second 3D transistor (right FinFET; ¶0001, ¶0028) each comprises a 3D semiconductor body (respective fins 206; ¶0020) and a gate structure (220) in contact with a plurality of sides of a corresponding 3D semiconductor body (¶0025, ¶0038), and a top surface of the 3D semiconductor body of the first 3D transistor is flush with an entire top surface of a source and a drain (pair of S/D’s 212 at either side of gate 220 are flush with an entire top surface of 206; ¶0029) of the first 3D transistor (as shown in Fig. 14);
the 3D semiconductor bodies of the first and second 3D transistors are physically connected to form a connected semiconductor body extending in a first direction (respective 206’s are physically connected and extend in the x-direction as being physically a part of, and extending from, the substrate 202; ¶0020) and the 3D semiconductor bodies of the first and second 3D transistors are adjacent in the first direction (X) and remain a same width in a second direction (Y) perpendicular to the first direction (as shown in view of Fig. 2A), a trench isolation (204; ¶0016) being located at a side of the connected semiconductor body (as shown in Fig. 2A and other figures); and
the gate structure (220) of the first 3D transistor (left FinFET) and the gate structure (220) of the second 3D transistor (right FinFET) are physically separated in the first and second directions and are respectively disposed over the 3D semiconductor bodies of the first and second 3D transistors (as shown in Fig. 8A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures having the 3D transistor configuration of Chen in the semiconductor device of Kwon in order to enhance the circuit performance and reliability of the memory circuit (Chen; ¶0001).
Chen’s 3D transistor FinFET configuration does not explicitly show in the figures “the gate structure(s) (220) are contacting a plurality of sides of the 3D semiconductor body (fin 206 of the respective FinFETs)”.
Nevertheless, reference Rigante from the same field of endeavor shows this well-known feature of the FinFET in Fig. 1.A. Rigante shows gate is in contact with a plurality of sides (top and both sides) of the 3D semiconductor body (102; ¶0055). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures such that the gate structures (220) of Chen would contact a plurality of sides of the 3D semiconductor body (Chen; fin 206 of the FinFET) in the manner of Riangte in order to improve scaling while improving channel control (Rigante; ¶0004-¶0005).
Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The combined disclosures hereinafter “modified Kwon”.
Modified Kwon is silent regarding the exact operating voltage of one of the plurality of 3D transistors of the I/O circuit (130) is configured to work under a voltage ranging from 0.9V to 1.2V.
However, the voltage applied to the device is directed toward the operation of the device, and the manner of operating the device does not differentiate the apparatus claim from the prior art (MPEP 2114 II).
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon, Chen, and Rigante in view of Weize Chen et al. (US 2022/0254920 A1; hereinafter Chen2).
Regarding Claim 3, modified Kwon teaches the memory device of claim 2, but is silent regarding wherein a thickness of the gate dielectric of the first 3D transistor is between 2 nm and 4 nm.
In the same memory field of endeavor, Chen2 teaches (in ¶0049) that a gate dielectric (432) can be formed for a transistor in a low voltage region of a NVM (non-volatile memory) device that can be 2nm thick. Chen sets forth in ¶0049 that the thickness of the dielectric layer can be selected to allow for fast read access time and to allow the transistors to operate at sufficiently high frequency.
Therefore, it would have been obvious to one of ordinary skill in the art, to optimize the thickness of the gate dielectric layer of modified Kwon to be within the claimed range to obtain the result-effective variables of Chen set forth above. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II.
Regarding Claim 18, modified Kwon teaches the memory device of claim 16, wherein the gate structure (Chen; 220) of each of the plurality of 3D transistors comprises a gate dielectric (232; ¶0038) and a gate electrode (234; ¶0038), the gate electrode comprises metal (Chen; ¶0038), but is silent regarding wherein a thickness of the gate dielectric of the first 3D transistor is between 2 nm and 4 nm.
In the same memory field of endeavor, Chen2 teaches (in ¶0049) that a gate dielectric (432) can be formed for a transistor in a low voltage region of a NVM (non-volatile memory) device that can be 2nm thick. Chen2 sets forth in ¶0049 that the thickness of the dielectric layer can be selected to allow for fast read access time and to allow the transistors to operate at sufficiently high frequency.
Therefore, it would have been obvious to one of ordinary skill in the art, to optimize the thickness of the gate dielectric layer of modified Kwon to be within the claimed range to obtain the result-effective variables of Chen2 set forth above. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon, Chen, and Rigante in view of Bin Yang et al. (US 2021/0036120 A1; hereinafter Yang).
Regarding Claim 6, modified Kwon teaches the memory device of claim 1, wherein Rigante teaches the 3D transistor (Fig. 1A) with a 3D semiconductor body (fin 102 fabricated from Si; ¶0055) wherein: a width of the 3D semiconductor body (fin 102) is between 10 nm and 180 nm (15nm to 40nm; ¶0111); and a height of the 3D semiconductor body is between 40 nm and 300 nm (200nm; ¶0120).
However, modified Kwon is silent regarding the specific dimensions of a channel length of the 3D semiconductor body that is between 30 nm and 180 nm.
In the same field of endeavor, Yang teaches the channel length of a FinFET is a critical dimension that affects threshold voltage of the device, and having transistors with different channel lengths allows integrated circuits to have transistors that exhibit different characteristics depending on their intended use in the device (Yang; ¶0037).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures and optimize the channel length of modified Kwon relative to the channel width (40nm) in order to provide a transistor for small scale applications while providing a desired threshold voltage for the device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon, Chen, Rigante, and Yang, in view of John B. Campi, JR et al. (US 2014/0339649 A1; hereinafter Campi).
Regarding Claim 7, modified Kwon teaches the memory device of claim 6, wherein the first peripheral circuit (Kwon; 130) further comprises:
a second 3D transistor (Kwon; another of the plurality of BLSLT; ¶0041; hereinafter BLSLT3); and
the trench isolation (Chen; 204) between the first adjacent 3D transistors (Chen; Fig. 14).
However, the prior art does not expressly disclose wherein a thickness of the trench isolation (204) being the same as the height of the 3D semiconductor body of the first 3D transistor.
In the same field of endeavor, Campi teaches trench isolation structures (40,41,42, and 43; ¶0017) adjacent a side of a fin (¶0017) have trench isolation thicknesses that can be varied for optimal electrical performance (Campi; ¶0017).
One of ordinary skill in the art would recognize optimizing the depth of the trench isolation feature would result in an adjustment to the desired electrical properties of the transistor while ensuring sufficient isolation between transistors (Campi; ¶0017).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the parameters of the trench isolation feature for the known result effective variables set forth above, and as further supported by MPEP section 2144.05 I and 2144.05 II B.
Claims 10-13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Chen, Rigante, and Seongjun Seo et al. (US 2019/0304991 A1; hereinafter Seo).
Regarding Claim 10, modified Kwon teaches the memory device of claim 8, wherein a second peripheral circuit (Kwon Fig. 7A; 120) of the plurality of peripheral circuits comprises a third 3D transistor (Kwon; PTR; ¶0055), but is silent regarding wherein a thickness of a gate dielectric of the third 3D transistor (PTR) is greater than the thickness of the gate dielectric of the first 3D transistor (BLSLT).
Nevertheless, in the same field of endeavor, Seo teaches a similar memory device (Fig. 2 and Fig. 3) including a plurality of peripheral circuits (PCR1 and PCR2; ¶0028) in a peripheral circuit region (PCR) of a memory device (100; ¶0011), wherein a first peripheral circuit (PCR2) includes a first transistor (Fig. 2; transistor with first individual gate stack PGS2; ¶0033; hereinafter TR1) and an other transistor (Fig. 2; transistor with second individual gate stack PGS2 below the first transistor spaced apart in direction D2; hereinafter TR2), and a third 3D transistor (Seo; Fig. 2/3; transistor of gate stack PGS1, modified to be a 3D transistor such as in modified Kwon above, hereinafter TR3) wherein a thickness of a gate dielectric of the third 3D transistor (Seo; gate dielectric 13a of TR3) is greater than the thickness of the gate dielectric of the first 3D transistor (Seo; gate dielectric 13b of TR1) (as shown in Seo Fig. 3 and ¶0034).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention and absent any new or unexpected results, to combine the disclosures and have the different transistor gate dielectric thicknesses of Seo (above) in the device of modified Kwon in order to provide the known advantage of high or low voltage transistors close to a memory cell region (Seo; ¶0032) and to provide a memory device with enhanced reliability and integration (Seo; ¶0005).
Regarding Claim 11, modified Kwon teaches the memory device of claim 10, wherein the third 3D transistor (modified PTR) further comprises a drift region (the transistor has a drift region where current carriers travel between the channel and drain).
Regarding Claim 12, modified Kwon teaches the memory device of claim 10, further comprising a second voltage source coupled to the second peripheral circuit (as modified by Seo; PCR1, which has a second voltage source providing a voltage to the transistor to be a “high-voltage” transistor; ¶0032) and configured to provide a second voltage to the third 3D transistor, wherein the second voltage is greater than the first voltage applied to the first 3D transistor (TR1 of PCR2) (as described in Seo ¶0032 in view of Fig. 2/3, wherein the transistor TR3 of PCR1 has a thick gate dielectric 13a and operates at a “high-voltage” which is higher than the “low-voltage” transistor TR1 of PCR2 with thinner gate dielectric 13b).
Regarding Claim 13, modified Kwon teaches the memory device of claim 12, but is silent regarding wherein the second voltage is greater than 1.2 V. However, the voltage applied to the device is directed toward the operation of the device, and the manner of operating the device does not differentiate the apparatus claim from the prior art (MPEP 2114 II).
Regarding Claim 21, modified Kwon teaches the memory device of claim 1, wherein:
a second peripheral circuit (Kwon Fig. 7A; 120) of the plurality of peripheral circuits comprises a third 3D transistor (Kwon; PTR; ¶0055);
wherein the third 3D transistor (PTR) is arranged neighboring the first 3D transistor, and the third 3D transistor (PTR) comprises a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body of the third 3D transistor (as modified by the features of Chen’s FinFET from claim 1), the gate structure of the third 3D transistor (PTR) comprising a gate electrode (as modified by Chen) disconnected from the gate electrode of the first 3D transistor (BLSLT) (as shown in view of Chen Fig. 8A, wherein the gate electrodes of gate structures 220 are disconnected from adjacent transistors in both directions X and Y), and the 3D semiconductor body of the third 3D transistor (PTR) being separated from the 3D semiconductor body of the first 3D transistor (BLSLT) (as shown in view of Chen Fig. 8A; wherein adjacent semiconductor bodies are partially separated by isolations structures 214).
Modified Kwon does not expressly disclose wherein the third 3D transistor is arranged neighboring the first 3D transistor in the second direction, and wherein
different voltages are supplied to the first 3D transistor and the third 3D transistor.
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Nevertheless, in the same field of endeavor, Seo teaches a similar memory device (Fig. 2 and Fig. 3) including a plurality of peripheral circuits (PCR1 and PCR2; ¶0028) in a peripheral circuit region (PCR) of a memory device (100; ¶0011), wherein a first peripheral circuit (PCR2) includes a first transistor (Fig. 2; transistor with first individual gate stack PGS2; ¶0033; hereinafter TR1) and an other transistor (Fig. 2; transistor with second individual gate stack PGS2 below the first transistor spaced apart in direction D2; hereinafter TR2, which are physically connected), and a third 3D transistor (Seo; Fig. 2/3; transistor of gate stack PGS1, modified to be a 3D transistor such as in modified Kwon above, hereinafter TR3) is arranged neighboring the first 3D transistor (TR1) in the second direction (D1), and
different voltages are supplied to the first 3D transistor and the third 3D transistor (as described in Seo ¶0032 in view of Fig. 2/3, wherein the transistor TR3 of PCR1 has a thick gate dielectric 13a and operates at a “high-voltage” which is higher than the “low-voltage” transistor TR1 of PCR2 with thinner gate dielectric 13b).
It would have been obvious to one of ordinary skill in the art, absent new or unexpected results and before the effective filing date of the claimed invention, to combine the disclosures and have the layout of the third 3D transistor of Seo (above) in the device of modified Kwon in order to provide the known advantage of high or low voltage transistors close to a memory cell region (Seo; ¶0032) and to provide a memory device with enhanced reliability and integration (Seo; ¶0005).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898