DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 13, 2026 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities: the limitation amended into claim 1 contains a typo in the phrase “dielectric wall” which is being interpreted to read “dielectric gate wall” given surrounding claim context. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,510,620 B1 to Chanemougame et al. (hereinafter “Chanemougame” – previously cited reference) in further view of US 2020/0066725 A1 to Wakayama (hereinafter “Bhuwalka” – previously cited reference).
Regarding claim 1, Chanemougame discloses an integrated circuit structure, comprising:
a sub-fin having a portion protruding above a shallow trench isolation (STI) structure (portion of fin-shaped structure below stack 122 disposed above STI 114; Fig. 1; column 7, lines 3-10; column 8, lines 52-57);
a plurality of horizontally stacked nanowires over the sub-fin (horizontally oriented nanowires 126 stacked over portion of fin-shaped structure; Fig. 1; column 7, lines 3-10; column 8, lines 17-57);
a gate dielectric material layer over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires (dielectric layer 172 disposed over portion of fin-shaped structure and STI 114 and around nanowires 126; Fig. 9; column 11, lines 21-31);
a conductive gate layer over the gate dielectric material layer (metal layer 196 disposed over dielectric layer 172; Fig. 17; column 12, line 66 to column 13, line 24);
a conductive gate fill material over the conductive gate layer (gate metal layer 204 disposed over layer 172; Fig. 17; column 13, lines 36-45);
a dielectric gate wall laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure (iterations of isolation pillars 160 laterally spaced apart from fin-shaped structure and nanowires 126 but over STI 114; Figs. 2 and 17; column 8, line 58 to column 9, line 25), wherein the gate dielectric material layer is along a side of the dielectric gate wall and extends above a top surface of the dielectric wall (dielectric layer 172 material disposed along side and top surface of isolation pillars 160; Fig. 9); and
a dielectric gate plug on the dielectric gate wall (isolation region 208 disposed over one of pillars 160; Fig. 17; column 14, lines 16-39).
Chanemougame fails to disclose a dielectric gate cap over the conductive gate fill material, the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap.
However, Bhuwalka discloses a dielectric gate cap over the conductive gate fill material (gate capping layer 175 disposed over gate electrode layer; Fig. 2; paragraph [0023]); the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap (gate capping layer 175 contacts and terminates in the same horizontal plane as gate isolation portion 180; Fig. 2; paragraph [0023]).
Chanemougame and Bhuwalka are considered to be analogous to the claimed invention because they are in the same field of nanostructured semiconductor device fabrication. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chanemougame to incorporate the teachings of Bhuwalka in order to potentially provide reduced parasitic capacitance, prevention of electrical shorts and improved yield, and reduction of time-dependent dielectric breakdown.
Regarding claim 2, Chanemougame in view of Bhuwalka discloses the integrated circuit structure of claim 1, wherein the dielectric gate plug is vertically aligned with the dielectric gate wall (isolation region 208 vertically aligned with one of isolation pillars 160; Fig. 17).
Regarding claim 3, Chanemougame in view of Bhuwalka discloses the integrated circuit structure of claim 1, wherein the dielectric gate plug is vertically offset from the dielectric gate wall (isolation region 208 vertically offset from one of isolation pillars 160; Fig. 17).
Regarding claim 4, Chanemougame in view of Bhuwalka discloses the integrated circuit structure of claim 1, wherein the gate dielectric material layer and the conductive gate layer are along at least a portion of the sides of the dielectric gate plug (portions of layer 172 and layer 196 disposed along bottom side of isolation region 208; Fig. 17).
Regarding claim 5, Chanemougame in view of Bhuwalka discloses the integrated circuit structure of claim 1, wherein the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and wherein the conductive gate fill material is in contact with the sides of the dielectric gate plug (portions of layer 172 and layer 196 not disposed along bottom side of isolation region 208 and gate metal layer 204 disposed along left and right sides of isolation region 208; Fig. 17).
Regarding claim 16, Chanemougame discloses a computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure (computer product having motherboard with IC processor thereon; column 16, lines 4-21), comprising:
a sub-fin having a portion protruding above a shallow trench isolation (STI) structure (portion of fin-shaped structure below stack 122 disposed above STI 114; Fig. 1; column 7, lines 3-10; column 8, lines 52-57);
a plurality of horizontally stacked nanowires over the sub-fin (horizontally oriented nanowires 126 stacked over portion of fin-shaped structure; Fig. 1; column 7, lines 3-10; column 8, lines 17-57);
a gate dielectric material layer over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires (dielectric layer 172 disposed over portion of fin-shaped structure and STI 114 and around nanowires 126; Fig. 9; column 11, lines 21-31);
a conductive gate layer over the gate dielectric material layer (metal layer 196 disposed over dielectric layer 172; Fig. 17; column 12, line 66 to column 13, line 24);
a conductive gate fill material over the conductive gate layer (gate metal layer 204 disposed over layer 172; Fig. 17; column 13, lines 36-45);
a dielectric gate wall laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure (iterations of isolation pillars 160 laterally spaced apart from fin-shaped structure and nanowires 126 but over STI 114; Figs. 2 and 17; column 8, line 58 to column 9, line 25), wherein the gate dielectric material layer is along a side of the dielectric gate wall and extends above a top surface of the dielectric gate wall (dielectric layer 172 material disposed along side and top surface of isolation pillars 160; Fig. 9); and
a dielectric gate plug on the dielectric gate wall (isolation region 208 disposed over one of pillars 160; Fig. 17; column 14, lines 16-39).
Chanemougame fails to disclose a dielectric gate cap over the conductive gate fill material, the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap.
However, Bhuwalka discloses a dielectric gate cap over the conductive gate fill material (gate capping layer 175 disposed over gate electrode layer; Fig. 2; paragraph [0023]); the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap (gate capping layer 175 contacts and terminates in the same horizontal plane as gate isolation portion 180; Fig. 2; paragraph [0023]).
Chanemougame and Bhuwalka are considered to be analogous to the claimed invention because they are in the same field of nanostructured semiconductor device fabrication. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chanemougame to incorporate the teachings of Bhuwalka in order to potentially provide reduced parasitic capacitance, prevention of electrical shorts and improved yield, and reduction of time-dependent dielectric breakdown.
Regarding claim 17, Chanemougame in view of Bhuwalka discloses the computing device of claim 16, further comprising: a memory coupled to the board (computer product having motherboard, processor, and memory; column 5, line 55 to column 6, line 14; column 16, lines 4-21).
Regarding claim 18, Chanemougame in view of Bhuwalka discloses the computing device of claim 16, further comprising: a communication chip coupled to the board (chip package having interconnections and signal processing device on motherboard; column 16, lines 4-21).
Regarding claim 19, Chanemougame in view of Bhuwalka discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die (packaged IC die; column 16, lines 4-21).
Regarding claim 20, Chanemougame in view of Bhuwalka discloses the computing device of claim 16, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (packaged IC having signal processor; column 16, lines 4-21).
Response to Arguments
Applicant's arguments filed April 9, 2026 have been fully considered. Applicant presents substantive amendments to claims 1 and 16 with corresponding arguments. Specifically, Applicant argues that amendments made to claims 1 and 16 overcome the 35 USC 103 rejection using Chanemougame in view of Bhuwalka. Examiner disagrees and notes that the dielectric gate wall is mapped to pillars 160, not element 210 as asserted by Applicant. Accordingly, Examiner directs Applicant’s attention to Fig. 9 which clearly shows dielectric layer 172 being disposed upon the side and top surface of pillars 160. Therefore, amended claims 1 and 16 do not overcome the 35 USC 103 rejection using Chanemougame in view of Bhuwalka.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights