CTFR 17/482,747 CTFR 99861 Detailed Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims The following is in response to the communication filed. Claims 1, 3-7, 9-11, 13-20 are currently pending. Claims 1, 7, 11, 16, and 18 have been amended. Claims 4, 11, 13-17, and 20 have been withdrawn. 12-151-10 AIA 12-51-10 Claim s 2, 8, and 19 have been canceled. Regarding claim 12, there remains a concern about clarifying the status and potentially missing claim text. As noted in the nonfinal dated 4/7/2026, Examiner explained that it appeared the claim was cancelled, as there was no claim text. Yet the status identified remained as Withdrawn. In the most recent claim set dated 7/7/2026, this same concern exists. Based on Applicant’s response (Remarks, page 10), it seems the intent is that claim 12 is in fact Withdrawn (not cancelled). Therefore, claim 12 will be treated as withdrawn. Applicant, however, must submit a corrected claim set that fixes the missing text issue as explained. Claims 1, 3-7, 9-10, and 18 have been examined. Response to Arguments Applicant’s arguments, see page 7, filed 7/07/2026, with respect to the rejection(s) of claims 1 and 18 under 35 U.S.C. § 103 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. New grounds of rejection is made in further view of Sung et al. US 20210100104 A1. See below for more detail. Claim 11 has been amended but have not been substantively reviewed in light of the fact that these claims are currently withdrawn. Similarly, claims 4, 13-17, and 20 have not been substantively reviewed in light of the fact that these claims currently remain withdrawn. Claim Rejections - 35 USC § 103 07-103 AIA The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. 07-21-aia AIA Claim s 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani et al. US 20190198436 (hereinafter Vadlamani) in view of Lan et. al. US 20210099149 (hereinafter Lan), Chen et al. US 20140117557 A1 (hereinafter Chen), and Sung et al. US 20210100104 A1 (hereinafter Sung) . Regarding claim 1: An electronic package (Vadlamani, Fig. 2a-2n, package structure), comprising: a core (Fig. 2a-2m, core 221), wherein the core comprises glass ([0036], the core may comprise glass); buildup layers over the core (Fig. 2b, buildup layers 211 on surface 205, the bottom surface of core 221); a plug embedded in the buildup layers, wherein the plug comprises a magnetic material (Fig. 2e, magnetic material 210) and wherein a dielectric layer of the buildup layers is vertically intervening between the plug and the core; (Fig. 2m shows a perspective view of the conductive structures 206 formed in serpentine structure which is adjacent to the dielectric material 201 as described in the figures 2a-2l. Therefore there would by necessity be dielectric layers of the buildup material that would be intervening between the plug and the core, even if such is not directly shown in the drawings.) an inductor wrapping around the plug. ([0029], "wherein conductive material may be patterned around the magnetic material to form embedded inductor structures of any desired geometry")… and wherein the inductor (inductor created around plug 210) is coupled to a via (interconnect structure 206 directly over plug 210) through the core (core 221), (Vadlamani, see annotated Fig. 2l above, interconnect structure 206 couples the inductor 210 through the plated through hold 204 that goes through the core 221.)… Vadlamani discloses that the package provides communication between a die and the next level component. Therefore there would by necessity be “a die coupled to the inductor.” Vadlamani does not appear to disclose “wherein the inductor comprises vias that pass through the plug, wherein the vias are coupled together by traces over the plug,” “the via of the inductor having a center in vertical alignment with a center of the via through the core,” or specifically disclose “the die vertically overlapping the plug.” Lan teaches semiconductor devices with integrated passive devices (Lan, [0002]). Note that Fig 3 is an embodiment that can be used in accordance to the embodiment described in Fig. 1 regarding the 3D inductor 180 is surrounding and embedded magnetic core 185. Elements related to the magnetic core 185 were not discuss with Fig. 3 to reduce complication with the figures. See paragraph [0033] for discussion. Lan discloses: wherein the inductor (Lan, Fig. 3, 3D inductor 310 and Fig. 1, 3D inductor 180) comprises vias (Fig. 3, vias 355 and Fig. 1 vias 155) that pass through the plug, (Lan, Fig. 1, embedded magnetic core 185.) wherein the vias (Fig. 3, via 355 and Fig.1 vias 155) are coupled together by traces (Fig. 3, winding portions 313) over the plug (Fig. 1, magnetic core 185). (Lan, Fig. 3, [0033], “Winding for each 3D may be formed using multiple winding portions 311, 312, 313.” And “the third portion of the windings 313 of the 3D inductor 310 may be cross coupled to vias 355 in a generally straight fashion.”) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani to have the inductor comprise vias that pass through the plug and are coupled together by traces over the plug as modified by Lan for purposes of formation of several windings of a 3D inductors for within the same plug. [Lan 0033]. Lan appears to disclose “the via of the inductor (Fig. 1, through substrate-via 115 in the inductor 180 ) having a center in vertical alignment with a center of the via through the core. (Fig. 1, through-substrate via 115 in the passive portion 105. The passive portion being considered the core.) ” Chen, which teaches the interposers having conductive vias and the layout density of those vias (Chen, Abstract), discloses that when those vias are positioned such that they aligned within the face of the conductive vias there is an improvement in the quality of the electrical connection between the conductive via and the conductive through via. (Chen, [0008].) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani as modified by Lan above to have the via of the inductor having a center in vertical alignment with a center of the via through the core as taught by Chen for purposes of having improved electrical connections between the conductive via and conductive vias and conductive through vias because the conductive is directly above and contacting the conductive through via (i.e., having the center in vertical alignment between the different vias). (Chen, [0008].) Vadlamani, Lan, and Chen do not appear to specifically disclose that “the die vertically overlapping with the plug.” Sung, which discloses a inductor structure with a magnetic substance as a support member surrounded by build-up layers (Sung, Abstract) , discloses: the die (Fig. 3, electrical component) vertically overlapping with the plug (200A coil structure which includes body 210 which is a magnetic material. See also Fig. 3.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, and Chen to have the die vertically overlapping with the plug as taught by Sung for purposes of a simpler manufacturing footprint within the size of the board. Regarding claim 5, Vadlamani, Lan, Chen and Sung disclose all the elements of claim 1. Vadlamani further discloses: further comprising: a bridge (at least Fig. 2c, interconnect structures 207 and 206 located to the side of the magnetic material 210. The broadest reasonable definition of bridge being a connection being a communicative coupling to external devices.) embedded in the buildup layers (build up layers 211), wherein the bridge is adjacent to the plug. (at least Fig. 2c, magnetic material 210. The interconnect structures 207 and 206 are adjacent to the magnetic material 210.) See figure below: PNG media_image1.png 680 975 media_image1.png Greyscale 07-22-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani, Lan, Chen and Sung as applied to claim 1 above, and further in view of Ma et. al. US 8207453 (hereinafter Ma) . Regarding claim 3, Vadlamani, Lan, Chen and Sung each the elements of claim 1 as recited above. The combination of Vadlamani, Lan, Chen and Sung do not appear to disclose “wherein the vias of the inductor each have a taper, wherein an end closer to the core is narrower than an end away from the core.” Ma, which teaches an integrated circuit device with a glass core and with electrically conductive terminals on both sides of the glass core (Ma, Abstract), discloses: wherein the vias of the inductor each have a taper, wherein an end closer to the core is narrower than an end away from the core. (Ma, Fig. 1c, vias 139a- c, 149a-c) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substituted of the vias from the device of Vadlamani, Lan, Chen and Sung for the tapered vias of Ma to result in the same device as recited by the claim with the same functionality in a predictable manner. Vadlamani discloses the use of interconnects 206 and 207. Ma discloses vias that have a taper in which the end close to the core is narrower than the end away from the core. The purpose of interconnects/via are to provide electrical connect and one of ordinary skill in the art before the effective filing date of the claimed invention to could have substituted the interconnects of Vadlamani with the via of Ma for the predictable result of providing electrical connection. The substitution of the tapered via’s from Mia would have predictable results when substituted into the device of Vadlamani as modified by Lan, Chen, and Sung. MPEP 2143 (B) . 07-22-aia AIA Claim s 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani, Lan, Chen and Sung as applied to claim 5 above, and further in view of May et al. US 20190341351 (hereinafter May) . Regarding claim 6, Vadlamani, Lan, Chen and Sung teaches the elements of claim 5 as recited above. Vadlamani teaches interconnects 207 and 206 are embedded in the buildup layers which is adjacent to the plug 210, which for the broadest reasonable definition of bridge being a connection being a communicative coupling to external devices. Neither Vadlamani, Lan, Chen and Sung appear to disclose: wherein the bridge comprises through silicon vias. Nor do they appear to teach where the interconnection 207 and 206 are a bridge die. May, which teaches forming microelectronic devices including embedded die substrates (May [0001]). Not only teaches a bridge die (i.e., bridge) with conductive pathways (May, [0002]) but further discloses: wherein the bridge (May, Fig. 2, first embedded die 104 ) comprises through silicon vias. (May, Fig. 2, vertical contacts 116(A) and contacts 118 extend to engage embedded die 104.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, Chen and Sung to have the bridge comprise through silicon vias as modified by May for purposes of facilitating electrical and mechanical coupling with one or more surface dies directly to embedded dies. (May [0021].) Regarding claim 7, Vadlamani, Lan, Chen and Sung the elements of claim 5 as recited above. Vadlamani further teaches that the various embodiments disclosed can be used for system on chip (SOC) products. (Vadlamani, [0069].) Therefore, while not shown in the figures, it’s implied that the device of Vadlamani can be connected to multiple dies since it can be used for SOC products. Vadlamani as modified by Lan, Chen, and Sung does not appear to explicitly teach the electronic package “a second die over the buildup layers, wherein the bridge communicatively couples the die to the second die.” May, which teaches forming microelectronic devices including embedded die substrates (May [0001]). Not only teaches a bridge die (i.e., bridge) with conductive pathways (May, [0002]) but further discloses: further comprising: a second die over the buildup layers (May, Fig. 2 second surface die 212), wherein the bridge (Fig. 2, embedded die 104) communicatively couples the first die to the second die (May, Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, Chen and Sung to have a first die and second die communicatively coupled by an embedded bridge die as disclosed by May for purposes of facilitating electrical and mechanical coupling with one or more surface dies directly to embedded dies. (May [0021].) With this modification, the bridge from Vadlamani (Vadlamani, Fig. 2I , interconnects 207 and 206) would be replaced the bridge die from May (May, Fig. 2, embedded die 104) would result in a device that could electrically communicate with two semiconductor dies on the surface of the device . 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani, Lan, Chen and Sung as applied to claim 1 above, and further in view of Wu et al. US 20210098353 (hereinafter Wu) . Regarding claim 9, Vadlamani, Lan, Chen and Sung teaches the elements of claim 1 as recited above. Vadlamani, Lan, Chen and Sung do not appear to disclose further comprising: a solder resist layer under the core, wherein pads are provided on the solder resist layer Wu, which teaches connecting a semiconductor die with a routing structure, where the routing layer is over a core substrate (Wu, Abstract), discloses: further comprising: a solder resist layer (Wu, Fig. 10, passivation layer 207) under the core (core substrate 202), wherein pads (routing layers 209, 213) are provided on the solder resist layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, Chen and Sung to have a solder resist layer under the core and where pads are provided on the solder resist layer as modified by Wu for purposes of connecting a semiconductor device with a routing structure . 07-22-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani, Lan, Chen, Sung and Wu as applied to claim 9 above, and further in view of May . Regarding claim 10, Vadlamani, Lan, Chen, Sung and Wu teach the elements of claim 9 as recited above. Vadlamani further teaches: the pads (Vadlamani, Fig. 2l, pads 244) Vadlamani as modified Lan, Chen, Sung and Wu appears to be silent regarding that the pads “are coupled to a package substrate with an organic core.” May, which teaches forming microelectronic devices including embedded die substrates, discloses: the pads (May, Fig. 2, lower surface 128) are coupled to a package substrate (May, Fig. 2, interposer 106) with an organic core. (May, [0024], As the interposer of May can include organic material such as cotton-paper reinforced epoxy or the like and it can be formed in a core configuration.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, Chen, Sung, and Wu to have the pads be couple to a package substrate made with an organic core as modified by May for purposes of providing the desired interconnect routing between an electronic package/substrate and external devices. (May, [0023].) 07-21-aia AIA Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani and in view of Lan, Chen, Sung, and May . Regarding claim 18, Vadlamani teaches: An electronic system (Fig. 6, computing system 600 ), comprising: a board (Fig 6, mainboard 602); … a patch (Figs. 2a-2m, package structure) coupled to the package substrate (Vadlamani discloses at [0045] that “A device … may be coupled with the [side] the substrate 202 by via solder structures coupled to the pads 244.”) wherein the patch comprises: a core (Fig. 2a-2m, core 221), wherein the core comprises glass ([0036], the core may comprise glass); buildup layers over the core (Fig. 2b, buildup layers 211 on surface 205, the bottom surface of core 221); a plug embedded in the buildup layers, wherein the plug comprises a magnetic material (Fig. 2e, magnetic material 210) and wherein a dielectric layer of the buildup layers is vertically intervening between the plug and the core; and (Fig. 2m shows a perspective view of the conductive structures 206 formed in serpentine structure which is adjacent to the dielectric material 201 as described in the figures 2a-2l. Therefore there would by necessity be dielectric layers of the buildup material that would be intervening between the plug and the core, even if such is not directly shown in the drawings.) an inductor wrapping around the plug. ([0029], "wherein conductive material may be patterned around the magnetic material to form embedded inductor structures of any desired geometry")… and wherein the inductor (inductor created around plug 210) is coupled to a via (interconnect structure 206 directly over plug 210) through the core (core 221), (Vadlamani, see annotated Fig. 2l above, interconnect structure 206 couples the inductor 210 through the plated through hold 204 that goes through the core 221.)… Vadlamani also, discloses that the package provides communication between a die and the next level component. Therefore there would by necessity be “a die coupled to the inductor.” Vadlamani does not appear to disclose “wherein the inductor comprises vias that pass through the plug, wherein the vias are coupled together by traces over the plug,” “the via of the inductor having a center in vertical alignment with a center of the via through the core,” “a package substrate coupled to the board, wherein the package substrate comprises an organic core,” or specifically disclose “the die vertically overlapping the plug.” Lan teaches semiconductor devices with integrated passive devices (Lan, [0002]). Note that Fig 3 is an embodiment that can be used in accordance to the embodiment described in Fig. 1 regarding the 3D inductor 180 is surrounding and embedded magnetic core 185. Elements related to the magnetic core 185 were note discuss with Fig. 3 to reduce complication with the figures. See paragraph [0033] for discussion. Lan discloses: wherein the inductor (Lan, Fig. 3, 3D inductor 310 and Fig. 1, 3D inductor 180) comprises vias (Fig. 3, vias 355 and Fig. 1 vias 155) that pass through the plug, (Lan, Fig. 1, embedded magnetic core 185.) wherein the vias (Fig. 3, via 355 and Fig.1 vias 155) are coupled together by traces (Fig. 3, winding portions 313) over the plug (Fig. 1, magnetic core 185). (Lan, Fig. 3, [0033], “Winding for each 3D may be formed using multiple winding portions 311, 312, 313.” And “the third portion of the windings 313 of the 3D inductor 310 may be cross coupled to vias 355 in a generally straight fashion.”) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani to have the inductor comprise vias that pass through the plug and are coupled together by traces over the plug as modified by Lan for purposes of formation of several windings of a 3D inductors for within the same plug. [Lan 0033]. Lan further appears to disclose “the via of the inductor (Fig. 1, through substrate-via 115 in the inductor 180 ) having a center in vertical alignment with a center of the via through the core. (Fig. 1, through-substrate via 115 in the passive portion 105. The passive portion being considered the core.) ” Chen, which teaches the interposers having conductive vias and the layout density of those vias (Chen, Abstract), discloses that when those vias are positioned such that they aligned within the face of the conductive vias there is an improvement in the quality of the electrical connection between the conductive via and the conductive through via. (Chen, [0008].) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani as modified by Lan above to have the via of the inductor having a center in vertical alignment with a center of the via through the core as taught by Chen for purposes of having improved electrical connections between the conductive via and conductive vias and conductive through vias because the conductive is directly above and contacting the conductive through via (i.e., having the center in vertical alignment between the different vias). (Chen, [0008].) Vadlamani, Lan, and Chen do not appear to specifically disclose that “the die vertically overlapping with the plug.” Sung, which discloses a inductor structure with a magnetic substance as a support member surrounded by build-up layers (Sung, Abstract) , discloses: the die (Fig. 3, electrical component) vertically overlapping with the plug (200A coil structure which includes body 210 which is a magnetic material. See also Fig. 3.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, and Chen to have the die vertically overlapping with the plug as taught by Sung for purposes of a simpler manufacturing footprint within the size of the board. Vadlamani, Lan, Chen, and Sung appear to be silent on “a package substrate coupled to the board, wherein the package substrate comprises an organic core.” May, which teaches forming microelectronic devices including embedded die substrates, discloses: a package substrate (May, Fig. 2, interposer 106) coupled to the board, wherein the package substrate comprises an organic core; (May, [0024], As the interposer of May can include organic material such as cotton-paper reinforced epoxy or the like and it can be formed in a core configuration.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Vadlamani, Lan, and Chen to have the pads be couple to a package substrate made with an organic core as modified by May for purposes of providing the desired interconnect routing between an electronic package/substrate and external devices. (May, [0023].) Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HEIM KIRIN GREWAL/ Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 17/482,747 Page 2 Art Unit: 2812 Application/Control Number: 17/482,747 Page 3 Art Unit: 2812 Application/Control Number: 17/482,747 Page 4 Art Unit: 2812 Application/Control Number: 17/482,747 Page 5 Art Unit: 2812 Application/Control Number: 17/482,747 Page 6 Art Unit: 2812 Application/Control Number: 17/482,747 Page 7 Art Unit: 2812 Application/Control Number: 17/482,747 Page 8 Art Unit: 2812 Application/Control Number: 17/482,747 Page 9 Art Unit: 2812 Application/Control Number: 17/482,747 Page 10 Art Unit: 2812 Application/Control Number: 17/482,747 Page 11 Art Unit: 2812 Application/Control Number: 17/482,747 Page 12 Art Unit: 2812 Application/Control Number: 17/482,747 Page 13 Art Unit: 2812 Application/Control Number: 17/482,747 Page 14 Art Unit: 2812 Application/Control Number: 17/482,747 Page 15 Art Unit: 2812 Application/Control Number: 17/482,747 Page 16 Art Unit: 2812 Application/Control Number: 17/482,747 Page 17 Art Unit: 2812
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