DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-5 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 recites “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention when combined with the claim limitations of claim 1 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material”. The claim limitations of claim 1 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material” appears to be referring to Fig. 2B which is mutually exclusive and cannot coexist with the claim limitations of claim 4 reciting “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” which appears to be referring to Fig. 3B.
Claim 20 recites “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention when combined with the claim limitations of claim 18 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material”. The claim limitations of claim 18 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material” appears to be referring to Fig. 2B which is mutually exclusive and cannot coexist with the claim limitations of claim 20 reciting “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” which appears to be referring to Fig. 3B.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” is indefinite and unclear when combined with the claim limitations of claim 1 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material”. The claim limitations of claim 1 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material” appears to be referring to Fig. 2B which is mutually exclusive and cannot coexist with the claim limitations of claim 4 reciting “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” which appears to be referring to Fig. 3B.
Claim 4 recites “vias” is indefinite and unclear since claim 1 already recited the term “vias”.
Claim 20 recites “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” is indefinite and unclear when combined with the claim limitations of claim 18 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material”. The claim limitations of claim 18 reciting “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material” appears to be referring to Fig. 2B which is mutually exclusive and cannot coexist with the claim limitations of claim 20 reciting “the inductor comprises vias that pass through the core adjacent to the plug, wherein the vias are coupled together by traces over the plug” which appears to be referring to Fig. 3B.
Claim 20 recites “vias” is indefinite and unclear since claim 1 already recited the term “vias”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 10, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. [U.S. Pub. No. 2015/0235753] in view of Yun et al. [U.S. Pub. No. 2017/0062120], Kidwell, JR. et al. [U.S. Pub. No. 2019/0164681], and Wuenschmann et al. [DE 19608913].
Regarding Claim 1, Chatani et al. shows an electronic package (Fig. 11 with teachings from Figs. 9-10 and Figs. 18-19; see also Fig. 14), comprising:
a core (22), wherein the core comprises prepreg (Paragraph [0117]);
a plug (1) through the core (see Figs. 9-11 and Figs. 18-19), wherein the plug comprises a magnetic material (Paragraph [0061]);
an inductor (element 20 having elements 4, 5, 2, 3) around the plug (see Figs. 9-11 and Figs. 18-19), the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Figs. 9-11 and Figs. 18-19, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3);
first layers (21a, 25a) over the core (see Fig. 11), wherein the first layers comprise a dielectric material (Paragraph [0120]); and
second layers (21b, 25b) under the core (see Fig. 11), wherein the second layers comprise the dielectric material (Paragraph [0120]).
Chatani et al. does not explicitly disclose the core comprises glass.
Yun et al. shows the core (1900, see Figs. 19A-19C) comprises glass (Paragraph [0099]). Yun et al. also discloses first layers (222, Paragraph [0040]) over the core (see Fig. 2), wherein the first layers comprise a dielectric material (Paragraph [0040]); and second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the core comprises glass, first layers over the core and second layers under the core as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to provide a rigid mechanical support to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material as taught by Wuenschmann et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 2, Chatani et al. shows wherein the vias (2, 3) are coupled together by traces (4) over the plug (see Fig. 11).
Regarding Claim 3, Chatani et al. shows the traces (4) are spaced away from the plug (1) by one of the first layers (21a, see Fig. 11).
Regarding Claim 4, Yun et al. shows the inductor (208) comprises vias (273, 233) that pass through the core (220) adjacent to the plug (see Fig. 2), wherein the vias (273, 233) are coupled together by traces (236, 276, Paragraph [0048], see Fig. 2) over the plug (262, 264, see Fig. 2).
Chatani et al. also shows the inductor (Fig. 14) comprises vias (2, 3) that pass through the core (32) adjacent to the plug (see Fig. 14), wherein the vias (2, 3) are coupled together by traces (4) over the plug (see Fig. 14).
Regarding Claim 5, Yun et al. shows the traces (236, 276, Paragraph [0048]) are spaced away from the plug (262, 264) by one of the first layers (222, see Fig. 2, Paragraph [0040]).
Regarding Claim 6, Chatani et al. shows the core (22) has a thickness that is 500µm or greater (0.9 mm, Paragraph [0223]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Regarding Claim 8, Yun et al. shows the magnetic material (262, 264) is a magnetic film (Paragraphs [0042]-[0043]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to increase inductance and help provides an inductor with a high quality factor, and low resistance (Paragraph [0044]).
Kidwell, JR. et al. shows the magnetic material (320, 322) is a magnetic film (Paragraph [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. to achieve desirable magnetic coupling and inductance values as required by design requirements (Paragraph [0039]).
Regarding Claim 10, Yun et al. shows a die (204) coupled to the first layers (222, see Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a die coupled to the first layers as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to establish electrical connection to an external circuit to form an integrated circuit package to achieve desirable operating characteristics based on design requirements (Paragraph [0038]).
Regarding Claim 18, Chatani et al. shows an electronic system (Fig. 11 with teachings from Figs. 9-10 and Figs. 18-19), comprising:
a package substrate (see Fig. 11) comprises:
a core (22), wherein the core comprises prepreg (Paragraph [0117]);
a plug (1) through the core (see Figs. 9-11 and Figs. 18-19), wherein the plug comprises a magnetic material (Paragraph [0061]);
an inductor (element 20 having elements 4, 5, 2, 3) around the plug (see Figs. 9-11 and Figs. 18-19), the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Figs. 9-11 and Figs. 18-19, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3);
first layers (21a, 25a) over the core (see Fig. 11), wherein the first layers comprise a dielectric material (Paragraph [0120]); and
second layers (21b, 25b) under the core (see Fig. 11), wherein the second layers comprise the dielectric material (Paragraph [0120]).
Chatani et al. does not explicitly disclose a board; a package substrate coupled to the board, the core comprises glass, and a die coupled to the package substrate.
Yun et al. shows a board (250); a package substrate (202) coupled to the board (see Fig. 2), the core (1900, see Figs. 19A-19C) comprises glass (Paragraph [0099]), and a die (204) coupled to the package substrate (202, see Fig. 2).
Yun et al. also discloses first layers (222, Paragraph [0040]) over the core (see Fig. 2), wherein the first layers comprise a dielectric material (Paragraph [0040]); and second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a board; a package substrate coupled to the board, the core comprises glass, first layers over the core and second layers under the core, and a die coupled to the package substrate as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to provide a rigid mechanical support to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]) and to establish electrical connection to an external circuit to form an integrated circuit package to achieve desirable operating characteristics based on design requirements (Paragraph [0038]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material as taught by Wuenschmann et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 19, Chatani et al. shows wherein the vias (2, 3) are coupled together by traces (4) over the plug (see Fig. 11).
Regarding Claim 20, Yun et al. shows the inductor (208) comprises vias (273, 233) that pass through the core (220) adjacent to the plug (see Fig. 2), wherein the vias (273, 233) are coupled together by traces (236, 276, Paragraph [0048], see Fig. 2) over the plug (262, 264, see Fig. 2).
Chatani et al. also shows the inductor (Fig. 14) comprises vias (2, 3) that pass through the core (32) adjacent to the plug (see Fig. 14), wherein the vias (2, 3) are coupled together by traces (4) over the plug (see Fig. 14).
Claim(s) 1-6, 8-10, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bharath et al. [U.S. Pub. No. 2020/0066830] in view of Yun et al. [U.S. Pub. No. 2017/0062120], Kidwell, JR. et al. [U.S. Pub. No. 2019/0164681], and Wuenschmann et al. [DE 19608913].
Regarding Claim 1, Bharath et al. shows an electronic package (Figs. 2A-2B or Figs. 3A-3B), comprising:
a core (107), wherein the core comprises glass (Paragraph [0046]);
a plug (103) through the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the plug comprises a magnetic material (Paragraph [0038]);
an inductor (101 or 102) around the plug (see Figs. 2A-2B or Figs. 3A-3B, element 101 or 102 around element 103), the inductor comprising vias (105a), each of the vias (105a) comprising a through plug hole filled with a conductive material (see Figs. 2A-2B or Figs. 3A-3B);
first layers (top elements 106) over the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the first layers comprise a dielectric material (Paragraphs [0034], [0041]); and
second layers (bottom element 106, Paragraph [0034] teaches element 106 can be multiple-layer stack of overlaid sheets of laminated film or build-up film) under the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the second layers comprise the dielectric material (Paragraphs [0034], [0041]).
Bharath et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Furthermore, Yun et al. clearly discloses second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]). Yun et al. also shows an inductor (208) around the plug (262, 264, 266, 268, see Figs. 2-6)
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have second layers as taught by Yun et al. for the electronic package as disclosed by Bharath et al. to facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
Bharath et al. in view of Yun et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
Bharath et al. in view of Yun et al. and Kidwell, JR. et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material as taught by Wuenschmann et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 2, Bharath et al. shows wherein the vias (105a) are coupled together by traces (114a) over the plug (see Figs. 2A-2B or Figs. 3A-3B).
Wuenschmann et al. shows wherein the vias are coupled together by traces (3) over the plug (see Figs. 1-5).
Regarding Claim 3, Yun et al. shows the traces (236, 276, Paragraph [0048]) are spaced away from the plug (262, 264) by one of the first layers (222, see Fig. 2, Paragraph [0040]).
Regarding Claim 4, Yun et al. shows the inductor (208) comprises vias (273, 233) that pass through the core (220) adjacent to the plug (see Fig. 2), wherein the vias (273, 233) are coupled together by traces (236, 276, Paragraph [0048], see Fig. 2) over the plug (262, 264, see Fig. 2).
Regarding Claim 5, Yun et al. shows the traces (236, 276, Paragraph [0048]) are spaced away from the plug (262, 264) by one of the first layers (222, see Fig. 2, Paragraph [0040]).
Regarding Claim 6, Bharath et al. shows the core (107) has a thickness that is 500µm or greater (800 microns, Paragraph [0088]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Regarding Claim 8, Yun et al. shows the magnetic material (262, 264) is a magnetic film (Paragraphs [0042]-[0043]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Yun et al. for the electronic package as disclosed by Bharath et al. to increase inductance and help provides an inductor with a high quality factor, and low resistance (Paragraph [0044]).
Kidwell, JR. et al. shows the magnetic material (320, 322) is a magnetic film (Paragraph [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Kidwell, JR. et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. to achieve desirable magnetic coupling and inductance values as required by design requirements (Paragraph [0039]).
Regarding Claim 9, Bharath et al. shows the magnetic material (103) comprises ferrite filler particles (Paragraphs [0038], [0092], claim 5).
Regarding Claim 10, Bharath et al. shows a die (110) coupled to the first layers (top elements 106, see Figs. 2A-2B or Figs. 3A-3B).
Yun et al. shows a die (204) coupled to the first layers (222, see Fig. 2).
Regarding Claim 18, Bharath et al. shows an electronic system (Figs. 2A-2B or Figs. 3A-3B), comprising:
a board (Paragraphs [0016], [0019], [0047]);
a package substrate (100) coupled to the board (Paragraphs [0016], [0019], [0047]), wherein the package substrate (100) comprises:
a core (107), wherein the core comprises glass (Paragraph [0046]);
a plug (103) through the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the plug comprises a magnetic material (Paragraph [0038]);
an inductor (101 or 102) around the plug (see Figs. 2A-2B or Figs. 3A-3B, element 101 or 102 around element 103), the inductor comprising vias (105a), each of the vias (105a) comprising a through plug hole filled with a conductive material (see Figs. 2A-2B or Figs. 3A-3B);
first layers (top elements 106) over the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the first layers comprise a dielectric material (Paragraphs [0034], [0041]); and
second layers (bottom element 106, Paragraph [0034] teaches element 106 can be multiple-layer stack of overlaid sheets of laminated film or build-up film) under the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the second layers comprise the dielectric material (Paragraphs [0034], [0041]); and
a die (110) coupled to the package substrate (100, see Figs. 2A-2B or Figs. 3A-3B).
Bharath et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Furthermore, Yun et al. clearly discloses second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]). Yun et al. also shows a board (250); a package substrate (202) coupled to the board (see Fig. 2), and a die (204) coupled to the package substrate (202, see Fig. 2). Yun et al. also shows an inductor (208) around the plug (262, 264, 266, 268, see Figs. 2-6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have second layers as taught by Yun et al. for the electronic package as disclosed by Bharath et al. to facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
Bharath et al. in view of Yun et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
Bharath et al. in view of Yun et al. and Kidwell, JR. et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material as taught by Wuenschmann et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 19, Bharath et al. shows wherein the vias (105a) are coupled together by traces (114a) over the plug (see Figs. 2A-2B or Figs. 3A-3B).
Wuenschmann et al. shows wherein the vias are coupled together by traces (3) over the plug (see Figs. 1-5).
Regarding Claim 20, Yun et al. shows the inductor (208) comprises vias (273, 233) that pass through the core (220) adjacent to the plug (see Fig. 2), wherein the vias (273, 233) are coupled together by traces (236, 276, Paragraph [0048], see Fig. 2) over the plug (262, 264, see Fig. 2).
Claim(s) 1-5, 8, 10, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lan et al. [U.S. Pub. No. 2021/0099149] in view of Yun et al. [U.S. Pub. No. 2017/0062120], Kidwell, JR. et al. [U.S. Pub. No. 2019/0164681], and Wuenschmann et al. [DE 19608913].
Regarding Claim 1, Lan et al. shows an electronic package (Figs. 1-7K), comprising:
a core (152), wherein the core comprises glass (Paragraph [0031]);
a plug (185) through the core (see Figs. 1-7K), wherein the plug comprises a magnetic material (Paragraph [0031]);
an inductor (180) around the plug (see Figs. 1-7K), the inductor comprising vias (181), each of the vias (181) comprising a through plug hole (155) completely filled with a conductive material (see Figs. 1-7K, element 155 is completely filled with a conductive material of elements 181);
first layers (112, 122) over the core (see Figs. 1-7K), wherein the first layers comprise a dielectric material (Paragraph [0027]); and
second layer (142) under the core (see Fig. 1-7K), wherein the second layer comprise the dielectric material (element 142 is an ILD and element 112, 122 are also ILD so therefore can be the dielectric material).
Lan et al. does not explicitly disclose second layers under the core.
Yun et al. shows the core (1900, see Figs. 19A-19C) comprises glass (Paragraph [0099]). Yun et al. also discloses first layers (222, Paragraph [0040]) over the core (see Fig. 2), wherein the first layers comprise a dielectric material (Paragraph [0040]); and second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have second layers as taught by Yun et al. for the electronic package as disclosed by Lan et al. to facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Lan et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material as taught by Wuenschmann et al. for the electronic package as disclosed by Lan et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 2, Lan et al. shows wherein the vias (181) are coupled together by traces (182) over the plug (see Figs. 1-7K).
Wuenschmann et al. shows wherein the vias are coupled together by traces (3) over the plug (see Figs. 1-5).
Regarding Claim 3, Lan et al. shows the traces (182) are spaced away from the plug (185) by one of the first layers (112, see Figs. 1-7K).
Yun et al. shows the traces (236, 276, Paragraph [0048]) are spaced away from the plug (262, 264) by one of the first layers (222, see Fig. 2, Paragraph [0040]).
Regarding Claim 4, Yun et al. shows the inductor (208) comprises vias (273, 233) that pass through the core (220) adjacent to the plug (see Fig. 2), wherein the vias (273, 233) are coupled together by traces (236, 276, Paragraph [0048], see Fig. 2) over the plug (262, 264, see Fig. 2).
Regarding Claim 5, Yun et al. shows the traces (236, 276, Paragraph [0048]) are spaced away from the plug (262, 264) by one of the first layers (222, see Fig. 2, Paragraph [0040]).
Regarding Claim 8, Yun et al. shows the magnetic material (262, 264) is a magnetic film (Paragraphs [0042]-[0043]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Yun et al. for the electronic package as disclosed by Lan et al. to increase inductance and help provides an inductor with a high quality factor, and low resistance (Paragraph [0044]).
Kidwell, JR. et al. shows the magnetic material (320, 322) is a magnetic film (Paragraph [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Kidwell, JR. et al. for the electronic package as disclosed by Lan et al. in view of Yun et al. to achieve desirable magnetic coupling and inductance values as required by design requirements (Paragraph [0039]).
Regarding Claim 10, Yun et al. shows a die (204) coupled to the first layers (222, see Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a die coupled to the first layers as taught by Yun et al. for the electronic package as disclosed by Lan et al. to establish electrical connection to an external circuit to form an integrated circuit package to achieve desirable operating characteristics based on design requirements (Paragraph [0038]).
Regarding Claim 18, Lan et al. shows an electronic system (Figs. 1-7K), comprising:
a package substrate (see Figs. 1-7K) comprises:
a core (152), wherein the core comprises glass (Paragraph [0031]);
a plug (185) through the core (see Figs. 1-7K), wherein the plug comprises a magnetic material (Paragraph [0031]);
an inductor (180) around the plug (see Figs. 1-7K), the inductor comprising vias (181), each of the vias (181) comprising a through plug hole (155) completely filled with a conductive material (see Figs. 1-7K, element 155 is completely filled with a conductive material of elements 181);
first layers (112, 122) over the core (see Figs. 1-7K), wherein the first layers comprise a dielectric material (Paragraph [0027]); and
second layer (142) under the core (see Fig. 1-7K), wherein the second layer comprise the dielectric material (element 142 is an ILD and element 112, 122 are also ILD so therefore can be the dielectric material).
Lan et al. does not explicitly disclose a board; a package substrate coupled to the board, the core comprises glass, second layers under the core, and a die coupled to the package substrate.
Yun et al. shows a board (250); a package substrate (202) coupled to the board (see Fig. 2), the core (1900, see Figs. 19A-19C) comprises glass (Paragraph [0099]), and a die (204) coupled to the package substrate (202, see Fig. 2).
Yun et al. also discloses first layers (222, Paragraph [0040]) over the core (see Fig. 2), wherein the first layers comprise a dielectric material (Paragraph [0040]); and second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a board; a package substrate coupled to the board, the core comprises glass, first layers over the core and second layers under the core, and a die coupled to the package substrate as taught by Yun et al. for the electronic package as disclosed by Lan et al. to provide a rigid mechanical support to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]) and to establish electrical connection to an external circuit to form an integrated circuit package to achieve desirable operating characteristics based on design requirements (Paragraph [0038]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Lan et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material as taught by Wuenschmann et al. for the electronic package as disclosed by Lan et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 19, Lan et al. shows wherein the vias (181) are coupled together by traces (182) over the plug (see Figs. 1-7K).
Wuenschmann et al. shows wherein the vias are coupled together by traces (3) over the plug (see Figs. 1-5).
Regarding Claim 20, Yun et al. shows the inductor (208) comprises vias (273, 233) that pass through the core (220) adjacent to the plug (see Fig. 2), wherein the vias (273, 233) are coupled together by traces (236, 276, Paragraph [0048], see Fig. 2) over the plug (262, 264, see Fig. 2).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claim 1 above, and further in view of Chatani et al. [U.S. Pub. No. 2015/0235753].
Regarding Claim 3, Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
In addition, Chatani et al. shows the traces (4) are spaced away from the plug (1) by one of the first layers (21a, see Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the traces are spaced away from the plug by one of the first layers as taught by Chatani et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to facilitate insulation to prevent unwanted connections and short circuits for reliability (Paragraph [0029]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claim 1 above, and further in view of Bharath et al. [U.S. Pub. No. 2020/0066830].
Regarding Claim 6, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the core has a thickness that is 500µm or greater.
Bharath et al. shows the core (107) has a thickness that is 500µm or greater (800 microns, Paragraph [0088]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the core has a thickness that is 500µm or greater as taught by Bharath et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to facilitate sufficient distance between the conductors and/or traces to achieve desirable coupling characteristics based on design requirements and provide a rigid mechanical support (Paragraph [0046]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claim 1 above, and further in view of Do et al. [U.S. Pub. No. 2020/0066627].
Regarding Claim 7, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material is a magnetic paste.
Do et al. shows an inductor coil (Figs. 1A-2O) teaching and suggesting the magnetic material (110a) is a magnetic paste (Paragraphs [0072], [0078]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic paste as taught by Do et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the cavity be backfilled with magnetic paste so that the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0078]).
Regarding Claim 9, Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material comprises ferrite filler particles.
Do et al. shows an inductor coil (Figs. 1A-2O) teaching and suggesting the magnetic material (110a) comprises ferrite filler particles (Paragraph [0037], claim 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material comprises ferrite filler particles as taught by Do et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0078]).
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claim 1 above, and further in view of Do et al. [U.S. Pub. No. 2020/0066634] (hereinafter as “Do ‘634”).
Regarding Claim 7, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material is a magnetic paste.
Do ‘634 shows an inductor coil (Figs. 1A-3M) teaching and suggesting the magnetic material (104a) is a magnetic paste (Paragraphs [0078], [0085]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic paste as taught by Do ‘634 for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the cavity be backfilled with magnetic paste so that the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0085]).
Regarding Claim 9, Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material comprises ferrite filler particles.
Do ‘634 shows an inductor coil (Figs. 1A-2O) teaching and suggesting the magnetic material (104a) comprises ferrite filler particles (Paragraphs [0041]-[0042], claim 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material comprises ferrite filler particles as taught by Do ‘634 for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Lan et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0085]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 08/20/2025 have been fully considered but they are not persuasive.
In response to applicant’s arguments that Chatani et al. does not show “the inductor comprising vias, each of the vias comprising a through plug hole completely filled with a conductive material” is found not persuasive because Chatani et al. clearly shows the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Figs. 9-11 and Figs. 18-19, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZFUNG J CHAN whose telephone number is (571)270-7981. The examiner can normally be reached M-TH 8:00AM-6:00PM.
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837
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