DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/19/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “vias” is indefinite and unclear since claim 1 already recited the term “vias”. As best understood, the examiner will interpret “vias” in claim 4 to be different from “the vias” in claim 1.
Claim 20 recites “vias” is indefinite and unclear since claim 18 already recited the term “vias”. As best understood, the examiner will interpret “vias” in claim 20 to be different from “the vias” in claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 8, 10, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. [U.S. Pub. No. 2015/0235753] in view of Yun et al. [U.S. Pub. No. 2017/0062120], Kidwell, JR. et al. [U.S. Pub. No. 2019/0164681], and Wuenschmann et al. [DE 19608913].
Regarding Claim 1, Chatani et al. shows an electronic package (Fig. 1), comprising:
a plug (1), wherein the plug comprises a magnetic material (Paragraph [0061]);
an inductor (element 10 having elements 4, 5, 2, 3) around the plug (see Fig. 1), the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Fig. 1, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3), wherein the vias (2, 3) are coupled together by one (4) or more traces directly on a top surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 4 directly on a top surface of element 1) and by one (5) or more traces directly on a bottom surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 5 directly on a bottom surface of element 1).
Chatani et al. does not explicitly disclose a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material.
Yun et al. shows a core (1900), wherein the core (1900, see Figs. 19A-19C) comprises glass (Paragraph [0099]), a plug (1902) through the core (see Figs. 19A-19C), first layers (222, Paragraph [0040]) over the core (see Fig. 2), wherein the first layers comprise a dielectric material (Paragraph [0040]); and second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to provide a rigid mechanical support to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation); wherein the vias (conductive material for element 2) are coupled together by one (top element 3) or more traces directly on a top surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by top element 3 directly on a top surface of element 1) and by one (bottom element 3) or more traces directly on a bottom surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by bottom element 3 directly on a bottom surface of element 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material and the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug as taught by Wuenschmann et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 6, Chatani et al. shows the core (22) has a thickness that is 500µm or greater (0.9 mm, Paragraph [0223]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Regarding Claim 8, Yun et al. shows the magnetic material (262, 264) is a magnetic film (Paragraphs [0042]-[0043]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to increase inductance and help provides an inductor with a high quality factor, and low resistance (Paragraph [0044]).
Kidwell, JR. et al. shows the magnetic material (320, 322) is a magnetic film (Paragraph [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. to achieve desirable magnetic coupling and inductance values as required by design requirements (Paragraph [0039]).
Regarding Claim 10, Yun et al. shows a die (204) coupled to the first layers (222, see Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a die coupled to the first layers as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to establish electrical connection to an external circuit to form an integrated circuit package to achieve desirable operating characteristics based on design requirements (Paragraph [0038]).
Regarding Claim 18, Chatani et al. shows an electronic system (Fig. 1), comprising:
a plug (1), wherein the plug comprises a magnetic material (Paragraph [0061]);
an inductor (element 10 having elements 4, 5, 2, 3) around the plug (see Fig. 1), the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Fig. 1, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3), wherein the vias (2, 3) are coupled together by one (4) or more traces directly on a top surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 4 directly on a top surface of element 1) and by one (5) or more traces directly on a bottom surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 5 directly on a bottom surface of element 1).
Chatani et al. does not explicitly disclose a board; a package substrate coupled to the board, a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material, and a die coupled to the package substrate.
Yun et al. shows a board (250); a package substrate (202) coupled to the board (see Fig. 2), a core (1900), wherein the core (1900, see Figs. 19A-19C) comprises glass (Paragraph [0099]), a plug (1902) through the core (see Figs. 19A-19C), first layers (222, Paragraph [0040]) over the core (see Fig. 2), wherein the first layers comprise a dielectric material (Paragraph [0040]); and second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]), and a die (204) coupled to the package substrate (202, see Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a board; a package substrate coupled to the board, a core, wherein the core comprises glass, a plug through the core, and a die coupled to the package substrate, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material as taught by Yun et al. for the electronic package as disclosed by Chatani et al. to provide a rigid mechanical support to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]) and to establish electrical connection to an external circuit to form an integrated circuit package to achieve desirable operating characteristics based on design requirements (Paragraph [0038]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation); wherein the vias (conductive material for element 2) are coupled together by one (top element 3) or more traces directly on a top surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by top element 3 directly on a top surface of element 1) and by one (bottom element 3) or more traces directly on a bottom surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by bottom element 3 directly on a bottom surface of element 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material and the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug as taught by Wuenschmann et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Claim(s) 1, 4, 6, 8-10, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. [U.S. Pub. No. 2015/0235753] in view of Bharath et al. [U.S. Pub. No. 2020/0066830], Kidwell, JR. et al. [U.S. Pub. No. 2019/0164681], and Wuenschmann et al. [DE 19608913].
Regarding Claim 1, Chatani et al. shows an electronic package (Fig. 1), comprising:
a plug (1), wherein the plug comprises a magnetic material (Paragraph [0061]);
an inductor (element 10 having elements 4, 5, 2, 3) around the plug (see Fig. 1), the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Fig. 1, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3), wherein the vias (2, 3) are coupled together by one (4) or more traces directly on a top surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 4 directly on a top surface of element 1) and by one (5) or more traces directly on a bottom surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 5 directly on a bottom surface of element 1).
Chatani et al. does not explicitly disclose a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material.
Bharath et al. shows an electronic package (Figs. 2A-2B or Figs. 3A-3B), comprising: a core (107), wherein the core comprises glass (Paragraph [0046]); a plug (103) through the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the plug comprises a magnetic material (Paragraph [0038]); wherein the vias (105a) are coupled together by one or more traces (114a or 114b) directly on a top surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 114a or 114b directly on a top surface of element 103) and by one or more traces (115) directly on a bottom surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 115 directly on a bottom surface of element 103); first layers (top elements 106) over the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the first layers comprise a dielectric material (Paragraphs [0034], [0041]); and second layers (bottom element 106, Paragraph [0034] teaches element 106 can be multiple-layer stack of overlaid sheets of laminated film or build-up film) under the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the second layers comprise the dielectric material (Paragraphs [0034], [0041]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material as taught by Bharath et al. for the electronic package as disclosed by Chatani et al. to provide a rigid mechanical support for the fabrication of a cored package substrate to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0046]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Bharath et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation); wherein the vias (conductive material for element 2) are coupled together by one (top element 3) or more traces directly on a top surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by top element 3 directly on a top surface of element 1) and by one (bottom element 3) or more traces directly on a bottom surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by bottom element 3 directly on a bottom surface of element 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material and the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug as taught by Wuenschmann et al. for the electronic package as disclosed by Chatani et al. in view of Bharath et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 4, Bharath et al. shows further comprises vias (108) that pass through the core (107) adjacent to the plug (103).
Regarding Claim 6, Chatani et al. shows the core (22) has a thickness that is 500µm or greater (0.9 mm, Paragraph [0223]).
Bharath et al. shows the core (107) has a thickness that is 500µm or greater (800 microns, Paragraph [0088]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Regarding Claim 8, Kidwell, JR. et al. shows the magnetic material (320, 322) is a magnetic film (Paragraph [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Bharath et al. to achieve desirable magnetic coupling and inductance values as required by design requirements (Paragraph [0039]).
Regarding Claim 9, Bharath et al. shows the magnetic material (103) comprises ferrite filler particles (Paragraphs [0038], [0092], claim 5).
Regarding Claim 10, Bharath et al. shows a die (110) coupled to the first layers (top elements 106, see Figs. 2A-2B or Figs. 3A-3B).
Regarding Claim 18, Chatani et al. shows an electronic system (Fig. 1), comprising:
a plug (1), wherein the plug comprises a magnetic material (Paragraph [0061]);
an inductor (element 10 having elements 4, 5, 2, 3) around the plug (see Fig. 1), the inductor comprising vias (2, 3), each of the vias (2, 3) comprising a through plug hole (through plug hole of element 1 for elements 2, 3) completely filled with a conductive material (see Fig. 1, through plug hole of element 1 is completely filled with a conductive material of elements 2, 3), wherein the vias (2, 3) are coupled together by one (4) or more traces directly on a top surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 4 directly on a top surface of element 1) and by one (5) or more traces directly on a bottom surface of the plug (see Fig. 1, elements 2, 3 are coupled together by element 5 directly on a bottom surface of element 1).
Chatani et al. does not explicitly disclose a board; a package substrate coupled to the board, a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material, and a die coupled to the package substrate.
Bharath et al. shows an electronic system (Figs. 2A-2B or Figs. 3A-3B), comprising: a board (Paragraphs [0016], [0019], [0047]); a package substrate (100) coupled to the board (Paragraphs [0016], [0019], [0047]), wherein the package substrate (100) comprises: a core (107), wherein the core comprises glass (Paragraph [0046]); a plug (103) through the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the plug comprises a magnetic material (Paragraph [0038]); wherein the vias (105a) are coupled together by one or more traces (114a or 114b) directly on a top surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 114a or 114b directly on a top surface of element 103) and by one or more traces (115) directly on a bottom surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 115 directly on a bottom surface of element 103); first layers (top elements 106) over the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the first layers comprise a dielectric material (Paragraphs [0034], [0041]); and second layers (bottom element 106, Paragraph [0034] teaches element 106 can be multiple-layer stack of overlaid sheets of laminated film or build-up film) under the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the second layers comprise the dielectric material (Paragraphs [0034], [0041]); and a die (110) coupled to the package substrate (100, see Figs. 2A-2B or Figs. 3A-3B).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a board; a package substrate coupled to the board, a core, wherein the core comprises glass, a plug through the core, first layers over the core, wherein the first layers comprise a dielectric material, and second layers under the core, wherein the second layers comprise the dielectric material, and a die coupled to the package substrate as taught by Bharath et al. for the electronic package as disclosed by Chatani et al. to provide a rigid mechanical support for the fabrication of a cored package substrate to enhance device performance by high-density interconnect, facilitate miniaturization and integration, facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0046]).
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Chatani et al. in view of Bharath et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
In addition, Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation); wherein the vias (conductive material for element 2) are coupled together by one (top element 3) or more traces directly on a top surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by top element 3 directly on a top surface of element 1) and by one (bottom element 3) or more traces directly on a bottom surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by bottom element 3 directly on a bottom surface of element 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material and the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug as taught by Wuenschmann et al. for the electronic package as disclosed by Chatani et al. in view of Bharath et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 20, Bharath et al. shows further comprises vias (108) that pass through the core (107) adjacent to the plug (103).
Claim(s) 1, 4, 6, 8-10, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bharath et al. [U.S. Pub. No. 2020/0066830] in view of Yun et al. [U.S. Pub. No. 2017/0062120], Kidwell, JR. et al. [U.S. Pub. No. 2019/0164681], and Wuenschmann et al. [DE 19608913].
Regarding Claim 1, Bharath et al. shows an electronic package (Figs. 2A-2B or Figs. 3A-3B), comprising:
a core (107), wherein the core comprises glass (Paragraph [0046]);
a plug (103) through the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the plug comprises a magnetic material (Paragraph [0038]);
an inductor (101 or 102) around the plug (see Figs. 2A-2B or Figs. 3A-3B, element 101 or 102 around element 103), the inductor comprising vias (105a), each of the vias (105a) comprising a through plug hole filled with a conductive material (see Figs. 2A-2B or Figs. 3A-3B), wherein the vias (105a) are coupled together by one or more traces (114a or 114b) directly on a top surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 114a or 114b directly on a top surface of element 103) and by one or more traces (115) directly on a bottom surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 115 directly on a bottom surface of element 103);
first layers (top elements 106) over the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the first layers comprise a dielectric material (Paragraphs [0034], [0041]); and
second layers (bottom element 106, Paragraph [0034] teaches element 106 can be multiple-layer stack of overlaid sheets of laminated film or build-up film) under the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the second layers comprise the dielectric material (Paragraphs [0034], [0041]).
Bharath et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Furthermore, Yun et al. clearly discloses second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]). Yun et al. also shows an inductor (208) around the plug (262, 264, 266, 268, see Figs. 2-6)
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have second layers as taught by Yun et al. for the electronic package as disclosed by Bharath et al. to facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
Bharath et al. in view of Yun et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
Bharath et al. in view of Yun et al. and Kidwell, JR. et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation).
Wuenschmann et al. also shows the vias (conductive material for element 2) are coupled together by one (top element 3) or more traces directly on a top surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by top element 3 directly on a top surface of element 1) and by one (bottom element 3) or more traces directly on a bottom surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by bottom element 3 directly on a bottom surface of element 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material and the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug as taught by Wuenschmann et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 4, Bharath et al. shows further comprises vias (108) that pass through the core (107) adjacent to the plug (103).
Regarding Claim 6, Bharath et al. shows the core (107) has a thickness that is 500µm or greater (800 microns, Paragraph [0088]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Regarding Claim 8, Yun et al. shows the magnetic material (262, 264) is a magnetic film (Paragraphs [0042]-[0043]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Yun et al. for the electronic package as disclosed by Bharath et al. to increase inductance and help provides an inductor with a high quality factor, and low resistance (Paragraph [0044]).
Kidwell, JR. et al. shows the magnetic material (320, 322) is a magnetic film (Paragraph [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic film as taught by Kidwell, JR. et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. to achieve desirable magnetic coupling and inductance values as required by design requirements (Paragraph [0039]).
Regarding Claim 9, Bharath et al. shows the magnetic material (103) comprises ferrite filler particles (Paragraphs [0038], [0092], claim 5).
Regarding Claim 10, Bharath et al. shows a die (110) coupled to the first layers (top elements 106, see Figs. 2A-2B or Figs. 3A-3B).
Yun et al. shows a die (204) coupled to the first layers (222, see Fig. 2).
Regarding Claim 18, Bharath et al. shows an electronic system (Figs. 2A-2B or Figs. 3A-3B), comprising:
a board (Paragraphs [0016], [0019], [0047]);
a package substrate (100) coupled to the board (Paragraphs [0016], [0019], [0047]), wherein the package substrate (100) comprises:
a core (107), wherein the core comprises glass (Paragraph [0046]);
a plug (103) through the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the plug comprises a magnetic material (Paragraph [0038]);
an inductor (101 or 102) around the plug (see Figs. 2A-2B or Figs. 3A-3B, element 101 or 102 around element 103), the inductor comprising vias (105a), each of the vias (105a) comprising a through plug hole filled with a conductive material (see Figs. 2A-2B or Figs. 3A-3B), wherein the vias (105a) are coupled together by one or more traces (114a or 114b) directly on a top surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 114a or 114b directly on a top surface of element 103) and by one or more traces (115) directly on a bottom surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 115 directly on a bottom surface of element 103);
first layers (top elements 106) over the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the first layers comprise a dielectric material (Paragraphs [0034], [0041]); and
second layers (bottom element 106, Paragraph [0034] teaches element 106 can be multiple-layer stack of overlaid sheets of laminated film or build-up film) under the core (see Figs. 2A-2B or Figs. 3A-3B), wherein the second layers comprise the dielectric material (Paragraphs [0034], [0041]); and
a die (110) coupled to the package substrate (100, see Figs. 2A-2B or Figs. 3A-3B).
Bharath et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Furthermore, Yun et al. clearly discloses second layers (223, Paragraph [0040]) under the core (see Fig. 2), wherein the second layers comprise the dielectric material (Paragraph [0040]). Yun et al. also shows a board (250); a package substrate (202) coupled to the board (see Fig. 2), and a die (204) coupled to the package substrate (202, see Fig. 2). Yun et al. also shows an inductor (208) around the plug (262, 264, 266, 268, see Figs. 2-6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have second layers as taught by Yun et al. for the electronic package as disclosed by Bharath et al. to facilitate insulation to prevent unwanted connection of adjacent metal layers (Paragraph [0040]).
Bharath et al. in view of Yun et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
In addition, Kidwell, JR. et al. clearly discloses first layers (566, 568) over the core (320, 322), wherein the first layers (566, 568) comprise a dielectric material (Paragraph [0057]); and second layers (562, 564) under the core (320, 322), wherein the second layers comprise the dielectric material (Paragraph [0057]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have first layers and second layers comprise the dielectric material as taught by Kidwell, JR. et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. to simplify design and reduce manufacture time and cost by using the same material while maintaining insulation to prevent shorting of conductors (Paragraph [0057]).
Bharath et al. in view of Yun et al. and Kidwell, JR. et al. does not explicitly disclose each of the vias comprising a through plug hole completely filled with a conductive material.
Wuenschmann et al. clearly show and disclose the inductor (Figs. 1-5) comprising vias (conductive material for element 2), each of the vias (conductive material for element 2) comprising a through plug hole (2) completely filled with a conductive material (see Figs. 1-5, element 2 is completely filled with a conductive material, Paragraph [0021], see English translation).
Wuenschmann et al. also shows the vias (conductive material for element 2) are coupled together by one (top element 3) or more traces directly on a top surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by top element 3 directly on a top surface of element 1) and by one (bottom element 3) or more traces directly on a bottom surface of the plug (see Figs. 1-5, conductive material for element 2 are coupled together by bottom element 3 directly on a bottom surface of element 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the vias comprising a through plug hole completely filled with a conductive material and the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug as taught by Wuenschmann et al. for the electronic package as disclosed by Bharath et al. in view of Yun et al. and Kidwell, JR. et al. to facilitate electrical connection to form an inductor with desirable operating characteristics and inductance values which simplify design and cost effective (see English translation, Abstract, Use/Advantage).
Regarding Claim 20, Bharath et al. shows further comprises vias (108) that pass through the core (107) adjacent to the plug (103).
Claim(s) 4, 6, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claims 1 and 18 above, and further in view of Bharath et al. [U.S. Pub. No. 2020/0066830].
Regarding Claims 4 and 20, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above but does not explicitly show further comprising vias that pass through the core adjacent to the plug.
Bharath et al. shows a package (Figs. 2A) teaching and suggesting further comprising vias (108) that pass through the core (107) adjacent to the plug (103).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have further comprising vias that pass through the core adjacent to the plug as taught by Bharath et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to facilitate electrical connection by interconnect traces disposed over opposing sides of package substrate core to achieve desirable operating characteristics (Paragraph [0047]).
Regarding Claim 6, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
Bharath et al. shows the core (107) has a thickness that is 500µm or greater (800 microns, Paragraph [0088]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the core has a thickness that is 500µm or greater as taught by Bharath et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to facilitate sufficient distance between the conductors and/or traces to achieve desirable coupling characteristics based on design requirements and provide a rigid mechanical support (Paragraph [0046]).
In addition, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the core has a thickness that is 500µm or greater, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art to achieve desirable operating characteristics. In re Aller, 105 USPQ 233.
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claim 1 above, and further in view of Do et al. [U.S. Pub. No. 2020/0066627].
Regarding Claim 7, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material is a magnetic paste.
Do et al. shows an inductor coil (Figs. 1A-2O) teaching and suggesting the magnetic material (110a) is a magnetic paste (Paragraphs [0072], [0078]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic paste as taught by Do et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the cavity be backfilled with magnetic paste so that the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0078]).
Regarding Claim 9, Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material comprises ferrite filler particles.
Do et al. shows an inductor coil (Figs. 1A-2O) teaching and suggesting the magnetic material (110a) comprises ferrite filler particles (Paragraph [0037], claim 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material comprises ferrite filler particles as taught by Do et al. for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0078]).
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. as applied to claim 1 above, and further in view of Do et al. [U.S. Pub. No. 2020/0066634] (hereinafter as “Do ‘634”).
Regarding Claim 7, Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material is a magnetic paste.
Do ‘634 shows an inductor coil (Figs. 1A-3M) teaching and suggesting the magnetic material (104a) is a magnetic paste (Paragraphs [0078], [0085]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material is a magnetic paste as taught by Do ‘634 for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the cavity be backfilled with magnetic paste so that the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0085]).
Regarding Claim 9, Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. shows the claimed invention as applied above.
Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. does not explicitly show the magnetic material comprises ferrite filler particles.
Do ‘634 shows an inductor coil (Figs. 1A-2O) teaching and suggesting the magnetic material (104a) comprises ferrite filler particles (Paragraphs [0041]-[0042], claim 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the magnetic material comprises ferrite filler particles as taught by Do ‘634 for the electronic package as disclosed by Chatani et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. OR Chatani et al. in view of Bharath et al., Kidwell, JR. et al., and Wuenschmann et al. OR Bharath et al. in view of Yun et al., Kidwell, JR. et al., and Wuenschmann et al. to have the magnetic core can be efficiently formed to enhance magnetic properties and increases the inductance density of the inductor structure (Paragraph [0085]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4, 6-10, 18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 01/16/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments that Bharath et al. does not show “the vias are coupled together by one or more traces directly on a top surface of the plug and by one or more traces directly on a bottom surface of the plug” is found not persuasive because Bharath et al. clearly shows the vias (105a) are coupled together by one or more traces (114a or 114b) directly on a top surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 114a or 114b directly on a top surface of element 103) and by one or more traces (115) directly on a bottom surface of the plug (see Figs. 2A-2B or Figs. 3A-3B, element 115 directly on a bottom surface of element 103).
Conclusion
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837
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