CTFR 17/483,498 CTFR 86105 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claims 1-31 are currently pending and have been examined. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-9, 11-18 and 20-31 are rejected under 35 U.S.C. 103 as being unpatentable over Giannacopoulos et al. (U.S. Pub. No. 20150120261 A1) in view of Monga et al. (U.S. Patent No. 11113030 B1) . Giannacopoulos was cited in a previous office action. As per claim 1, Giannacopoulos teaches the invention substantially as claimed including one or more processors, comprising: cause one or more graph computing resources to be used to perform the one or more software kernels of a graphics processing unit (GPU) to be configured independently of performance of the graph code by the GPU using the one or more graph computing resources (par. 0122 The most popular APIs used to implement algorithms on GPUs are the Compute Unified Device Architecture (CUDA) and the Open Computing Language (OpenCL). CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU [to GPU memory independently] and then a collection of kernels [execution graph] are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. [0119], It is expected that adeptly parallel algorithms such as the FMGaBP benefit from the increased parallelism of GPU architectures. [0124] The FN s, VN s, and level matrix data are transferred to the GPU once and hence no GPU-CPU memory transfers are required during the algorithm's execution, [0009]-[0016]) Giannacopoulos does not expressly describe: circuitry to, in response to an application programming interface (API) call: generate graph code to indicate one or more software kernels . However, Monga teaches: circuitry to, in response to an application programming interface (API) call: generate graph code to indicate one or more software kernels (col. 18, lines 11-13 The main class includes control APIs for initializing [generating] the graph …, running the graph (e.g., run( )), and ending the graph; col. 3, lines 31-35 generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of initiating/generating a graph in response to calls to initialize from control APIs of Monga with the system and method of Giannacopoulos resulting in a system and method which provides for generating a graph comprising a collection of kernels to be executed on a GPU responsive to calls from control APIs as in Monga. One of ordinary skill would have been motivated to make this combination for the purpose of improving performance (col. 12, 1-4). As per claim 2, Giannacopoulos further teaches: wherein the API call further causes the circuitry to generate the graph code and instantiate the one or more graph computing resources comprising at least memory of the GPU prior to execution of any of the one or more software kernels of the graph code by the GPU (par. 0122 APIs used to implement algorithms on GPUs … Initially, data has to be explicitly transferred from the CPU memory to GPU [GPU memory] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. 0131 data can be loaded completely i nto shared memory in order to be used by a single FGaBP kernel call reducing communication within the GPU's memory hierarchy). As per claim 3, Giannacopoulos further teaches: wherein the graph code comprises the one or more software kernels (par. 0122 a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 4, Giannacopoulos further teaches: wherein the one or more graph computing resources are configured when the one or more graph computing resources of the GPU are initialized for use by the one or more software kernels of an execution graph of a software program (par. 0122 CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 5, Giannacopoulos does not expressly describe: wherein the one or more graph computing resources are configured by updating the one or more graph computing resources using data previously generated by a software program ( par. 0122 The most popular APIs used to implement algorithms on GPUs are the Compute Unified Device Architecture (CUDA) and the Open Computing Language (OpenCL) . CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU [to GPU memory independently] and then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. [0119], [0124],[0009]- [0016]) . As per claim 6, Giannacopoulos further teaches: wherein in response to the API call, the one or more graph computing resources are to be configured to perform the one or more software kernels of an execution graph for a software program (par. 0122 The most popular APIs … CUDA … used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 7, Giannacopoulos further teaches: wherein the one or more graph computing resources are memory resources of the GPU to be used during execution of the graph code (par. 0122 The most popular APIs used to implement algorithms on GPUs are the Compute Unified Device Architecture (CUDA) and the Open Computing Language (OpenCL) . CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU [GPU memory independently] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 8, Giannacopoulos further teaches: wherein in response to the API call, one or more instructions are to cause a parallel processing library to configure the one or more graph computing resources (par. 0122 APIs used to implement algorithms on GPUs are the Compute Unified Device Architecture (CUDA) and the Open Computing Language (OpenCL). CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 9, it is a system having similar limitations as claim 1. Thus, claim 9 is rejected for the same rationale as applied to claim 1. Giannacopoulos further teaches: memory to store instructions, and one or more processors (par. 151 "storage medium" may represent one or more devices for storing data; par. 0152 one or more processors). As per claim 11, Giannacopoulos further teaches: wherein in response to the API call, the instructions executed by the one or more processors cause the one or more graph computing resources to be usable by the one or more software kernels of an execution graph (par. 0122 Initially, data has to be explicitly transferred from the CPU memory to GPU [GPU memory region] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. 0131 data can be loaded completely into shared memory [initialize] in … GPU's memory). As per claim 12, Giannacopoulos further teaches: wherein the instructions, as a result of execution by the one or more processors, further cause the system to initialize one or more memory regions of the one or more graph computing resources (par. 0122 Initially, d ata has to be explicitly transferred from the CPU memory to GPU [GPU memory region]; par. 0131 data can be loaded completely into shared memory [initialize] in order to be used by a single FGaBP kernel call reducing communication within the GPU's memory ). As per claim 13, it is a system having similar limitations as claim 5. Thus, claim 13 is rejected for the same rationale as applied to claim 5. As per claim 14, it is a system having similar limitations as claim 3. Thus, claim 14 is rejected for the same rationale as applied to claim 3. As per claim 15, Giannacopoulos further teaches: wherein the one or more graph computing resources are memory for the GPU (par. 0131 data can be loaded completely into shared memory in order to be used by a single FGaBP kernel call reducing communication within the GPU's memory hierarchy). As per claim 16, it is a non-transitory machine-readable medium having similar limitations as claim 1. Thus, claim 16 is rejected for the same rationale as applied to claim 1. As per claim 17, Giannacopoulos further teaches: cause the one or more processors to initialize the one or more graph computing resources (par. 0122 Initially, d ata has to be explicitly transferred from the CPU memory to GPU [GPU memory region]; par. 0131 data can be loaded completely into shared memory [initialize] in order to be used by a single FGaBP kernel call reducing communication within the GPU's memory ). As per claim 18, it is a machine-readable medium having similar limitations as claim 5. Thus, claim 18 is rejected for the same rationale as applied to claim 5. As per claim 20, Giannacopoulos further teaches: wherein the one or more graph computing resources comprise memory to be used by one or more software kernels of the graph code (par. 0122 Initially, d ata has to be explicitly transferred from the CPU memory to GPU [GPU memory independently] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. 0131 data can be loaded completely into shared memory in order to be used by a single FGaBP kernel call reducing communication within the GPU's memory ). As per claim 21, Giannacopoulos further teaches: wherein the graph code comprises an execution order of the one or more software kernels (par. 0122 a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. 0148 GPU In addition, the order of the operations may be rearranged). As per claim 22, Giannacopoulos further teaches: cause the one or more graph computing resources to be configured prior to execution of a software program and cause another one or more graph computing resources to be configured prior to execution of another software program (par. 0122 Initially, data has to be explicitly transferred from the PU memory to GPU and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU. Threads are grouped into blocks that are scheduled for execution on the GPU's SM). As per claim 23, Giannacopoulos further teaches: wherein the one or more graph computing resources are memory for the GPU (par. 0122 Initially, d ata has to be explicitly transferred from the CPU memory to GPU [GPU memory] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. 0131 data can be loaded completely into shared memory in order to be used by a single FGaBP kernel call reducing communication within the GPU's memory hierarchy). As per claim 24, Giannacopoulos teaches the invention as claimed including method comprising: receiving an application programming interface (API) call to configure one or more graph computing resources of a graphics processing unit (GPU) (par. 0122 popular APIs … CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU), and in response to the API call: causing the one or more graph computing resources to be used to perform the one or more software kernels to be configured before performance of the graph code by the GPU using the one or more graph computing resources (par. 0122 … Initially, data has to be explicitly transferred from the CPU memory to GPU [GPU memory] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU; par. [0119], It is expected that adeptly parallel algorithms such as the FMGaBP benefit from the increased parallelism of GPU architectures. [0124] The FN s, VN s, and level matrix data are transferred to the GPU once and hence no GPU-CPU memory transfers are required during the algorithm's execution. [0009]-[0016]). Giannacopoulos does not expressly describe: in response to the API call: generating graph code to indicate one or more software kernels to be performed by the GPU . However, Monga teaches: in response to the API call: generating graph code to indicate one or more software kernels to be performed by the GPU (col. 18, lines 11-13 The main class includes control APIs for initializing [generating] the graph …, running the graph (e.g., run( )), and ending the graph; col. 3, lines 31-35 generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of initiating/generating a graph in response to calls to initialize from control APIs of Monga with the system and method of Giannacopoulos resulting in a system and method which provides for generating a graph comprising a collection of kernels to be executed on a GPU responsive to calls from control APIs as in Monga. One of ordinary skill would have been motivated to make this combination for the purpose of improving performance (col. 12, 1-4). As per claim 25, Giannacopoulos further teaches: further comprising initializing the one or more graph computing resources before performance of the graph code by the GPU (par. 0122 … Initially, data has to be explicitly transferred from the CPU memory to GPU [GPU memory] and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 26, Giannacopoulos further teaches: updating the one or more graph computing resources using data generated by a first execution of the graph code before a second execution of the graph code (par. 0080 The FMGaBP algorithm uses the iterative FGaBP as the coarsest level solver. Thus, the algorithm performs iterations based on previous iteration results; par. 0023 iteratively executing the belief propagation update rules until a predetermined condition has been met). As per claim 27, it is method having similar limitations as claim 3. Thus, claim 27 is rejected for the same rationale as applied to claim 3. As per claim 28, it is method having similar limitations as claim 21. Thus, claim 28 is rejected for the same rationale as applied to claim 21. As per claim 29, Giannacopoulos further teaches: in response to receiving the API call, configuring the one or more graph computing resources (par. 0122 APIs used to implement algorithms on GPUs are the Compute Unified Device Architecture (CUDA) … used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU). As per claim 30, Giannacopoulos further teaches: in response to receiving the API call, configuring the one or more graph computing resources in response to an indication to the API to perform the one or more software kernels of an execution graph for a software program (par. 0122 0122] APIs used to implement algorithms on GPUs are the Compute Unified Device Architecture (CUDA) … used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU. Initially, data has to be explicitly transferred from the CPU memory to GPU and a then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU.). As per claim 31 Giannacopoulos further teaches: in response to the API call, executing one or more instructions to cause a parallel processing library to configure the one or more graph computing resources (par. 0122 CUDA 5.0 was used along with the library CUBLAS 5.0 [57] to implement the FMGaBP algorithm on the GPU ... then a collection of kernels are instantiated from the CPU to execute the parallel segments of the program on the GPU) . 07-21-aia AIA Claim s 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Giannacopoulos in view of Monga, and further in view of Liu et al. (U.S. Pub. No. 20210342184 A1) . Liu was cited in a previous office action. As per claim 10, Giannacopoulos and Monga do not expressly describe: wherein the instructions, as a result of execution by the one or more processors, further cause the system to allocate one or more memory regions of the one or more graph computing resources . However, analogous prior art, Liu teaches: wherein the instructions, as a result of execution by the one or more processors, further cause the system to allocate one or more memory regions of the one or more graph computing resources (par. 0030 allocating a memory for an input and an output of a kernel function, executing allocation of a work space memory for the kernel function). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of allocating memory for kernel functions of Liu with the system and method of Giannacopoulos and Monga resulting in a system and method which provides for allocating memory spaces for use by software kernels as in Liu. One of ordinary skill in the art would have been motivated to make this combination for the purpose of reducing data movement during processing of a computing job, and which are beneficial to load balancing (abstract). As per claim 19, it is a non-transitory machine-readable medium having similar limitations as claim 10. Thus, claim 19 is rejected for the same rationale as applied to claim 10 . Response to Arguments 07-37 AIA Applicant's arguments filed 03/02/2026 have been fully considered but they are not persuasive. (1) The applicant argues in pages 8-11 for claim 1 that “n owhere do the cited portions of Giannacopoulos mention … "caus[ing] one or more graph computing resources to be used to perform the one or more software kernels of a graphics processing unit (GPU) to be configured independently of performance of the graph code by the GPU using the one or more graph computing resources" As per point 1, the examiner respectfully submits that prior art cited reasonably teaches all the limitations as claimed. For example, Giannacopoulos, par. 0122, describes that Initially, data has to be explicitly transferred from the CPU memory to GPU [to GPU memory independently] and then a collection of kernels [execution graph] are instantiated from the CPU to execute the parallel segments of the program on the GPU. Further, par. 0124 describes that the FN s, VN s, and level matrix data are transferred to the GPU once and hence no GPU-CPU memory transfers are required during the algorithm's execution. That is, prior to instantiating the execution graph kernels for execution, data is transferred from the CPU memory to the GPU memory, which is same as causing graph computing resources [data and GPU memory] to be configured independently of performing execution graph by the GPU. Therefore, applicant’s arguments are not persuasive . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Pub. No. 20250284567 A1 teaches speculative execution of kernel programs in a chiplet based architecture . 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Willy W. Huaracha whose telephone number is (571) 270-5510. The examiner can normally be reached on M-F 8:30-5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached on (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WH/ Examiner, Art Unit 2195 /BRADLEY A TEETS/ Supervisory Patent Examiner, Art Unit 2197 Application/Control Number: 17/483,498 Page 2 Art Unit: 2197 Application/Control Number: 17/483,498 Page 3 Art Unit: 2197 Application/Control Number: 17/483,498 Page 4 Art Unit: 2197 Application/Control Number: 17/483,498 Page 5 Art Unit: 2197 Application/Control Number: 17/483,498 Page 6 Art Unit: 2197 Application/Control Number: 17/483,498 Page 7 Art Unit: 2197 Application/Control Number: 17/483,498 Page 8 Art Unit: 2197 Application/Control Number: 17/483,498 Page 9 Art Unit: 2197 Application/Control Number: 17/483,498 Page 10 Art Unit: 2197 Application/Control Number: 17/483,498 Page 11 Art Unit: 2197 Application/Control Number: 17/483,498 Page 12 Art Unit: 2197 Application/Control Number: 17/483,498 Page 14 Art Unit: 2197 Application/Control Number: 17/483,498 Page 15 Art Unit: 2197
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