DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/28/2026 has been entered.
Response to Arguments
Applicant's arguments filed 4/28/2026 have been fully considered but they are not persuasive. Applicant argues that a dielectric with traces, as taught by Scheid, cannot read on the claimed “metal layer.” However, the traces within the dielectric are in fact a layer of metal. There is nothing in the claims requiring the metal layer to consist only of metal, and therefore Scheid’s layers can be considered metal layers in the same way that a metallization layer does not contain only metal. Therefore, the rejection is maintained. However, in an effort to advance prosecution, reference Bonilla et al. (US Patent No. 9,502,350) is being introduced below to teach purely metal conformal layers separated by a dielectric.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 25-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scheid et al. (US Publication No. 2010/0308453).
Regarding claim 1, Scheid discloses a conformal power delivery structure comprising (Figure 8):
a first electrically conductive layer (98), the first electrically conductive layer having a non-flat upper surface defining one or more recesses (94a)
a second electrically conductive layer (91a) having a lower surface that generally conforms with the upper surface of the first electrically conductive layer such that one or more portions of the second electrically conductive layer are at least partially (110a) within the recesses defined by the upper surface of the first electrically conductive layer (98)
a dielectric material layer (26/30) in contact with the upper surface of the first electrically conductive layer and the lower surface of the second electrically conductive layer
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Regarding claim 2, Scheid discloses the first electrically conductive layer (98) has a substantially flat lower surface (98 bottom), and the second electrically conductive layer (91a) has a substantially flat upper surface (116a) parallel with the substantially flat lower surface of the first electrically conductive layer (98).
Regarding claim 3, Scheid discloses the second electrically conductive layer (91a) defines one or more openings (94a) on its upper surface and a portion of the first conductive layer (98) is within the openings (94a) of the second electrically conductive layer (91a) (Figure 11).
Regarding claim 4, Scheid discloses at least certain of the openings (94a) of the second electrically conductive layer (91a) are circular, rectangular, oval-shaped, or square-shaped (Figure 11).
Regarding claim 5, Scheid discloses at least certain of the recesses (94a) of the first electrically conductive layer (98) are circular, rectangular, oval- shaped, or square-shaped (Figure 11).
Regarding claim 6, Scheid discloses the first (98) and second (91a) electrically conductive layers are co-planar with one another in areas defined by the recesses (Figure 8).
Regarding claim 7, Scheid discloses a substrate (38), wherein the first electrically conductive layer (98) is on the substrate (38) and the recesses define openings that expose portions of a surface of the substrate to portions of the second electrically conductive layer (91a) (Figure 10).
Regarding claim 8, Scheid discloses a third electrically conductive layer (108a) comprising metal, the third electrically conductive layer defining one or more recesses (defines the bottom of recess 94a), wherein the second electrically conductive layer (91) is at least partially within the recesses of the third electrically conductive layer (108a) and has a lower surface that generally conforms with the upper surface of the third electrically conductive layer, and the dielectric material (112a) is between the surfaces of the third electrically conductive layer (108a) and the second electrically conductive layer (91) that conform with one another.
Regarding claim 25, Scheid discloses a device comprising: a conformal power delivery structure comprising:
a first electrically conductive layer (98)
a second electrically conductive layer (91a) above the first electrically conductive layer, wherein at least one surface of the second electrically conductive layer is conformal with at least one non-fat surface of the first electrically conductive layer
a dielectric material (26/30) in contact with the conformal surfaces of the first electrically conductive layer and the second electrically conductive layer
an integrated circuit die (100a/100b) comprising circuitry (106a) conductively coupled to the conformal power delivery structure (98/91a)
Regarding claim 26, Scheid discloses the first electrically conductive layer (98) and the second electrically conductive (91a) are substantially co-planar (Figure 8).
Regarding claim 27, Scheid discloses the non-flat upper surface of the first electrically conductive layer (98) defines recesses and the lower surface of the second electrically conductive layer (91a) extends into the recesses (Figure 8).
Regarding claim 28, Scheid discloses the first electrically conductive layer (98) defines openings in a lower surface and portions the second electrically conductive layer (91a) are in the openings (Figure 8).
Regarding claim 29, Scheid discloses the second electrically conductive layer (91a) defines openings in an upper surface and portions the first electrically conductive layer (98) are in the openings (Figure 8).
Regarding claim 30, Scheid discloses a lower surface of the first electrically conductive layer (98) is substantially flat and an upper surface of the second electrically conductive layer (91a) is substantially flat.
Regarding claim 31, Scheid discloses the conformal power delivery structure is within a package substrate (38) of the device.
Regarding claim 32, Scheid discloses the conformal power delivery structure is within the integrated circuit die (100a/100b).
Claims 1-8, 25-30, and 32-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bonilla et al. (US Patent No. 9,502,350).
Regarding claim 1, Bonilla discloses a conformal power delivery structure comprising:
a first electrically conductive layer (202), the first electrically conductive layer having a non-flat upper surface defining one or more recesses (Figure 5A)
a second electrically conductive layer (208)) having a lower surface that generally conforms with the upper surface of the first electrically conductive layer (202) such that one or more portions of the second electrically conductive layer are at least partially within the recesses defined by the upper surface of the first electrically conductive layer (Figure 5C)
a dielectric material layer (206) in contact with the upper surface of the first electrically conductive layer (202) and the lower surface of the second electrically conductive layer (208) (Figure 5B)
Regarding claim 2, Bonilla discloses the first electrically conductive layer (202) has a substantially flat lower surface, and the second electrically conductive layer (208) has a substantially flat upper surface parallel with the substantially flat lower surface of the first electrically conductive layer (Figure 5D).
Regarding claim 3, Bonilla discloses the second electrically conductive layer (208) defines one or more openings on its upper surface and a portion of the first conductive layer (202) is within the openings of the second electrically conductive layer (208) (Figure 5D).
Regarding claim 4, Bonilla discloses at least certain of the openings of the second electrically conductive layer are circular, rectangular, oval-shaped, or square-shaped (Figure 5D; col. 4, lines 26-45).
Regarding claim 5, Bonilla discloses at least certain of the recesses of the first electrically conductive layer are circular, rectangular, oval- shaped, or square-shaped (Figure 5D; col. 4, lines 26-45).
Regarding claim 6, Bonilla discloses the first (202) and second (208) electrically conductive layers are co-planar with one another in areas defined by the recesses (Figure 5E).
Regarding claim 7, Bonilla discloses a substrate (200), wherein the first electrically conductive layer (202) is on the substrate (200) and the recesses define openings that expose portions of a surface of the substrate to portions of the second electrically conductive layer (208).
Regarding claim 8, Scheid discloses a third electrically conductive layer (108a) comprising metal, the third electrically conductive layer defining one or more recesses (defines the bottom of recess 94a), wherein the second electrically conductive layer (91) is at least partially within the recesses of the third electrically conductive layer (108a) and has a lower surface that generally conforms with the upper surface of the third electrically conductive layer, and the dielectric material (112a) is between the surfaces of the third electrically conductive layer (108a) and the second electrically conductive layer (91) that conform with one another.
Regarding claim 25, Bonilla discloses a device comprising: a conformal power delivery structure comprising:
a first electrically conductive layer (202)
a second electrically conductive layer (208) above the first electrically conductive layer, wherein at least one surface of the second electrically conductive layer is conformal with at least one non-fat surface of the first electrically conductive layer (Figure 5C)
a dielectric material (206) in contact with the conformal surfaces of the first electrically conductive layer (202) and the second electrically conductive layer (208) (Figure 5B)
an integrated circuit die comprising circuitry (M1) conductively coupled to the conformal power delivery structure (col. 3, lines 49-61)
Regarding claim 26, Bonilla discloses the first electrically conductive layer (202) and the second electrically conductive (208) are substantially co-planar (Figure 5E).
Regarding claim 28, Bonilla discloses the first electrically conductive layer (202) defines openings in a lower surface and portions the second electrically conductive layer (208) are in the openings (Figure 5E).
Regarding claim 29, Bonilla discloses the second electrically conductive layer (208) defines openings in an upper surface and portions the first electrically conductive layer (202) are in the openings (Figure 5D).
Regarding claim 30, Bonilla discloses a lower surface of the first electrically conductive layer (202) is substantially flat and an upper surface of the second electrically conductive layer (208) is substantially flat (Figure 5D).
Regarding claim 32, Bonilla discloses the conformal power delivery structure is within the integrated circuit die (col. 3, lines 49-61).
Regarding claim 33, Bonilla discloses the conformal surfaces of the first electrically conductive layer (202/203) and the second electrically conductive layer (208/210) are separated only by the dielectric material (206).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Scheid et al. (US Publication No. 2010/0308453) in view of Song et al. (US Publication No. 2022/0020735).
Regarding claim 9, Scheid discloses an integrated circuit die (144) comprising the conformal power delivery structure of claim 1, and further comprising: a first set of electrical connectors (144a) on an exterior surface of the die (144), the first set of pads (150a) electrical connectors connected to the first electrically conductive layer (36) by a first set of vias (146a); a second set of electrical connectors (144b) on the exterior surface of the die (144), the second set of electrical connectors connected to the second electrically conductive layer (148) by a second set of vias (146b). Scheid does not disclose logic circuitry is coupled to at least one of the first electrically conductive layer and the second electrically conductive layer. However, Song discloses logic circuitry in a processor in an IC (paragraphs 35-38). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the die of Scheid to include logic circuitry in a processor within the IC, as taught by Song, since it can increase the number of devices and interconnect levels for mobile applications that support multimedia enhancements (paragraphs 2-3).
Regarding claim 10, Scheid discloses the limitations as discussed in the rejection of claim 9 above. Scheid does not disclose the logic circuitry is in a processor within the integrated circuit die. However, Song discloses logic circuitry in a processor in an IC (paragraphs 35-38). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the die of Scheid to include logic circuitry in a processor within the IC, as taught by Song, since it can increase the number of devices and interconnect levels for mobile applications that support multimedia enhancements (paragraphs 2-3).
Regarding claim 11, Scheid discloses a chip package comprising: the integrated circuit die of claim 9; and a package substrate (38) comprising a first power plane (144b) and a second power plane (158a); wherein the first electrically conductive layer (98) of the conformal power delivery structure of the integrated circuit die is connected to the first power plane of the package substrate and the second electrically conductive layer (91) of the conformal power delivery structure of the integrated circuit die is connected to the second power plane of the package substrate (Figures 8-10).
Regarding claim 12, Scheid discloses the conformal power delivery structure is on a surface of the integrated circuit die (144) opposite the package substrate, and the chip package further comprises a thermal interface material in contact with the conformal power delivery structure and a heat sink coupled to the thermal interface material (paragraphs 23 and 30).
Regarding claim 13, Scheid discloses the conformal power delivery structure of the integrated circuit die (144) is a first conformal power delivery structure (91), and the package substrate (38) comprises a second conformal power delivery structure (158a) of claim 1, the first power plane defined by the first electrically conductive layer (91) of the second conformal power delivery structure and the second power plane defined by the second electrically conductive layer (158a) of the second conformal power delivery structure (Figures 8-10).
Regarding claim 14, Scheid discloses a system comprising:
an integrated circuit die (100a/100b)
a package (92) connected to the integrated circuit die (100a/100b) and comprising a conformal power delivery structure, the conformal power delivery structure comprising
a first metal layer (98) having a non-flat upper surface that defines one or more recesses (94a)
a dielectric layer (26/30) on the upper surface of the first metal layer (98)
a second metal layer (91a) on the dielectric layer (26/30), the second metal layer being at least partially (110a) within the recesses of the first metal layer (98) such that a lower surface (116a) of the second metal layer (91a) generally conforms with the upper surface of the first metal layer, the second metal layer defining openings (94a) in an upper surface thereof, wherein at least a portion of the first metal layer (98) is in the openings of the second metal layer (Figure 11)
a first set of vias (144a) connected to the portions of the first metal layer (98) in the openings of the second metal layer (paragraph 104; Figure 8)
a second set of vias (146b) connected to the upper surface of the second metal layer (91a)
Scheid does not disclose the IC die comprises a processor per se. However, Song discloses logic circuitry in a processor in an IC (paragraphs 35-38). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the die of Scheid to include logic circuitry in a processor within the IC, as taught by Song, since it can increase the number of devices and interconnect levels for mobile applications that support multimedia enhancements (paragraphs 2-3).
Regarding claim 15, Scheid discloses a thermal interface material in contact with the integrated circuit die (144) and a heat sink coupled to the thermal interface material (paragraphs 23 and 30).
Regarding claim 16, Scheid discloses a circuit board, wherein the package (92) is connected to the circuit board (38).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 7/23/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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