DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 16, 2026, has been entered.
Claims 1-24 are pending in this office action and presented for examination. Claims 1-4, 9-12, and 17-20 are newly amended by the response received January 16, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “when the field of the single descriptor is a second different value, cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core” in lines 10-13. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0070], “generate the output (e.g., as a single stream)”; paragraph [0094], “generate an output, e.g., as a single stream”; paragraph [00120], “generate the output as a single stream”) does not appear to provide support for causing a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as “a single response to the hardware processor core”. Examiner notes that “a single response” is not necessarily the same scope as “a single stream”.
Claims 2-8 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 9 recites the limitation “in response to receiving the single descriptor, causing a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core when the field of the single descriptor is a second different value” in lines 9-13. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0070], “generate the output (e.g., as a single stream)”; paragraph [0094], “generate an output, e.g., as a single stream”; paragraph [00120], “generate the output as a single stream”) does not appear to provide support for causing a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as “a single response to the hardware processor core”. Examiner notes that “a single response” is not necessarily the same scope as “a single stream”.
Claims 10-16 are rejected for failing to alleviate the rejection of claim 9 above.
Claim 17 recites the limitation “when the field of the single descriptor is a second different value, cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core” in lines 16-19. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0070], “generate the output (e.g., as a single stream)”; paragraph [0094], “generate an output, e.g., as a single stream”; paragraph [00120], “generate the output as a single stream”) does not appear to provide support for causing a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as “a single response to the hardware processor core”. Examiner notes that “a single response” is not necessarily the same scope as “a single stream”.
Claims 18-24 are rejected for failing to alleviate the rejection of claim 17 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “when a field of the single descriptor is a first value, cause a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits to perform an operation indicated in the single descriptor to generate an output, and when the field of the single descriptor is a second different value, cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core” in lines 6-13. However, it is indefinite as to whether the limitation is conveying that an output of “an operation” and the output of “a streaming operation” are the same, in view of the use of antecedent basis language (“the”) in claim 1, line 13, preceding “output”.
Claims 2-8 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 7 recites the limitation “the single stream of output” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 8 recites the limitation “the single stream of output” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 9 recites the limitation “in response to receiving the single descriptor, causing a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits to perform an operation indicated in the single descriptor to generate an output when a field of the single descriptor is a first value; and in response to receiving the single descriptor, causing a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core when the field of the single descriptor is a second different value” in lines 5-13. However, it is indefinite as to whether the limitation is conveying that an output of “an operation” and the output of “a streaming operation” are the same, in view of the use of antecedent basis language (“the”) in claim 9, line 11, preceding “output”.
Claims 10-16 are rejected for failing to alleviate the rejection of claim 9 above.
Claim 15 recites the limitation “the single stream of output” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 16 recites the limitation “the single stream of output” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 17 recites the limitation “when a field of the single descriptor is a first value, cause a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits to perform an operation indicated in the single descriptor to generate an output, and when the field of the single descriptor is a second different value, cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core” in lines 12-19. However, it is indefinite as to whether the limitation is conveying that an output of “an operation” and the output of “a streaming operation” are the same, in view of the use of antecedent basis language (“the”) in claim 17, line 19, preceding “output”.
Claims 18-24 are rejected for failing to alleviate the rejection of claim 17 above.
Claim 23 recites the limitation “the single stream of output” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 24 recites the limitation “the single stream of output” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 9, 13, 17, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sankaran et al. (Sankaran) (US 20190347125 A1).
Consider claim 1, Sankaran discloses an apparatus comprising: a hardware processor core ([0473], line 7, processor cores); and an accelerator circuit coupled to the hardware processor core ([0473], lines 1-2, data streaming accelerator), the accelerator circuit comprising a work dispatcher circuit ([0475], lines 1-5, a second arbiter 3519 arbitrates between batches of work descriptors 3518 provided by the batch processing unit 3516 and individual work descriptors 3514 retrieved from the work queues 3511-3512 and outputs the work descriptors to a work descriptor processing unit 3530) and one or more work execution circuits ([0475], line 5, work descriptor processing unit 3530) to, in response to a single descriptor sent from the hardware processor core ([0437], line 2, descriptors; [0473], lines 1-7, a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). DSA uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores…)): when a field of the single descriptor is a first value ([0503], lines 1-3, a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed; for example, the operation field is a field that comprises a value that does not correspond to the value indicative of a batch descriptor), cause a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits ([0475], lines 1-5, a second arbiter 3519 arbitrates between batches of work descriptors 3518 provided by the batch processing unit 3516 and individual work descriptors 3514 retrieved from the work queues 3511-3512 and outputs the work descriptors to a work descriptor processing unit 3530) to perform an operation indicated in the single descriptor ([0503], lines 1-3, a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed; for example, the operation field is a value that does not correspond to the value indicative of a batch descriptor) to generate an output ([0475], line 8, generate output data), and when the field of the single descriptor is a second different value ([0622], lines 2-3, batch operation 4108), cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core ([0397], lines 1-6, batch processing: some implementations support submitting descriptors in a “batch.” A batch descriptor points to a set of virtually contiguous work descriptors (i.e., descriptors containing actual data operations). When processing a batch descriptor, DSA fetches the work descriptors from the specified memory and processes them; [0473], lines 1-7, a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). DSA uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores…)).
Consider claim 5, Sankaran discloses the apparatus of claim 1 (see above), wherein, when the field of the single descriptor is the second different value, the work dispatcher circuit is to serialize the plurality of jobs by waiting to send a next job of the plurality of jobs to the one or more work execution circuits until an immediately previous job of the plurality of jobs is completed by the one or more work execution circuits ([0552], lines 1-7, software can also specify ordering for descriptors in a batch specified by a Batch descriptor. Each work descriptor has a Fence flag. When set, Fence guarantees that processing of that descriptor will not start until previous descriptors in the same batch are completed. This allows a descriptor with Fence to consume data produced by a previous descriptor in same batch).
Consider claim 9, Sankaran discloses a method comprising: sending, by a hardware processor core of a system ([0473], line 7, processor cores), a single descriptor ([0437], line 2, descriptors; [0473], lines 1-7, a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). DSA uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores…)) to an accelerator circuit coupled to the hardware processor core ([0473], lines 1-2, data streaming accelerator) and comprising a work dispatcher circuit ([0475], lines 1-5, a second arbiter 3519 arbitrates between batches of work descriptors 3518 provided by the batch processing unit 3516 and individual work descriptors 3514 retrieved from the work queues 3511-3512 and outputs the work descriptors to a work descriptor processing unit 3530) and one or more work execution circuits ([0475], line 5, work descriptor processing unit 3530); in response to receiving the single descriptor, causing a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits ([0475], lines 1-5, a second arbiter 3519 arbitrates between batches of work descriptors 3518 provided by the batch processing unit 3516 and individual work descriptors 3514 retrieved from the work queues 3511-3512 and outputs the work descriptors to a work descriptor processing unit 3530) to perform an operation indicated in the single descriptor ([0503], lines 1-3, a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed; for example, the operation field is a value that does not correspond to the value indicative of a batch descriptor) to generate an output ([0475], line 8, generate output data) when a field of the single descriptor is a first value ([0503], lines 1-3, a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed; for example, the operation field is a field that comprises a value that does not correspond to the value indicative of a batch descriptor); and in response to receiving the single descriptor, causing a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core ([0397], lines 1-6, batch processing: some implementations support submitting descriptors in a “batch.” A batch descriptor points to a set of virtually contiguous work descriptors (i.e., descriptors containing actual data operations). When processing a batch descriptor, DSA fetches the work descriptors from the specified memory and processes them; [0473], lines 1-7, a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). DSA uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores…)) when the field of the single descriptor is a second different value ([0622], lines 2-3, batch operation 4108).
Consider claim 13, Sankaran discloses the method of claim 9 (see above), wherein, when the field of the single descriptor is the second different value, the work dispatcher circuit serializes the plurality of jobs by waiting to send a next job of the plurality of jobs to the one or more work execution circuits until an immediately previous job of the plurality of jobs is completed by the one or more work execution circuits ([0552], lines 1-7, software can also specify ordering for descriptors in a batch specified by a Batch descriptor. Each work descriptor has a Fence flag. When set, Fence guarantees that processing of that descriptor will not start until previous descriptors in the same batch are completed. This allows a descriptor with Fence to consume data produced by a previous descriptor in same batch).
Consider claim 17, Sankaran discloses an apparatus comprising: a hardware processor core ([0473], line 7, processor cores) comprising: decoder circuit to decode an instruction comprising an opcode into a decoded instruction (for example, [0789], lines 1-3, the fetched instruction is decoded at 6103. For example, the ENCQMD instruction is decoded by decode circuitry such as that detailed herein), the opcode to indicate an execution circuit is to generate a single descriptor and cause the single descriptor to be sent to an accelerator circuit coupled to the hardware processor core, and the execution circuit, wherein the execution circuit is to execute the decoded instruction according to the opcode ([0791], lines 1-2, the decoded instruction is executed by execution circuitry (hardware); [0479], line 1, software specifies work for DSA through descriptors; [0481], lines 4-7, software prepares the descriptor in memory and submits the descriptor to a Work Queue (WQ) 3511-3512 of the device. The descriptor is submitted to the device using a MOVDIR64B, ENQCMD, or ENQCMDS instruction; FIG. 126B, Decode Unit 12640, Execution Unit(S) 12660; [0473], lines 1-2, data streaming accelerator); and the accelerator circuit, wherein the accelerator circuit comprises a work dispatcher circuit ([0475], lines 1-5, a second arbiter 3519 arbitrates between batches of work descriptors 3518 provided by the batch processing unit 3516 and individual work descriptors 3514 retrieved from the work queues 3511-3512 and outputs the work descriptors to a work descriptor processing unit 3530) and one or more work execution circuits ([0475], line 5, work descriptor processing unit 3530) to, in response to the single descriptor sent from the hardware processor core ([0437], line 2, descriptors; [0473], lines 1-7, a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). DSA uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores…)): when a field of the single descriptor is a first value ([0503], lines 1-3, a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed; for example, the operation field is a field that comprises a value that does not correspond to the value indicative of a batch descriptor), cause a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits ([0475], lines 1-5, a second arbiter 3519 arbitrates between batches of work descriptors 3518 provided by the batch processing unit 3516 and individual work descriptors 3514 retrieved from the work queues 3511-3512 and outputs the work descriptors to a work descriptor processing unit 3530) to perform an operation indicated in the single descriptor ([0503], lines 1-3, a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed; for example, the operation field is a value that does not correspond to the value indicative of a batch descriptor) to generate an output ([0475], line 8, generate output data), and when the field of the single descriptor is a second different value ([0622], lines 2-3, batch operation 4108), cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform a streaming operation indicated in the single descriptor to generate the output as a single response to the hardware processor core ([0397], lines 1-6, batch processing: some implementations support submitting descriptors in a “batch.” A batch descriptor points to a set of virtually contiguous work descriptors (i.e., descriptors containing actual data operations). When processing a batch descriptor, DSA fetches the work descriptors from the specified memory and processes them; [0473], lines 1-7, a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). DSA uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores…)).
Consider claim 21, Sankaran discloses the apparatus of claim 17 (see above), wherein, when the field of the single descriptor is the second different value, the work dispatcher circuit is to serialize the plurality of jobs by waiting to send a next job of the plurality of jobs to the one or more work execution circuits until an immediately previous job of the plurality of jobs is completed by the one or more work execution circuits ([0552], lines 1-7, software can also specify ordering for descriptors in a batch specified by a Batch descriptor. Each work descriptor has a Fence flag. When set, Fence guarantees that processing of that descriptor will not start until previous descriptors in the same batch are completed. This allows a descriptor with Fence to consume data produced by a previous descriptor in same batch).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 10-11, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran as applied to claims 1, 9, and 17 above, and further in view of Fields (US 20060015945 A1) and Schmisseur (US 20020144027 A1).
Consider claim 2, Sankaran discloses the apparatus of claim 1 (see above), wherein the single descriptor comprises a transfer size field of the single descriptor indicating a number of bytes in an input for the streaming operation ([0517], lines 1-3, the transfer size field 3808 indicates the number of bytes to be read from the source address to perform the operation).
However, Sankaran does not disclose the transfer size field of the single descriptor indicating a chunk size and a number of chunks in the input for the streaming operation, and a second field that when set to a first value indicates a transfer size field of the single descriptor indicates a number of bytes in an input for the streaming operation, and when set to a second different value indicates the transfer size field of the single descriptor indicates a chunk size and a number of chunks in the input for the streaming operation.
On the other hand, Fields discloses indicating a chunk size and a number of chunks ([0029], line 3, a first data structure comprising two or more of the following; [0032], lines 1-2, a descriptor that includes the number of chunks in each record; [0033], lines 1-2, a descriptor representing a predetermined size for each chunk). Moreover, Schmisseur discloses using a second field in a descriptor to indicate whether another field indicates a first option or second option ([0033], lines 2-7, logic to selectively process data fields of a data access descriptor as either information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor; [0031], lines 1-11, data in the control field 208 indicates whether the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer, or whether the data access descriptor 200 indicates a memory location of a scatter gather list for processing. For example, one or more bits in the control filed 208 may indicate that the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer located at a "source buffer" address stored in field 202 to a "destination buffer" address stored in field 204; [0032], lines 1-5, The control field 208 may also comprise one or more bits indicating that the data access descriptor 200 is to represent a location of a scatter gather list to be processed beginning at a "scatter gather list address" stored in one or more of the data fields 202 and 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fields and Schmisseur with the invention of Sankaran in order to increase flexibility and capability by supporting both bytes and chunks as options to specify input for an operation.
Consider claim 3, the overall combination entails the apparatus of claim 2 (see above), wherein, when the second field is set to the second different value, the work dispatcher circuit is to cause the one or more work execution circuits to start the streaming operation in response to receiving a first chunk of a plurality of chunks of the input (Fields, [0029], line 3, a first data structure comprising two or more of the following; [0032], lines 1-2, a descriptor that includes the number of chunks in each record; [0033], lines 1-2, a descriptor representing a predetermined size for each chunk; note that for an operation to start operating on a plurality of chunks, a first chunk has to be received).
Consider claim 10, Sankaran discloses the method of claim 9 (see above), wherein the single descriptor comprises a transfer size field of the single descriptor indicating a number of bytes in an input for the streaming operation ([0517], lines 1-3, the transfer size field 3808 indicates the number of bytes to be read from the source address to perform the operation).
However, Sankaran does not disclose the transfer size field of the single descriptor indicating a chunk size and a number of chunks in the input for the streaming operation, and a second field that when set to a first value indicates a transfer size field of the single descriptor indicates a number of bytes in an input for the streaming operation, and when set to a second different value indicates the transfer size field of the single descriptor indicates a chunk size and a number of chunks in the input for the streaming operation.
On the other hand, Fields discloses indicating a chunk size and a number of chunks ([0029], line 3, a first data structure comprising two or more of the following; [0032], lines 1-2, a descriptor that includes the number of chunks in each record; [0033], lines 1-2, a descriptor representing a predetermined size for each chunk). Moreover, Schmisseur discloses using a second field in a descriptor to indicate whether another field indicates a first option or second option ([0033], lines 2-7, logic to selectively process data fields of a data access descriptor as either information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor; [0031], lines 1-11, data in the control field 208 indicates whether the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer, or whether the data access descriptor 200 indicates a memory location of a scatter gather list for processing. For example, one or more bits in the control filed 208 may indicate that the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer located at a "source buffer" address stored in field 202 to a "destination buffer" address stored in field 204; [0032], lines 1-5, The control field 208 may also comprise one or more bits indicating that the data access descriptor 200 is to represent a location of a scatter gather list to be processed beginning at a "scatter gather list address" stored in one or more of the data fields 202 and 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fields and Schmisseur with the invention of Sankaran in order to increase flexibility and capability by supporting both bytes and chunks as options to specify input for an operation.
Consider claim 11, the overall combination entails the method of claim 10 (see above), wherein, when the second field is set to the second different value, the work dispatcher circuit causes the one or more work execution circuits to start the streaming operation in response to receiving a first chunk of a plurality of chunks of the input (Fields, [0029], line 3, a first data structure comprising two or more of the following; [0032], lines 1-2, a descriptor that includes the number of chunks in each record; [0033], lines 1-2, a descriptor representing a predetermined size for each chunk; note that for an operation to start operating on a plurality of chunks, a first chunk has to be received).
Consider claim 18, Sankaran discloses the apparatus of claim 17 (see above), wherein the single descriptor comprises a transfer size field of the single descriptor indicating a number of bytes in an input for the streaming operation ([0517], lines 1-3, the transfer size field 3808 indicates the number of bytes to be read from the source address to perform the operation).
However, Sankaran does not disclose the transfer size field of the single descriptor indicating a chunk size and a number of chunks in the input for the streaming operation, and a second field that when set to a first value indicates a transfer size field of the single descriptor indicates a number of bytes in an input for the streaming operation, and when set to a second different value indicates the transfer size field of the single descriptor indicates a chunk size and a number of chunks in the input for the streaming operation.
On the other hand, Fields discloses indicating a chunk size and a number of chunks ([0029], line 3, a first data structure comprising two or more of the following; [0032], lines 1-2, a descriptor that includes the number of chunks in each record; [0033], lines 1-2, a descriptor representing a predetermined size for each chunk). Moreover, Schmisseur discloses using a second field in a descriptor to indicate whether another field indicates a first option or second option ([0033], lines 2-7, logic to selectively process data fields of a data access descriptor as either information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor; [0031], lines 1-11, data in the control field 208 indicates whether the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer, or whether the data access descriptor 200 indicates a memory location of a scatter gather list for processing. For example, one or more bits in the control filed 208 may indicate that the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer located at a "source buffer" address stored in field 202 to a "destination buffer" address stored in field 204; [0032], lines 1-5, The control field 208 may also comprise one or more bits indicating that the data access descriptor 200 is to represent a location of a scatter gather list to be processed beginning at a "scatter gather list address" stored in one or more of the data fields 202 and 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fields and Schmisseur with the invention of Sankaran in order to increase flexibility and capability by supporting both bytes and chunks as options to specify input for an operation.
Consider claim 19, the overall combination entails the apparatus of claim 18 (see above), wherein, when the second field is set to the second different value, the work dispatcher circuit is to cause the one or more work execution circuits to start the streaming operation in response to receiving a first chunk of a plurality of chunks of the input (Fields, [0029], line 3, a first data structure comprising two or more of the following; [0032], lines 1-2, a descriptor that includes the number of chunks in each record; [0033], lines 1-2, a descriptor representing a predetermined size for each chunk; note that for an operation to start operating on a plurality of chunks, a first chunk has to be received).
Claim(s) 4, 12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran as applied to claims 1, 9, and 17 above, and further in view of Schmisseur (US 20020144027 A1).
Consider claim 4, Sankaran discloses the apparatus of claim 1 (see above), but does not discloses the single descriptor comprises a second field that when set to a first value indicates a source address field or a destination address field of the single descriptor indicates a location of a single contiguous block of an input for the streaming operation or the output, respectively, and when set to a second different value indicates the source address field or the destination address field of the single descriptor indicates a list of multiple non-contiguous locations of the input or the output, respectively.
On the other hand, Schmisseur discloses a single descriptor comprises a second field that when set to a first value indicates a source address field or a destination address field of the single descriptor indicates a location of a single contiguous block of an input for a streaming operation or an output, respectively, and when set to a second different value indicates the source address field or the destination address field of the single descriptor indicates a list of multiple non-contiguous locations of the input or the output, respectively ([0033], lines 2-7, logic to selectively process data fields of a data access descriptor as either information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor; [0031], lines 1-11, data in the control field 208 indicates whether the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer, or whether the data access descriptor 200 indicates a memory location of a scatter gather list for processing. For example, one or more bits in the control filed 208 may indicate that the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer located at a "source buffer" address stored in field 202 to a "destination buffer" address stored in field 204; [0032], lines 1-5, The control field 208 may also comprise one or more bits indicating that the data access descriptor 200 is to represent a location of a scatter gather list to be processed beginning at a "scatter gather list address" stored in one or more of the data fields 202 and 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schmisseur with the invention of Sankaran in order to reduce processing overhead (see Schmisseur, [0037], last 4 lines) and support flexibility by supporting both of the aforementioned options.
Consider claim 12, Sankaran discloses the method of claim 9 (see above), but does not discloses the single descriptor comprises a second field that when set to a first value indicates a source address field or a destination address field of the single descriptor indicates a location of a single contiguous block of an input for the streaming operation or the output, respectively, and when set to a second different value indicates the source address field or the destination address field of the single descriptor indicates a list of multiple non-contiguous locations of the input or the output, respectively.
On the other hand, Schmisseur discloses a single descriptor comprises a second field that when set to a first value indicates a source address field or a destination address field of the single descriptor indicates a location of a single contiguous block of an input for a streaming operation or an output, respectively, and when set to a second different value indicates the source address field or the destination address field of the single descriptor indicates a list of multiple non-contiguous locations of the input or the output, respectively ([0033], lines 2-7, logic to selectively process data fields of a data access descriptor as either information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor; [0031], lines 1-11, data in the control field 208 indicates whether the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer, or whether the data access descriptor 200 indicates a memory location of a scatter gather list for processing. For example, one or more bits in the control filed 208 may indicate that the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer located at a "source buffer" address stored in field 202 to a "destination buffer" address stored in field 204; [0032], lines 1-5, The control field 208 may also comprise one or more bits indicating that the data access descriptor 200 is to represent a location of a scatter gather list to be processed beginning at a "scatter gather list address" stored in one or more of the data fields 202 and 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schmisseur with the invention of Sankaran in order to reduce processing overhead (see Schmisseur, [0037], last 4 lines) and support flexibility by supporting both of the aforementioned options.
Consider claim 20, Sankaran discloses the apparatus of claim 17 (see above), but does not discloses the single descriptor comprises a second field that when set to a first value indicates a source address field or a destination address field of the single descriptor indicates a location of a single contiguous block of an input for the streaming operation or the output, respectively, and when set to a second different value indicates the source address field or the destination address field of the single descriptor indicates a list of multiple non-contiguous locations of the input or the output, respectively.
On the other hand, Schmisseur discloses a single descriptor comprises a second field that when set to a first value indicates a source address field or a destination address field of the single descriptor indicates a location of a single contiguous block of an input for a streaming operation or an output, respectively, and when set to a second different value indicates the source address field or the destination address field of the single descriptor indicates a list of multiple non-contiguous locations of the input or the output, respectively ([0033], lines 2-7, logic to selectively process data fields of a data access descriptor as either information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor; [0031], lines 1-11, data in the control field 208 indicates whether the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer, or whether the data access descriptor 200 indicates a memory location of a scatter gather list for processing. For example, one or more bits in the control filed 208 may indicate that the data access descriptor 200 is to be processed as a DMA descriptor for the transfer of a contiguous data buffer located at a "source buffer" address stored in field 202 to a "destination buffer" address stored in field 204; [0032], lines 1-5, The control field 208 may also comprise one or more bits indicating that the data access descriptor 200 is to represent a location of a scatter gather list to be processed beginning at a "scatter gather list address" stored in one or more of the data fields 202 and 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schmisseur with the invention of Sankaran in order to reduce processing overhead (see Schmisseur, [0037], last 4 lines) and support flexibility by supporting both of the aforementioned options.
Claim(s) 6, 14, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran as applied to claims 1, 9, and 17 above, and further in view of Tomozaki et al. (Tomozaki) (US 7640374 B2).
Consider claim 6, Sankaran discloses the apparatus of claim 1 (see above), wherein the field of the single descriptor is the second different value, the work dispatcher circuit is to send the plurality of jobs to a work execution circuit (see above).
However, Sankaran does not disclose sending the plurality of jobs in parallel to a plurality of work execution circuits.
On the other hand, Tomozaki discloses sending a plurality of jobs in parallel to a plurality of work execution circuits (col. 8, line 67, to col. 9, line 4, allocates the sub-descriptors to a plurality of DMA controllers 4, as shown in FIG. 9. Each DMA controller 4 which receives a sub-descriptor implements the processing of data reading using the sub-descriptor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tomozaki with the invention of Sankaran in order to increase system performance via parallel execution.
Consider claim 14, Sankaran discloses the method of claim 9 (see above), wherein the field of the single descriptor is the second different value, the work dispatcher circuit is to send the plurality of jobs to a work execution circuit (see above).
However, Sankaran does not disclose sending the plurality of jobs in parallel to a plurality of work execution circuits.
On the other hand, Tomozaki discloses sending a plurality of jobs in parallel to a plurality of work execution circuits (col. 8, line 67, to col. 9, line 4, allocates the sub-descriptors to a plurality of DMA controllers 4, as shown in FIG. 9. Each DMA controller 4 which receives a sub-descriptor implements the processing of data reading using the sub-descriptor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tomozaki with the invention of Sankaran in order to increase system performance via parallel execution.
Consider claim 22, Sankaran discloses the apparatus of claim 17 (see above), wherein the field of the single descriptor is the second different value, the work dispatcher circuit is to send the plurality of jobs to a work execution circuit (see above).
However, Sankaran does not disclose sending the plurality of jobs in parallel to a plurality of work execution circuits.
On the other hand, Tomozaki discloses sending a plurality of jobs in parallel to a plurality of work execution circuits (col. 8, line 67, to col. 9, line 4, allocates the sub-descriptors to a plurality of DMA controllers 4, as shown in FIG. 9. Each DMA controller 4 which receives a sub-descriptor implements the processing of data reading using the sub-descriptor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tomozaki with the invention of Sankaran in order to increase system performance via parallel execution.
Claim(s) 7-8, 15-16, and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran as applied to claims 1, 9, and 17 above, and further in view of Burke et al. (Burke) (US 8539124 B1).
Consider claim 7, Sankaran discloses the apparatus of claim 1 (see above), wherein, when the field of the single descriptor is the second different value ([0622], lines 2-3, batch operation 4108) and a field of the single descriptor being set to indicate a functionality (FIG. 41, flags field), and the accelerator circuit outputting a single stream of output ([0473], lines 1-2, data streaming accelerator), but does not disclose when a metadata tagging field of the single descriptor is set, the accelerator circuit is to insert metadata into the single stream of output.
On the other hand, Burke discloses inserting metadata into a single stream of output (col. 5, lines 65-67, in some embodiments, the host driver may insert metadata into the I/O stream that is being written to or read from the data storage).
Burke’s teaching may improve data transfer (Burke, col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burke with the invention of Sankaran in order to improve data transfer. Note that Burke’s teaching of the option of inserting metadata into a single stream of output, when applied to the invention of Sankaran which entails a field of the single descriptor being set to indicate a functionality, results in the overall claimed limitation of, when the field of the single descriptor is the second different value and a metadata tagging field of the single descriptor is set, the accelerator circuit is to insert metadata into the single stream of output.
Consider claim 8, Sankaran discloses the apparatus of claim 1 (see above), wherein, when the field of the single descriptor is the second different value ([0622], lines 2-3, batch operation 4108) and an additional value field of the single descriptor being set to indicate a functionality (FIG. 41, flags field), and the accelerator circuit outputting a single stream of output ([0473], lines 1-2, data streaming accelerator), but does not disclose when an additional value field of the single descriptor is set, the accelerator circuit is to insert one or more additional values into the single stream of output.
On the other hand, Burke discloses inserting one or more additional values into a single stream of output (col. 5, lines 65-67, in some embodiments, the host driver may insert metadata into the I/O stream that is being written to or read from the data storage).
Burke’s teaching may improve data transfer (Burke, col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burke with the invention of Sankaran in order to improve data transfer. Note that Burke’s teaching of the option of inserting one or more additional values into a single stream of output, when applied to the invention of Sankaran which entails a field of the single descriptor being set to indicate a functionality, results in the overall claimed limitation of, when the field of the single descriptor is the second different value and an additional value field of the single descriptor is set, the accelerator circuit is to insert one or more additional values into the single stream of output.
Consider claim 15, Sankaran discloses the method of claim 9 (see above), wherein, when the field of the single descriptor is the second different value ([0622], lines 2-3, batch operation 4108) and a field of the single descriptor being set to indicate a functionality (FIG. 41, flags field), and the accelerator circuit outputting a single stream of output ([0473], lines 1-2, data streaming accelerator), but does not disclose when a metadata tagging field of the single descriptor is set, the accelerator circuit inserts metadata into the single stream of output.
On the other hand, Burke discloses inserting metadata into a single stream of output (col. 5, lines 65-67, in some embodiments, the host driver may insert metadata into the I/O stream that is being written to or read from the data storage).
Burke’s teaching may improve data transfer (Burke, col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burke with the invention of Sankaran in order to improve data transfer. Note that Burke’s teaching of the option of inserting metadata into a single stream of output, when applied to the invention of Sankaran which entails a field of the single descriptor being set to indicate a functionality, results in the overall claimed limitation of, when the field of the single descriptor is the second different value and a metadata tagging field of the single descriptor is set, the accelerator circuit inserts metadata into the single stream of output.
Consider claim 16, Sankaran discloses the method of claim 9 (see above), wherein, when the field of the single descriptor is the second different value ([0622], lines 2-3, batch operation 4108) and an additional value field of the single descriptor being set to indicate a functionality (FIG. 41, flags field), and the accelerator circuit outputting a single stream of output ([0473], lines 1-2, data streaming accelerator), but does not disclose when an additional value field of the single descriptor is set, the accelerator circuit inserts one or more additional values into the single stream of output.
On the other hand, Burke discloses inserting one or more additional values into a single stream of output (col. 5, lines 65-67, in some embodiments, the host driver may insert metadata into the I/O stream that is being written to or read from the data storage).
Burke’s teaching may improve data transfer (Burke, col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burke with the invention of Sankaran in order to improve data transfer. Note that Burke’s teaching of the option of inserting one or more additional values into a single stream of output, when applied to the invention of Sankaran which entails a field of the single descriptor being set to indicate a functionality, results in the overall claimed limitation of, when the field of the single descriptor is the second different value and an additional value field of the single descriptor is set, the accelerator circuit inserts one or more additional values into the single stream of output.
Consider claim 23, Sankaran discloses the apparatus of claim 17 (see above), wherein, when the field of the single descriptor is the second different value ([0622], lines 2-3, batch operation 4108) and a field of the single descriptor being set to indicate a functionality (FIG. 41, flags field), and the accelerator circuit outputting a single stream of output ([0473], lines 1-2, data streaming accelerator), but does not disclose when a metadata tagging field of the single descriptor is set, the accelerator circuit is to insert metadata into the single stream of output.
On the other hand, Burke discloses inserting metadata into a single stream of output (col. 5, lines 65-67, in some embodiments, the host driver may insert metadata into the I/O stream that is being written to or read from the data storage).
Burke’s teaching may improve data transfer (Burke, col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burke with the invention of Sankaran in order to improve data transfer. Note that Burke’s teaching of the option of inserting metadata into a single stream of output, when applied to the invention of Sankaran which entails a field of the single descriptor being set to indicate a functionality, results in the overall claimed limitation of, when the field of the single descriptor is the second different value and a metadata tagging field of the single descriptor is set, the accelerator circuit is to insert metadata into the single stream of output.
Consider claim 24, Sankaran discloses the apparatus of claim 17 (see above), wherein, when the field of the single descriptor is the second different value ([0622], lines 2-3, batch operation 4108) and an additional value field of the single descriptor being set to indicate a functionality (FIG. 41, flags field), and the accelerator circuit outputting a single stream of output ([0473], lines 1-2, data streaming accelerator), but does not disclose when an additional value field of the single descriptor is set, the accelerator circuit is to insert one or more additional values into the single stream of output.
On the other hand, Burke discloses inserting one or more additional values into a single stream of output (col. 5, lines 65-67, in some embodiments, the host driver may insert metadata into the I/O stream that is being written to or read from the data storage).
Burke’s teaching may improve data transfer (Burke, col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burke with the invention of Sankaran in order to improve data transfer. Note that Burke’s teaching of the option of inserting one or more additional values into a single stream of output, when applied to the invention of Sankaran which entails a field of the single descriptor being set to indicate a functionality, results in the overall claimed limitation of, when the field of the single descriptor is the second different value and an additional value field of the single descriptor is set, the accelerator circuit is to insert one or more additional values into the single stream of output.
Response to Arguments
Applicant on page 7 argues: “Paragraph [0083] was inadvertently mentioned in the last response. The Applicant confirms it was not intended to be amended.”
Examiner thanks Applicant for the confirmation for clarity of the record.
Applicant on page 7 argues: “The Applicant respectfully requests suggestions regarding allowability including claim amendment suggestions. Providing this prescribed guidance is in the interest of compact prosecution.”
While Examiner has no suggestions regarding allowability at the current time, one potential avenue of amendment might be to amend the claims in a manner that would preclude the batch descriptor subject matter from reading on the relevant claim language under the broadest reasonable interpretation, in view of Applicant’s arguments that appear to be based on the recited “single descriptor” being different from a batch descriptor.
Applicant on page 7 argues: “Claims 17-24 stand rejected under 35 U.S.C. § 112(b) as allegedly being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Although the Applicant disagrees, the Applicant has amended independent claim 17 merely in the interest of compact prosecution.”
In view of the aforementioned amendment, the previously presented indefinite rejections are withdrawn.
Applicant on page 9 notes that paragraph [0501] of Sankaran recites “In one implementation, for each work descriptor 3514, the engine 3550 pre-fetches the translation for the completion record address, and passes the operation to the work descriptor processing unit 3530. The work descriptor processing unit 3530 uses the Device TLB 1722 and IOMMU 1710 for source and destination address translations, reads source data, performs the specified operation, and writes the destination data back to memory. When the operation is complete, the engine writes the completion record to the pre-translated completion address and generates an interrupt, if requested by the work descriptor.”
However, Examiner submits that this paragraph does not preclude Sankaran from teaching the new amended subject matter. For example, Examiner submits that the aforementioned operations involved in performing an operation of a work descriptor do not preclude Sankaran’s batch descriptor from being considered to indicate a “streaming” operation to be performed by the one or more work execution circuits. For example, as cited, the accelerator of Sankaran is a data stream accelerator that performs streaming operations. For example, Examiner submits that processing the batch descriptor entails obtaining and processing a stream of descriptors to obtain an output. Examiner generally notes that the instant specification does not appear to disclose specifics regarding the “streaming” limitation that would be at odds with Examiner’s interpretation. Additionally, Examiner submits that the aforementioned output is a single response to the batch descriptor sent by the hardware processor core.
Applicant on page 10 argues: ‘As another example, Applicant's paragraph [0090] of the published application recites "In certain examples, streaming descriptor represents a stream/cumulation of individual jobs (e.g., work-items or mini-jobs) and thus removes the need of going back-and-forth to an accelerator, e.g., as in FIG. 9A." (emphasis added).’
However, Examiner submits that Sankaran’s batch descriptor 3515 likewise represents a stream/cumulation of individual jobs (e.g., work-items or mini-jobs)— work descriptors 3518. In addition, as noted in paragraph [0545], “Use of Batch descriptors allows DSA clients to submit multiple work descriptors using a single ENQCMD, ENQCMDS, or MOVDIR64B instruction and can potentially improve overall throughput.” In other words, Sankaran’s batch descriptor likewise removes the need of sending multiple jobs separately as in FIG. 9A.
Conclusion
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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