Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US PgPUB 20210296445 (hereinafter Lee) in view of Hsieh US 20220238677 (hereinafter Hsieh et al.).
Regarding claim 1, Lee discloses a transistor structure (TITLE) in figures 14C and 14D comprising: a gate metal (162) [0109]; a gate oxide (142) [0078] [0110] on around the gate metal (162); and a monolayer (131, 132, 133) [0127-0130] [0090] on the gate oxide (142), the monolayer having a first side (top side) and a second side (bottom side) opposite the first side, wherein a first portion of an edge (left side) of the monolayer between the first side (top side) and the second side (bottom side) of the monolayer is coupled with a surface of a first contact metal (182) [0109], and wherein a second portion of the edge (right side) of the monolayer between the first side (top side) and the second side (bottom side) of the monolayer is coupled with a surface of a second contact metal (192) [0109].
Lee does not disclose the first gate spacer and second gate spacer.
Hsieh et al (US 2022/0238677) teaches a similar structure of LEE. Hsieh (fig. 8) teaches a nanowire transistor comprising: a gate metal (metal layer 52, [0016]); a gate oxide (high-k dielectric layer 48, [0016]-[0017]) around the gate metal (52); a monolayer ( semiconductor layers 22, 24 or 26, “the original cubic second semiconductor layers 22, 24, 26 are transformed into cylindrical nanowire channel layers” [0009] and [0015]) on the gate oxide (48); a first contact metal (contact plug 62 on the left, [0019]); a second contact metal (contact plug 62 on the right, [0019]); a first gate spacer (spacer 34 on the left, [0011]) laterally between a first portion (left portion of the dielectric layer 48) of the gate oxide (48) and the first contact metal (62); and a second gate spacer (spacer 34 on the right, [0011]) laterally between a second portion (right portion of the dielectric layer 48) of the gate oxide (48) and the second contact metal (62), wherein the second portion of the gate oxide (48) is laterally between the gate metal (52) and the second gate spacer (34).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have formed the transistor structure of LEE with spacers 34 in between gate 52 and contact plug 62 of Hsieh in order to “define a NMOS region 82 and a PMOS region 84 on the substrate 12, and then carry out the fabrication processes conducted in FIGS. 1-8 for fabricating source/drain structures 40 and/or contact plugs 62 made of graphene on the NMOS region 82 and PMOS region 84 respectively.” and “boosting the performance of the device significantly.” as taught by Hsieh, [0022] and [0024].
Regarding claim 2, Lee discloses the transistor structure of claim 1 in figures 14C and 14D, wherein the monolayer (131, 132, 133) [0127-0130] [0090] includes a selected one or more of: sulfur (S), selenium (Se), tellurium (Te), tungsten (W), and molybdenum (Mo) [0018] [0019].
Note that Lee discloses that channel layers (131, 132, 133) may be monolayers [0090].
Regarding claim 3, Lee discloses the transistor structure of claim 1 in figures 14C and 14D, wherein the monolayer (133, 132, 133) has a thickness of 3.3 angstroms (A) [0025].
Regarding claim 4, Lee discloses the transistor structure of claim 1 in figures 14C and 14D, wherein the surface of the first contact metal (182) [0109] or the second contact metal (192) [0109] is substantially perpendicular to the first side or the second side of the monolayer.
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Marked Up Figure 14C For Claim 4 Clarification
Regarding claim 5, Lee discloses the transistor structure of claim 1 in figure 14C and 14D, wherein a distance (CL1, CL2, CL3) [0112] along the first side of the monolayer (131, 132, 133) between the surface of the first contact metal (182) and the surface of the second contact metal (192) is less than or equal to 15 nm [0107].
Regarding claim 6, Lee discloses the transistor structure of claim 1 in figure 14C and 14D, wherein the monolayer (133) further includes multiple monolayers (133a, 133b, 133c) [0130] that form a monolayer stack.
Regarding claim 7, Lee discloses the transistor structure of claim 6 in figure 14C and 14D, wherein the multiple monolayers (133a, 133b, 133c) [0130] are directly physically coupled with each other.
Regarding claim 18, Lee discloses a system in figure 14C comprising: a substrate (110) [0119]; and a transistor structure (102’’) [0130] on the substrate (110), the transistor structure comprising: a gate metal (162) [0109]; a gate oxide (142) [0078] [0110] on around the gate metal (162), the gate oxide including hafnium (Hf) [0078]; and a monolayer (131, 132, 133) [0127-0130] [0090] on the gate oxide, the monolayer having a first side (top side) and a second side (bottom side) opposite the first side, wherein a first portion of an edge (left side)of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a first contact metal (182) [0109], and wherein a second portion of the edge (right side) of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a second contact metal (192) [0109].
Lee does not disclose the first gate spacer and second gate spacer.
Hsieh et al (US 2022/0238677) teaches a similar structure of LEE. Hsieh (fig. 8) teaches a nanowire transistor comprising: a gate metal (metal layer 52, [0016]); a gate oxide (high-k dielectric layer 48, [0016]-[0017]) around the gate metal (52); a monolayer ( semiconductor layers 22, 24 or 26, “the original cubic second semiconductor layers 22, 24, 26 are transformed into cylindrical nanowire channel layers” [0009] and [0015]) on the gate oxide (48); a first contact metal (contact plug 62 on the left, [0019]); a second contact metal (contact plug 62 on the right, [0019]); a first gate spacer (spacer 34 on the left, [0011]) laterally between a first portion (left portion of the dielectric layer 48) of the gate oxide (48) and the first contact metal (62); and a second gate spacer (spacer 34 on the right, [0011]) laterally between a second portion (right portion of the dielectric layer 48) of the gate oxide (48) and the second contact metal (62), wherein the second portion of the gate oxide (48) is laterally between the gate metal (52) and the second gate spacer (34).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have formed the transistor structure of LEE with spacers 34 in between gate 52 and contact plug 62 of Hsieh in order to “define a NMOS region 82 and a PMOS region 84 on the substrate 12, and then carry out the fabrication processes conducted in FIGS. 1-8 for fabricating source/drain structures 40 and/or contact plugs 62 made of graphene on the NMOS region 82 and PMOS region 84 respectively.” and “boosting the performance of the device significantly.” as taught by Hsieh, [0022] and [0024].
Regarding claim 20, Lee discloses the system of claim 18, wherein the monolayer (131, 132, 133) includes a plurality of monolayers (133a, 133b, 133c) [0130] stacked on each other.
Claims 1, 8, 9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US PGPUB 20200279918) (hereinafter Wu) in view of Hsieh US 20220238677 (hereinafter Hsieh et al.).
Regarding claim 1, Wu discloses a transistor structure (TITLE) in figure 11 comprising: a gate metal (130) [0067]; a gate oxide (126, 128) [0065] [0066] on a side of the gate metal; and a monolayer (112, 114, 116) [0027] [0035] on the gate oxide, the monolayer having a first side (top side) and a second side (bottom side) opposite the first side, wherein a first portion of an edge (left side) of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a first contact metal (134) [0072], and wherein a second portion of the edge (right side) of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a second contact metal (134) [0072].
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Marked Up Figure 11 – Clarifying Claim 1
Wu does not disclose the first gate spacer and second gate spacer.
Hsieh et al (US 2022/0238677) teaches a similar structure of Wu. Hsieh (fig. 8) teaches a nanowire transistor comprising: a gate metal (metal layer 52, [0016]); a gate oxide (high-k dielectric layer 48, [0016]-[0017]) around the gate metal (52); a monolayer ( semiconductor layers 22, 24 or 26, “the original cubic second semiconductor layers 22, 24, 26 are transformed into cylindrical nanowire channel layers” [0009] and [0015]) on the gate oxide (48); a first contact metal (contact plug 62 on the left, [0019]); a second contact metal (contact plug 62 on the right, [0019]); a first gate spacer (spacer 34 on the left, [0011]) laterally between a first portion (left portion of the dielectric layer 48) of the gate oxide (48) and the first contact metal (62); and a second gate spacer (spacer 34 on the right, [0011]) laterally between a second portion (right portion of the dielectric layer 48) of the gate oxide (48) and the second contact metal (62), wherein the second portion of the gate oxide (48) is laterally between the gate metal (52) and the second gate spacer (34).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have formed the transistor structure of Wu with spacers 34 in between gate 52 and contact plug 62 of Hsieh in order to “define a NMOS region 82 and a PMOS region 84 on the substrate 12, and then carry out the fabrication processes conducted in FIGS. 1-8 for fabricating source/drain structures 40 and/or contact plugs 62 made of graphene on the NMOS region 82 and PMOS region 84 respectively.” and “boosting the performance of the device significantly.” as taught by Hsieh, [0022] and [0024].
Regarding claim 8, Wu discloses the transistor structure of claim 1 in figure 11, wherein the gate metal (130) [0067] is a first gate metal and the monolayer (112, 114, 116) [0027] [0035] is a first monolayer (116); and further comprising: a plurality of other gate metals in a stack below the first gate metal, wherein a gate oxide layer (126, 128) [0065] [0066] is above and below each of the other gate metals; a plurality of other monolayers (112, 114), each other monolayer, respectively, above each of the plurality of the other gate metals (130) and within the gate oxide layer; and wherein a first portion of an edge of each of the other monolayers between the first side and the second side of the monolayer is coupled with the surface of the first contact metal (134) [0072], and wherein a second portion of the edge of each of the monolayers is coupled with a surface of the second contact metal (134) [0072].
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Marked Up Figure 11 – Clarification for claim 8
Regarding claim 9, Wu discloses the transistor structure of claim 8, wherein a distance between a first monolayer (116) and one of the other monolayers (114, 112) ranges from 6 nm to 10 nm [0039].
Note that the monolayers keep the same separation once the sacrificial nanosheet layers are removed in the referenced application, and thus, the thickness of the sacrificial nanosheet layers discussed in [0039] is the distance between a first monolayer and one of the other monolayers.
Regarding claim 11, Wu discloses the transistor structure of claim 8, wherein a number of the plurality of other gate metals (130) is six or more [0037].
Note that if they increase the number of channel layers as disclosed in [0037], they will increase the number of gate metals as well given the design of the referenced device explained in [0029].
Regarding claim 12, Wu discloses a method shown in figure 11 comprising: applying a first oxide layer (105) [0065] on a substrate; forming a first gate metal (130) [0067] on the oxide layer (128) [0066]; forming another oxide layer (126) [0065] on top of the first gate metal [0054]; and forming a monolayer (112) [0027] [0035] on the other oxide layer, the monolayer having a first side (top side) and a second side (bottom side) opposite the first side, wherein a first portion of an edge (left side) of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a first contact metal (134) [0072], and wherein a second portion of the edge (right side) of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a second contact metal (134) [0072].
Note that 128 is the top portion of the first oxide layer and also may be composed of an oxide [0066], which is why separate element numbers are provided.
Wu does not teach forming the first gate spacer and second gate spacer as recited.
Hsieh et al (US 2022/0238677) teaches a similar structure of Wu. Hsieh (fig. 8) teaches a nanowire transistor comprising: a gate metal (metal layer 52, [0016]); a gate oxide (high-k dielectric layer 48, [0016]-[0017]) around the gate metal (52); a monolayer ( semiconductor layers 22, 24 or 26, “the original cubic second semiconductor layers 22, 24, 26 are transformed into cylindrical nanowire channel layers” [0009] and [0015]) on the gate oxide (48); a first contact metal (contact plug 62 on the left, [0019]); a second contact metal (contact plug 62 on the right, [0019]); forming a first gate spacer (spacer 34 on the left, [0011]) laterally between a first portion (left portion of the dielectric layer 48) of the gate oxide (48) and the first contact metal (62); and forming a second gate spacer (spacer 34 on the right, [0011]) laterally between a second portion (right portion of the dielectric layer 48) of the gate oxide (48) and the second contact metal (62), wherein the second portion of the gate oxide (48) is laterally between the gate metal (52) and the second gate spacer (34).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have formed the transistor structure of Wu with spacers 34 in between gate 52 and contact plug 62 of Hsieh in order to “define a NMOS region 82 and a PMOS region 84 on the substrate 12, and then carry out the fabrication processes conducted in FIGS. 1-8 for fabricating source/drain structures 40 and/or contact plugs 62 made of graphene on the NMOS region 82 and PMOS region 84 respectively.” and “boosting the performance of the device significantly.” as taught by Hsieh, [0022] and [0024].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wu with Hsieh et al. as applied to claim 8 above, and further in view of Lee.
Regarding claim 10, Wu with Hsieh et al. discloses the transistor structure of claim 8, but does not disclose wherein each of the plurality of monolayers (112, 114, 116) further includes multiple monolayers.
However, Lee discloses a transistor structure in figure 14C wherein each channel layer (monolayer) (131, 132, 133) [0109] further includes multiple monolayers [0067].
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Wu and Hsieh et al. in light of the teachings of Lee by including multiple monolayers in each of the plurality of channel layers to help mitigate some of the defects commonly seen with monolayers.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wu with Hsieh et al. as applied to claim 12 above, and further in view of Lee.
Regarding claim 14, Wu with Hsieh et al. discloses the method of claim 12, wherein the channel length (L) is less than or equal to 15 nm [0067], but does not explicitly disclose wherein a distance along the first side of the monolayer between the surface of the first contact metal and the surface of the second contact metal is less than or equal to 15 nm.
However, Lee discloses a transistor in figure 14C wherein a distance (CL1, CL2, CL3) [0112] along the first side of the monolayer between the surface of the first contact metal (182) [0109] and the surface of the second contact metal (192) [0109] is less than or equal to 15 nm [0113].
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Wu with Hsieh et al. by replacing the source/drain regions (124) [0051] that comprise a doped semiconductor material with a metal electrode in light of the teachings of Lee to get the improved electrical conductivity, capacity, and stability that metals possess in comparison with semiconductor materials, which would result in a device wherein teachings disclose the claimed length between contact metal. If not, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to incorporate Lee’s teachings of a channel length of 3 nm or less [0113] because decreasing the channel length can decrease the size of the transistor which can in turn create improved devices [0003] [0004].
Regarding claim 15, Wu with Hsieh et al. discloses the method of claim 12, but does not disclose wherein forming a monolayer (112, 114, 116) on the oxide layer (126) further includes forming a plurality of monolayers on the oxide layer, wherein the monolayers are stacked on each other.
However, Lee discloses a method for forming a transistor in figure 14C comprising forming a monolayer (131, 132, 133) [0127-0130] [0090] on the oxide layer (142) [0110] further includes forming a plurality of monolayers on the oxide layer [0067], wherein the monolayers are stacked on each other.
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Wu with Hsieh et al. by including a stacked monolayer structure in light of the teachings of Lee because increasing the number of monolayers may reduce a short channel effect and help maintain constant junction capacitance across the monolayers [0066] as taught by Lee.
Regarding claim 16, Wu with Hsieh et al. discloses the method of claim 12, wherein the monolayer (112, 114, 116) [0027] [0035] includes “single crystal (monocrystalline) semiconductor materials” [0035], but do not specifically mention wherein the monolayer includes a selected one or more of: sulfur (S), selenium (Se), tellurium, tungsten (W), and molybdenum (Mo).
However, Lee discloses a method for forming a transistor structure wherein the monolayer (131, 132, 133) [0127-0130] [0090] includes a selected one or more of: sulfur (S), selenium (Se), tellurium (Te), tungsten (W), and molybdenum (Mo) [0018] [0019].
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Wu with Hsieh et al. by including one or more of the listed materials in the monolayer in light of the teachings of Lee because they are all common elements in semiconductor compounds and they are known to work in comparable transistors as disclosed by Lee.
Regarding claim 17, Wu with Hsieh et al. discloses the method of claim 12, but does not explicitly disclose wherein the monolayer (112, 114, 116) has a thickness of 3.3 angstroms (A) [0040].
However, Lee discloses a method for forming a transistor structure wherein the monolayer (131, 132, 133) [0127-0130] [0090] has a thickness of 1 nm or less [0113].
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Wu with Hsieh et al. by including the thickness of the monolayer as taught by Lee because thinner monolayers allow for shorter gate lengths [0068] which can decrease the size of the transistor which can in turn create improved devices [0003] [0004].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee with Hsieh et al. as applied to claim 18 above, and further in view of Wu.
Regarding claim 19, Lee with Hsieh et al. discloses the system of claim 18 in figure 14C, wherein the transistor structure (102’’) [0130] is a first transistor structure, the gate metal (162) [0109] as a first gate metal, the gate oxide (142) [0110] [0078] is a first gate oxide, and the monolayer (131, 132, 133) [0127-0130] [0090] is a first monolayer. Lee also discloses having the gate oxide include aluminum [0078].
Lee with Hsieh et al. do not disclose wherein it is further comprising: a second transistor structure on the substrate, the second transistor structure comprising: a second gate metal; a second gate oxide on a side of the second gate metal, the second gate oxide including aluminum (Al); and a second monolayer on the second gate oxide, the second monolayer having a first side and a second side opposite the first side, wherein a first portion of an edge of the second monolayer between the first side and the second side of the second monolayer is coupled with a surface of a third contact metal, and wherein a second portion of the edge of the second monolayer between the first side and the second side of the second monolayer is coupled with a surface of a fourth contact metal.
However, Wu discloses a system in figure 11 comprising: a substrate (101) [0070]; and a transistor structure (102) [0028] on the substrate, the transistor structure comprising: a gate metal (130) [0067]; a gate oxide (128) [0065] on a side of the gate metal, the gate oxide including hafnium (Hf) [0066]; and a monolayer (112, 114, 116) [0035] on the gate oxide, the monolayer having a first side and a second side opposite the first side, wherein a first portion of an edge of the monolayer between the first side and the second side of the monolayer is coupled (see “Marked Up Figure 11 – Clarifying Claim 1” for clarification regarding coupling)with a surface of a first contact metal (134) [0072], and wherein a second portion of the edge of the monolayer between the first side and the second side of the monolayer is coupled with a surface of a second contact metal (134) [0072];
wherein the transistor structure (102) [0075] is a first transistor structure, the gate metal (130) [0067] as a first gate metal, the gate oxide (128) [0065] is a first gate oxide, and the monolayer (112, 114, 116) [0035] is a first monolayer; and further comprising: a second transistor (See figure below) structure on the substrate, the second transistor structure comprising: a second gate metal (130); a second gate oxide (128) on a side of the second gate metal, the second gate oxide (128) including aluminum (Al) [0066]; and a second monolayer (112, 114, 116) on the second gate oxide (128), the second monolayer (112, 114, 116) having a first side and a second side opposite the first side, wherein a first portion of an edge of the second monolayer between the first side and the second side of the second monolayer is coupled with a surface of a third contact metal (not shown, but obviously present based on disclosure) [0023] and wherein a second portion of the edge of the second monolayer between the first side and the second side of the second monolayer is coupled with a surface of a fourth contact metal [0023].
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View of Scaled Out Picture of Wu’s Disclosure
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Lee and Hsieh et al. to include a repeating structure of transistors in light of the teachings of Wu in order to form an IC.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 and 14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892