Attorney Docket Number: 01.AD4357-US
Filing Date: 9/24/2021
Inventors et al: Ganguly
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendment filed 9/02/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed on 9/02/2025, responding to the Office action mailed on 6/04/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 7-10 and added new claims 21-34. Accordingly, pending in this application are claims 1-6 and 21-34.
Response to Argument
Applicant’s arguments and amendments to the Claims have failed to overcome the claim rejections under 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 6/04/2025. The Applicant’s response filed 9/02/2025 argues that the Chiang1 in view of Liu discloses a source with no wing or wingspan with respect to a fin portion, but this additional wing with respect to a fin portion is not mentioned in the claims. The claim limitation simply recites a limit of ratio between the lateral width of the channel semiconductor and the lateral width of the source or drain, which is taught within Liu (see, e.g., paragraph 20 of Liu). It also argues that the source has a same lateral width as the fin, but Liu explicitly states otherwise (see, e.g., paragraph 20 of Liu). Therefore, all previous claim rejections are upheld.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US 20210057525 A1) in view of Liu (US 20230088066 A1).
Regarding claim 1, Chiang (see, e.g., fig. 11) teaches most aspects of the instant invention, including an apparatus comprising:
a channel semiconductor (e.g., second semiconductor layers 105) over a substrate (e.g., substrate 101) and between a source and a drain (e.g., epitaxial source/drain regions 133) wherein the source and drain (e.g., epitaxial source/drain regions 133) are epitaxial to the channel semiconductor (e.g., second semiconductor layers 105), the channel semiconductor (e.g., second semiconductor layers 105) has a first lateral width along a lateral dimensional substantially perpendicular to an axis extending between the source and drain (e.g., epitaxial source/drain regions 133); and
A gate electrode (e.g., gate electrode 123) coupled to the channel semiconductor (e.g., second semiconductor layers 105);
Chiang, however, fails to show one of the source or drain has a portion that extends beyond the lateral width of the channel semiconductor along the lateral dimension by a second lateral width and the second lateral width is not less than .15 of the first lateral width while it also fails to show the second lateral width is not more than one-third of the first lateral width, while it also fails to teach a source contact coupled to the source and a drain contact coupled to the drain.
Liu (see fig. 2), in a similar device to Chiang, teaches one of the source or drain (e.g., source 104.1c) has a portion that extends beyond the lateral width of the channel semiconductor (e.g., channel portions 106.1c) along the lateral dimension by a second lateral width, and the second lateral width is not less than .15 of the first lateral width, and is not more than one-third of the first lateral width (see, e.g., paragraph 20 “the length of each of the sources 104.1a-e…may be 50 to 100 nm, the length of each of the channel portions 106.1a-e…may be 120 to 600nm”), and the source contact coupled to the source and a drain contact coupled to the drain (see, e.g., paragraph 42 “…a source contact and a drain contact may be coupled to the epitaxial region 143 and the epitaxial region 149, respectively).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraphs 15 and 16) to have the reduced widths of the source or drain region of Liu epitaxial to the channel regions of Chiang, for the purpose of improved switching speed and higher output current. It also would have been obvious to connect source/drain contacts to the aforementioned diffusion regions to achieve the expected result of allowing both diffusion regions of Chiang to transfer current as needed throughout the device.
Regarding claim 2, Liu teaches the second lateral width is not more than one-quarter of the first lateral width (see, e.g., paragraph 20 “the length of each of the sources 104.1a-e…may be 50 to 100 nm, the length of each of the channel portions 106.1a-e…may be 120 to 600nm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraphs 15 and 16) to even further reduce the width of the source or drain regions of Liu epitaxial to the channel regions of Chiang, for the purpose of improved switching speed and higher output current.
Claims 3-4 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Liu further in view of Peng (US 20230066230 A1) and Takeuchi (US 20200161430 A1).
Regarding claim 3, Chiang in view of Liu fails to teach the source or drain comprising a doped epitaxial nucleation layer on the channel semiconductor and a doped epitaxial bulk layer on the doped epitaxial nucleation layer, while it also fails to teach the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial layer.
Peng (see, e.g., fig. 1), in a similar device to Chiang in view of Liu, teaches a source or drain (e.g., S/D epitaxial structure 125) comprises a doped epitaxial nucleation layer on the channel semiconductor (e.g., channel regions of GAA-FETS 100 or 105) and a doped epitaxial bulk layer on the doped epitaxial nucleation layer (see, e.g., paragraph 17 “Each S/D epitaxial structure 125 may include one or more doped epitaxial layers…”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include doped epitaxial layers of Peng into the source or drain terminals of the structure of Chiang in view of Liu, for the sake of enhancing carrier mobility or improving device performance, as well as allowing multiple dopant profiles for stability of the device.
Peng, however, fails to teach the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial bulk layer.
Takeuchi (see, e.g., fig. 12), in a similar device to Chiang in view of Liu further in view of Peng, teaches the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial bulk layer (see, e.g., paragraph 90 “the upper source/drain regions 305, 307 have… higher dopant concentration… than the lower source/drain regions 304, 306… the upper source/drain regions 305, 307… may be in-situ doped epitaxial layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the source/drain of Chiang in view of Liu in further view of Peng to include the technical feature of the source/drain regions being divided into a lower region and an upper region wherein the upper region has higher dopant concentration than the lower region, for the purpose of utilizing enhanced superlattice materials within source/drain regions to reduce Schottky barrier height and thereby decrease source/drain contact resistance, as taught by Takeuchi (see paragraphs 12 and 34-35).
Furthermore, it has been held that the selection of a known material based on its suitability for its intended use is within the skill of one of ordinary skill in the art. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) See also MPEP § 2144.07.
Regarding claim 4, Peng (see, e.g., paragraph 21) teaches the doped epitaxial nucleation layer and the doped epitaxial bulk layer are doped with phosphorous and/or arsenic (see, e.g., paragraph 21 “….n-type GAA FETS include S/D epitaxial structures 125 with arsenic…phosphorous…or combinations thereof”), wherein the one of the source or drain further comprises a phosphorous doped capping layer on the doped epitaxial bulk layer (see, e.g., paragraph 17 - “Each S/D epitaxial structure 125 may include one or more doped epitaxial layers…” + paragraph 21 - “….n-type GAA FETS include S/D epitaxial structures 125 with…phosphorous…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to add another doping epitaxial layer to the source/drain structure of Chiang and Liu in order to increase the number doping profiles, increasing stability of the device. It also would have been obvious to include arsenic or phosphorous to achieve the expected result of adding impurities/dopants to the layers of the device.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Liu further in view of Xie (US 20230075966 A1)
Regarding claim 5, Chiang in view of Liu fails to teach one of the source or drain comprises a first sidewall and a second sidewall opposite the first sidewall, wherein any measurement between the first and second sidewalls along the lateral dimensional differ by not more than 8 nm.
Xie (see, e.g., fig. 4), in a similar device to Chiang in view of Liu teaches a source or drain (e.g., nanosheet source/drain regions 200) comprises a first sidewall and a second sidewall opposite the first sidewall, wherein any measurement between the first and second sidewalls along the lateral dimensional differ by not more than 8 nm (see, e.g., paragraph 58 “In various embodiments, the nanosheet source/drain regions 200 can have a width in a range of about 8 nm to about 100 nm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to scale down, or further reduce the width of the source and drain for the sake of improving switching speed and efficiency.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang(hereinafter referred to as Chiang1) in view of Liu further in view of Chiang (US 20200343377 A1)(hereinafter referred to as Chiang2).
Regarding claim 6, Chiang1 in view Liu fails to teach an aspect ratio of a height to a width of one of the source or drain is not less than 2.
Chiang2 (see, e.g., fig. 1J), in a similar device to Chiang1 in view of Liu, teaches an aspect ratio of a height to a width of one of the source or drain (e.g., source/drain features 144) is not less than 2 (see, e.g., paragraph 65 “In some embodiments, the ratio of the height H1 to the width W1 ranges from about .5 to about 10”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraph 2) to minimize the lateral dimensions of the source or drain structure of Chiang1 in view of Liu relative to its vertical height to achieve the expected result of reducing the required spacing necessary for the device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu in further view of Haran (US 20220415795 A1).
Chiang 21 in view of Liu fails to show a power supply or an integrated circuit die coupled to the power supply, the integrated circuit die comprising the aforementioned apparatus.
Haran (see, e.g., fig. 6) shows a power supply (e.g., battery 615) and an integrated circuit die (e.g., integrated system 610, see paragraph 69 “…a chip level… or package-level integrated system 610…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include a power supply and the integrated chip/die of Haran to comprise the apparatus of Chiang 1 in view of Liu, in order to achieve the expected result of physically powering the device.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu and Haran further in view of Peng and Takeuchi.
Regarding claim 22, Chiang1 (see, e.g., fig. 11) shows most aspects of the instant invention, including an apparatus comprising:
a source and a drain (e.g., epitaxial source/drain regions 133) each epitaxial to the channel semiconductor (e.g., second semiconductor layers 105), wherein the channel semiconductor (e.g., second semiconductor layers 105) has a first lateral width along a lateral dimensional substantially perpendicular to an axis extending between the source and drain (e.g., epitaxial source/drain regions 133); and
A gate electrode (e.g., gate electrode 123) coupled to the channel semiconductor (e.g., second semiconductor layers 105);
Chiang1, however, fails to show one of the source or drain has a portion that extends beyond the lateral width of the channel semiconductor along the lateral dimension by a second lateral width and the second lateral width is not less than .15 of the first lateral width while it also fails to show the second lateral width is not more than .35 of the first lateral width, while it also fails to teach a source contact coupled to the source and a drain contact coupled to the drain.
Liu (see fig. 2), in a similar device to Chiang1, teaches one of the source or drain (e.g., source 104.1c) has a portion that extends beyond the lateral width of the channel semiconductor (e.g., channel portions 106.1c) along the lateral dimension by a second lateral width, and the second lateral width is not less than .15 of the first lateral width, and is not more than .35 of the first lateral width (see, e.g., paragraph 20 “the length of each of the sources 104.1a-e…may be 50 to 100 nm, the length of each of the channel portions 106.1a-e…may be 120 to 600nm”), and the source contact coupled to the source and a drain contact coupled to the drain (see, e.g., paragraph 42 “…a source contact and a drain contact may be coupled to the epitaxial region 143 and the epitaxial region 149, respectively).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraphs 15 and 16) to have the reduced widths of the source or drain region of Liu epitaxial to the channel regions of Chiang1, for the purpose of improved switching speed and higher output current. It also would have been obvious to connect source/drain contacts to the aforementioned diffusion regions to achieve the expected result of allowing both diffusion regions of Chiang to transfer current as needed throughout the device.
Regarding claim 23, Liu teaches the second lateral width is not more than one-quarter of the first lateral width (see, e.g., paragraph 20 “the length of each of the sources 104.1a-e…may be 50 to 100 nm, the length of each of the channel portions 106.1a-e…may be 120 to 600nm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraphs 15 and 16) to even further reduce the width of the source or drain regions of Liu epitaxial to the channel regions of Chiang1, for the purpose of improved switching speed and higher output current.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu further in view of Peng (US 20230066230 A1) and Takeuchi (US 20200161430 A1).
Regarding claim 24, Chiang1 in view of Liu fails to teach the source or drain comprises a doped epitaxial nucleation layer on the channel semiconductor and a doped epitaxial bulk layer on the doped epitaxial nucleation layer, while it also fails to teach the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial layer.
Peng (see, e.g., fig. 1), in a similar device to Chiang1 in view of Liu, teaches a source or drain (e.g., S/D epitaxial structure 125) comprises a doped epitaxial nucleation layer on the channel semiconductor (e.g., channel regions of GAA-FETS 100 or 105) and a doped epitaxial bulk layer on the doped epitaxial nucleation layer (see, e.g., paragraph 17 “Each S/D epitaxial structure 125 may include one or more doped epitaxial layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include doped epitaxial layers of Peng into the source or drain terminals of the structure of Chiang1 and Liu, for the sake of enhancing carrier mobility or improving device performance, as well as allowing multiple dopant profiles for stability of the device.
Peng, however, fails to teach the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial bulk layer.
Takeuchi (see, e.g., fig. 12), in a similar device to Chiang1 in view of Liu further in view of Peng, teaches the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial bulk layer (see, e.g., paragraph 90 “the upper source/drain regions 305, 307 have… higher dopant concentration… than the lower source/drain regions 304, 306… the upper source/drain regions 305, 307… may be in-situ doped epitaxial layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the source/drain of Chiang1 in view of Liu in further view of Peng to include the technical feature of the source/drain regions being divided into a lower region and an upper region wherein the upper region has higher dopant concentration than the lower region, for the purpose of utilizing enhanced superlattice materials within source/drain regions to reduce Schottky barrier height and thereby decrease source/drain contact resistance, as taught by Takeuchi (see paragraphs 12 and 34-35).
Furthermore, it has been held that the selection of a known material based on its suitability for its intended use is within the skill of one of ordinary skill in the art. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) See also MPEP § 2144.07.
Regarding claim 25, Peng (see, e.g., paragraph 21) teaches the doped epitaxial nucleation layer and the doped epitaxial bulk layer are doped with phosphorous and/or arsenic (see, e.g., paragraph 21 “….n-type GAA FETS include S/D epitaxial structures 125 with arsenic…phosphorous…or combinations thereof”), wherein the one of the source or drain (e.g., S/D epitaxial structure 125) further comprises a phosphorous doped capping layer on the doped epitaxial bulk layer (see, e.g., paragraph 17 - “Each S/D epitaxial structure 125 may include one or more doped epitaxial layers…” + paragraph 21 - “….n-type GAA FETS include S/D epitaxial structures 125 with…phosphorous…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to add another doping epitaxial layer to the source/drain structure of Chiang1 in view of Liu in order to increase the number doping profiles, increasing stability of the device. It also would have been obvious to include arsenic or phosphorous to achieve the expected result of adding impurities/dopants to the layers of the device.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu further in view of Xie (US 20230075966 A1).
Regarding claim 26, Chiang1 in view of Liu fails to teach one of the source or drain comprises a first sidewall and a second sidewall opposite the first sidewall, wherein any measurement between the first and second sidewalls along the lateral dimensional differ by not more than 8 nm.
Xie (see, e.g., fig. 4), in a similar device to Chiang1 in view of Liu teaches a source or drain (e.g., nanosheet source/drain regions 200) comprises a first sidewall and a second sidewall opposite the first sidewall, wherein any measurement between the first and second sidewalls along the lateral dimensional differ by not more than 8 nm (see, e.g., paragraph 58 “In various embodiments, the nanosheet source/drain regions 200 can have a width in a range of about 8 nm to about 100 nm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to scale down, or further reduce the width of the source and drain of Chiang1 in view of Liu for the sake of improving switching speed and efficiency, as taught by Xie.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu further in view of Chiang2.
Regarding claim 27, Chiang1 in view Liu fails to teach an aspect ratio of a height to a width of one of the source or drain is not less than 2.
Chiang2 (see, e.g., fig. 1J), in a similar device to Chiang1 in view of Liu, teaches an aspect ratio of a height to a width of one of the source or drain (e.g., source/drain features 144) is not less than 2 (see, e.g., paragraph 65 “In some embodiments, the ratio of the height H1 to the width W1 ranges from about .5 to about 10”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraph 2) to minimize the lateral dimensions of the source or drain structure of Chiang1 in view of Liu relative to its vertical height to achieve the expected result of reducing the required spacing necessary for the device, as taught by Chiang2.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu in further view of Haran (US 20220415795 A1).
Regarding claim 28. Chiang1 in view of Liu fails to show a power supply or an integrated circuit die coupled to the power supply, the integrated circuit die comprising the channel semiconductor, the source, the drain, the gate electrode, the source contact, and the gate contact.
Haran (see, e.g., fig. 6) shows a power supply (e.g., battery 615) and an integrated circuit die (e.g., integrated system 610, see paragraph 69 “…a chip level… or package-level integrated system 610…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include a power supply and the integrated chip/die of Haran to comprise the apparatus of Chiang1 in view of Liu, in order to achieve the expected result of physically powering the device.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu and Haran further in view of Peng and Takeuchi.
Regarding claim 29, Chiang1 (see, e.g., fig. 11) shows most aspects of the instant invention, including an apparatus comprising:
a source and a drain (e.g., epitaxial source/drain regions 133) each epitaxial to the channel semiconductor (e.g., second semiconductor layers 105), wherein the channel semiconductor (e.g., second semiconductor layers 105) has a first lateral width along a lateral dimensional substantially perpendicular to an axis extending between the source and drain (e.g., epitaxial source/drain regions 133),
Chiang1, however, fails to show one of the source or drain has a portion that extends beyond the lateral width of the channel semiconductor along the lateral dimension by a second lateral width and the second lateral width is not less than .15 of the first lateral width while it also fails to show the second lateral width is not more than .25 of the first lateral width, while it also fails to teach contacts coupled to the channel semiconductor, the source, and the drain.
Liu (see fig. 2), in a similar device to Chiang1, teaches one of the source or drain (e.g., source 104.1c) has a portion that extends beyond the lateral width of the channel semiconductor (e.g., channel portions 106.1c) along the lateral dimension by a second lateral width, and the second lateral width is not less than .15 of the first lateral width, and is not more than .25 of the first lateral width (see, e.g., paragraph 20 “the length of each of the sources 104.1a-e…may be 50 to 100 nm, the length of each of the channel portions 106.1a-e…may be 120 to 600nm”), and the contacts coupled to the source and a drain (see, e.g., paragraph 42 “…a source contact and a drain contact may be coupled to the epitaxial region 143 and the epitaxial region 149, respectively) and a contact (e.g., gate conductor 152) coupled to the channel semiconductor (e.g., channel portion 106.1c).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraphs 15 and 16) to have the reduced widths of the source or drain region of Liu epitaxial to the channel regions of Chiang1, for the purpose of improved switching speed and higher output current. It also would have been obvious to provide source/drain contacts to the aforementioned diffusion regions to achieve the expected result of allowing both diffusion regions of Chiang1 to transfer current as needed throughout the device, and providing the gate conductor of Liu contacting the channel region of Chiang1 in order to achieve the expected result of controlling the flow of current within the channel region.
Claims 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu further in view of Peng (US 20230066230 A1) and Takeuchi (US 20200161430 A1).
Regarding claim 30, Chiang1 in view of Liu fails to teach the source or drain comprises a doped epitaxial nucleation layer on the channel semiconductor and a doped epitaxial bulk layer on a doped epitaxial nucleation layer, while it also fails to teach the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial layer.
Peng (see, e.g., fig. 1), in a similar device to Chiang1 in view of Liu, teaches a source or drain (e.g., S/D epitaxial structure 125) comprises a doped epitaxial nucleation layer on the channel semiconductor (e.g., channel regions of GAA-FETS 100 or 105) and a doped epitaxial bulk layer on the doped epitaxial nucleation layer (see, e.g., paragraph 17 “Each S/D epitaxial structure 125 may include one or more doped epitaxial layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include doped epitaxial layers of Peng into the source or drain terminals of the structure of Chiang and Liu, for the sake of enhancing carrier mobility or improving device performance, as well as allowing multiple dopant profiles for stability of the device.
Peng, however, fails to teach the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial bulk layer.
Takeuchi (see, e.g., fig. 12), in a similar device to Chiang1 in view of Liu further in view of Peng, teaches the doped epitaxial nucleation layer comprising a lower dopant concentration than the doped epitaxial bulk layer (see, e.g., paragraph 90 “the upper source/drain regions 305, 307 have… higher dopant concentration… than the lower source/drain regions 304, 306… the upper source/drain regions 305, 307… may be in-situ doped epitaxial layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the source/drain of Chiang1 in view of Liu in further view of Peng to include the technical feature of the source/drain regions being divided into a lower region and an upper region wherein the upper region has higher dopant concentration than the lower region, for the purpose of utilizing enhanced superlattice materials within source/drain regions to reduce Schottky barrier height and thereby decrease source/drain contact resistance, as taught by Takeuchi (see paragraphs 12 and 34-35).
Furthermore, it has been held that the selection of a known material based on its suitability for its intended use is within the skill of one of ordinary skill in the art. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) See also MPEP § 2144.07.
Regarding claim 31, Peng (see, e.g., paragraph 21) teaches the doped epitaxial nucleation layer and the doped epitaxial bulk layer are doped with phosphorous and/or arsenic (see, e.g., paragraph 21 “….n-type GAA FETS include S/D epitaxial structures 125 with arsenic…phosphorous…or combinations thereof”), wherein the one of the source or drain (e.g., S/D epitaxial structure 125) further comprises a phosphorous doped capping layer on the doped epitaxial bulk layer (see, e.g., paragraph 17 - “Each S/D epitaxial structure 125 may include one or more doped epitaxial layers…” + paragraph 21 - “….n-type GAA FETS include S/D epitaxial structures 125 with…phosphorous…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to add another doping epitaxial layer to the source/drain structure of Chiang and Liu in order to increase the number doping profiles, increasing stability of the device. It also would have been obvious to include arsenic or phosphorous to achieve the expected result of adding impurities/dopants to the layers of the device.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu further in view of Xie (US 20230075966 A1).
Regarding claim 32, Chiang1 in view of Liu fails to teach one of the source or drain comprises a first sidewall and a second sidewall opposite the first sidewall, wherein any measurement between the first and second sidewalls along the lateral dimensional differ by not more than 8 nm.
Xie (see, e.g., fig. 4), in a similar device to Chiang1 in view of Liu teaches a source or drain (e.g., nanosheet source/drain regions 200) comprises a first sidewall and a second sidewall opposite the first sidewall, wherein any measurement between the first and second sidewalls along the lateral dimensional differ by not more than 8 nm (see, e.g., paragraph 58 “In various embodiments, the nanosheet source/drain regions 200 can have a width in a range of about 8 nm to about 100 nm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to scale down, or further reduce the width of the source and drain of Chiang 1 in view of Liufor the sake of improving switching speed and efficiency, as taught by Xie.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang (hereinafter referred to as Chiang1) in view of Liu further in view of Chiang (US 20200343377 A1)(hereinafter referred to as Chiang2).
Regarding claim 33, Chiang1 in view Liu fails to teach an aspect ratio of a height to a width of one of the source or drain is not less than 2.
Chiang2 (see, e.g., fig. 1J), in a similar device to Chiang1 in view of Liu, teaches an aspect ratio of a height to a width of one of the source or drain (e.g., source/drain features 144) is not less than 2 (see, e.g., paragraph 65 “In some embodiments, the ratio of the height H1 to the width W1 ranges from about .5 to about 10”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention (see, e.g., paragraph 2) to minimize the lateral dimensions of the source or drain structure of Chiang1 in view of Liu relative to its vertical height to achieve the expected result of reducing the required spacing necessary for the device.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang1 in view of Liu in further view of Haran (US 20220415795 A1).
Regarding claim 34, Chiang1 in view of Liu fails to show a power supply or an integrated circuit die coupled to the power supply, the integrated circuit die comprising the channel semiconductor, the source, the drain, and the contacts.
Haran (see, e.g., fig. 6) shows a power supply (e.g., battery 615) and an integrated circuit die (e.g., integrated system 610, see paragraph 69 “…a chip level… or package-level integrated system 610…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include a power supply and the integrated chip/die of Haran to comprise the apparatus of Chiang1 in view of Liu, in order to achieve the expected result of physically powering the device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Thomas McCoy/
________________________
Thomas McCoy
Patent Examiner
Art Unit 2814
571-272-0282
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814