Attorney Docket Number: 01.AB9483-US
Filing Date: 9/24/2021
Inventors: Cea et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the RCE amendments filed on 01/16/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued
examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the
finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's
submission filed on 1/16/2026 has been entered.
Acknowledgments
The RCE submission filed on 1/16/2026 as an amendment in reply to the Office action mailed on
11/24/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 6 and 23 are newly canceled. New claims 28-32 are added. Accordingly, pending in this Office action are claims 1-5, 7-10, 21-22, and 24-32, with remaining claims 11-20 remaining withdrawn from consideration.
Amendment Status
Applicant’s amendments to the claims have overcome the claim rejections under 35 U.S.C. 112(b), 35 U.S.C. 102, and 35 U.S.C. 103. New grounds of rejection are presented below, however, upon further search and consideration.
Claim Objections
Claim 21 is objected to because of the following informalities: “a gate insulator”, per line 16 is a previously recited limitation. For the purposes of examination, the “gate insulator” of line 16 will be construed to recite “a second gate insulator”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miura (US 20210082766 A1).
Regarding claim 21, Miura (see, e.g., fig. 6E) shows all aspects of the instant invention including an apparatus comprising:
A single transistor structure (e.g., single crystal silicon (Si) substrate 1) comprising an upper body of channel material (e.g., upper Si layers 4) over a lower body of lower channel material (e.g., lower Si layers 4);
A gate insulator (e.g., left-side gate insulating film 21) in direct contact with a first sidewall (e.g., first sidewall, see annotated fig. 1 above) of at least the lower body channel material (e.g., lower Si layers 4)
A gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) in direct contact with the gate insulator (e.g., left-side gate insulating film 21) and adjacent to the first sidewall (e.g., first sidewall, see annotated fig. 1 above) of each of the lower body of channel materials (e.g., lower Si layers 4), wherein the gate insulator (e.g., left-side gate insulating film 21) and the gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) are also within a space between the upper (e.g., upper Si layers 4) and lower bodies of channel material (e.g., lower Si layers 4); and
a dielectric material (e.g., aggregate of FET isolation insulating films 7) in direct contact with a second sidewall (e.g., second sidewall, see annotated fig. 2 above) opposite the first sidewall (e.g., first sidewall, see annotated fig. 1 above) of at least the lower body of channel materials (e.g., lower Si layers 4), wherein the gate electrode (e.g., left-side p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) and the gate insulator (e.g., left-side gate insulating film 21) are between the dielectric material body (e.g., aggregate of FET isolation insulating films 7) and the first sidewall (e.g., first sidewall, see annotated fig. 1 above) of at least the lower body of channel material (e.g., lower Si layers 4);
a pair of second fin structures (see, e.g., annotated fig. 1) adjacent to the first fin structure (e.g., collection of previously referenced upper and lower channel material protrusions), wherein each of the second fin structures (see, e.g., annotated fig. 1) comprise another upper body of channel material (e.g., upper Si layers 4 of pair of second fin structures) over another lower body of channel material (e.g., lower Si layers 4 of pair of second fin structures);
a second gate electrode (e.g., centered gate buried film 28, between the fin structures) between the second fin structures (see, e.g., annotated fig. 1), and adjacent to a second gate insulator (e.g., gate insulating film 21 in center) that is in direct contact with an interior sidewall of each of the upper (e.g., upper Si layers 4 of pair of second fin structures) and lower material (e.g., lower Si layers 4 of pair of second fin structures) bodies of channel material of both second fin structures (see, e.g., annotated fig. 1), wherein the second gate electrode (e.g., centered p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) is between the upper (e.g., upper Si layers 4 of pair of second fin structures) and lower material (e.g., lower Si layers 4 of pair of second fin structures) bodies of channel material of both second fin structures (see, e.g., annotated fig. 1), and the dielectric material (e.g., aggregate of FET isolation insulating films 7) is adjacent to, and in contact with, an exterior sidewall of each of the upper (e.g., upper Si layers 4 of pair of second fin structures) and lower (e.g., lower Si layers 4 of pair of second fin structures) bodies of channel material of both second fin structures (see, e.g., annotated fig. 1 below);
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Annotated Fig. 1
Regarding claim 22, Miura (see, e.g., fig. 6E) shows the gate electrode (e.g., left-side p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) and the gate insulator (e.g., left-side gate insulating film 21) are between the dielectric material (e.g., aggregate of FET isolation insulating films 7) and the first sidewall (e.g., first sidewall, see annotated fig. 1 above) of the lower body of channel material (e.g., lower Si layers 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention
was made.
Claims 25-26 are rejected under 35 U.S.C. 103 being unpatentable over Miura in view of Hager (US 20220311413 A1).
Regarding claim 25, Miura (see, e.g., fig. 6E) shows the apparatus further comprises a second dielectric material (e.g., STI insulting film 2) of a second composition (e.g., paragraph 21, “A material of the STI insulating film 2 may be SiO2, or SiON, SiCO or the like derived SiO2”) in direct contact with a first sidewall (e.g., sidewall of fin in contact with STI insulating film 2) of a base (e.g., fork-extension structure from Si substrate 1) of the first fin structure and an interior sidewall of a base of each of the pair of second fin structures (see, e.g., annotated fig. 1 above), and both the gate electrode (e.g., left-side p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) and the second gate electrode (e.g., centered p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) are over the second dielectric material (e.g., STI insulting film 2) below the lower body of channel material (e.g., lower Si layers 4), the gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) is over the second dielectric material body (e.g., STI insulting film 2); and the second dielectric material body (e.g., STI insulting film 2) is between the first dielectric material body (e.g., aggregate of FET isolation insulating films 7) and the base (e.g., fork-extension structure from Si substrate 1) of the first fin structure.
Miura (see, e.g., fig. 6E), however, fails to explicitly show that the dielectric material is a first dielectric material of a first composition.
Hager (see, e.g., paragraph 31), in a similar device to Miura, teaches that the material of a dielectric layer can be formed using silicon dioxide, silicon nitride, tantalum oxide, cerium oxide, carbon-doped oxide, et cetera (see, e.g., paragraph 31 of Hager).
Accordingly, it would have been obvious at the time of the invention to one of ordinary skill in the art to use a dielectric material within Miura of a composition other than SiO2, because many are recognized in the semiconductor art for their usage in dielectric materials, as taught by Hager, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 26, Miura (see, e.g., fig. 6E) in view of Hager teaches the dielectric material (e.g., FET isolation insulating film 7) is of a first composition (e.g., modified composition of Hager, see paragraphs 9-11 above) the apparatus further comprises a second dielectric material (e.g., STI insulting film 2) of a second composition (e.g., paragraph 21, “A material of the STI insulating film 2 may be SiO2, or SiON, SiCO or the like derived SiO2”) in direct contact with a first sidewall (e.g., sidewall of fin in contact with STI insulating film 2) of a base (e.g., fork-extension structure from Si substrate 1) of the first fin structure below the lower body of channel material (e.g., lower Si layer 4), the gate electrode (e.g., left-side p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) is over the second dielectric material (e.g., STI insulting film 2) below the lower body of channel material (e.g., lower Si layers 4), and the second dielectric material (e.g., STI insulting film 2) is between the first dielectric material body (e.g., aggregate of FET isolation insulating films 7) and the base (e.g., fork-extension structure from Si substrate 1) of the first fin structure.
Claims 27-29 are rejected under 35 U.S.C. 103 being unpatentable over Miura in view of Yang (US 20220037535 A1).
Regarding claim 27, Miura (see, e.g., figs. 2D and 6E) shows a source and a drain (e.g., source/drain 13), wherein each of the source and the drain (e.g., source/drain 13) further comprises: impurity doped semiconductor material (e.g., paragraph 65 “…p-type SiGe source/drain 13… Thereafter, the source/drain (not shown) of the n-type FET is formed through a similar process to obtain a structure shown in FIG. 2D. A highly doped n-type Si is selectively grown in the source/drain region of the n-type FET. The selective growth of the p-type SiGe source/drain 13 and the n-type Si source/drain…”) coupled (see, e.g., fig. 2D) to at least one of the upper (e.g., upper Si layers 4) and lower channel bodies of channel material (e.g., lower Si layers 4).
Miura (see, e.g., figs. 2D and 6E), however, fails to show a contact metal in direct contact with a first sidewall of the impurity doped semiconductor material, wherein the dielectric material body is in direct contact with a second, opposite, sidewall of the impurity doped semiconductor material.
Yang (see, e.g., figs. 18A and 18B), in a similar device to Miura, teaches a contact metal (e.g., S/D contacts 250) in direct contact with a first sidewall (e.g., top wall of S/D features 230N and 230P) of the impurity doped semiconductor material within a source/drain (e.g., epitaxial S/D features 230N and 230P), and a dielectric material body (e.g., interlayer dielectric (ILD) layer 232) in direct contact (see, e.g., annotated fig. 3 below) with a second, opposite sidewall of the impurity doped semiconductor material (e.g., epitaxial S/D features 230N and 230P).
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Annotated Fig. 3
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact metal of Yang contacting the source and drain of Miura, in order to enable mobility of charge carriers to the source and from the drain, in order to enable transistor operation. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material of Yang connected to the dielectric material body of Miura, connected to the opposite/bottom sidewall of the source/drain, in order to provide additional prevention in allowing the impurities or current within the source/drain to diffuse to local semiconductor layers within the device.
Regarding claim 28, Miura (see, e.g., figs. 2D and 6E) shows the source and the drain (e.g., source/drain 13), is a first source and a first drain (e.g., source/drain 13) comprising a first impurity doped semiconductor material (e.g., paragraph 65 “…p-type SiGe source/drain 13… Thereafter, the source/drain (not shown) of the n-type FET is formed through a similar process to obtain a structure shown in FIG. 2D. A highly doped n-type Si is selectively grown in the source/drain region of the n-type FET. The selective growth of the p-type SiGe source/drain 13 and the n-type Si source/drain…”) of a first conductivity type coupled (see, e.g., fig. 2D) to the lower body of channel material (e.g., lower Si layers 4).
Miura (see, e.g., figs. 2D and 6E), however, fails to show a contact metal is in direct contact with a first sidewall of the first impurity doped semiconductor material.
Yang (see, e.g., figs. 18A and 18B) teaches a contact metal (e.g., S/D contacts 250) is in direct contact with a first sidewall (e.g., top wall of S/D features 230N) first impurity doped semiconductor material (e.g., epitaxial S/D features 230N).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact metal of Yang contacting the source and drain of Miura, in order to enable mobility of charge carriers to the source and from the drain, in order to enable transistor operation. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material of Yang connected to the dielectric material body of Miura, connected to the opposite/bottom sidewall of the source/drain, in order to provide additional prevention in allowing the impurities or current within the source/drain to diffuse to local semiconductor layers within the device.
Regarding claim 29, Yang teaches a second source and a second drain (e.g., epitaxial S/D features 230P) wherein each of the second source and the second drain further comprises (e.g., epitaxial S/D features 230P) a second impurity doped semiconductor material (e.g., impurity of epitaxial S/D features 230P, see, e.g., paragraph 28) coupled to an upper body of channel materials (see, e.g., figs. 18 of Yang), and a contact metal (e.g., S/D contact 250) in direct contact with a first sidewall of the second impurity doped semiconductor material (e.g., impurity of epitaxial S/D features 230P, see, e.g., paragraph 28).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second source and drain of Yang within the device of Miura in view of Yang, in order to achieve the expected result of increasing transistor density within the device. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact metal configuration of Yang within the device of Miura in view of Yang, in order to achieve the expected result of enabling mobility of charge carries to and from the source and drain throughout other regions of the device.
Claims 30-31 are rejected under 35 U.S.C. 103 being unpatentable over Miura in view of Hager further in view of Yu (US 20200212037 A1).
Regarding claim 30, Miura (see, e.g., fig. 6E) shows most aspects of the instant invention including an integrated circuit structure comprising:
A fin structure comprising an upper channel material (e.g., upper Si layers 4) over a lower channel material (e.g., lower Si layers 4) and a base (e.g., protruding portion of Si substrate 1) below the lower channel material (e.g., lower Si layers 4);
A gate insulator (e.g., gate insulating film 21) in direct contact with a first sidewall (e.g., first sidewall, see annotated fig. 1 above) of the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4);
A gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) in contact with the gate insulator (e.g., gate insulating film 21) and adjacent to the first sidewall (e.g., sidewalls of Si layers 4) of each of the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4), wherein the gate insulator (e.g., gate insulating film 21) and the gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) are also within a space between the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4);
A first dielectric material (e.g., FET isolation insulating film 7) adjacent to the first sidewall and adjacent to a second, opposite, sidewall of each of the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4), wherein:
the first dielectric material (e.g., FET isolation insulating film 7) is in direct contact with the second, opposite, sidewall (e.g., second sidewall, see annotated fig. 2 below) of each of the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4); and
the gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) and the gate insulator (e.g., gate insulating film 21) are between the first dielectric material (e.g., aggregate of FET isolation insulating films 7) and the first sidewall (e.g., first sidewall, see annotated fig. 1 above) of each of the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4);
a second dielectric material (e.g., STI insulating film 2) of a second composition (see, e.g., paragraph 60 “A material of the STI insulating film 2 may be SiO.sub.2, or SiON…”) in direct contact with a first sidewall of the base (e.g., protruding portion of Si substrate 1), wherein:
the second dielectric material (e.g., STI insulating film 2) is below the gate electrode (e.g., p-work function control metal film 22 + n-work function control metal film 27 + gate buried metal film 28) and has a lateral thickness, normal from the first sidewall of the base (e.g., protruding portion of Si substrate 1), and the first dielectric material (e.g., FET isolation insulating film 7) is separated from the first sidewall of the upper (e.g., upper Si layers 4) and lower channel materials (e.g., lower Si layers 4).
Miura (see, e.g., fig. 6E), however, fails to show that the first dielectric material is a first dielectric material of a first composition, while it also fails to teach the first dielectric material is separated from the first sidewall of the upper and lower channel materials by no more than the lateral thickness.
Hager (see, e.g., paragraph 31), in a similar device to Miura, teaches that the material of a dielectric layer can be formed using silicon dioxide, silicon nitride, tantalum oxide, cerium oxide, carbon-doped oxide, et cetera (see, e.g., paragraph 31 of Hager).
Accordingly, it would have been obvious at the time of the invention to one of ordinary skill in the art to use a dielectric material body within Miura of a composition other than SiO2, because many are recognized in the semiconductor art for their usage in dielectric materials, as taught by Hager, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Miura in view of Hager, however, fails to teach the first dielectric material is separated from the first sidewall of the upper and lower channel materials by no more than the lateral thickness.
Yu (see, e.g., fig. 8), in a similar device to Miura in view of Hager, teaches a lateral thickness of an isolation structure (e.g., isolation structure 20) is 20 nm to 50 nm (see, e.g., paragraph 38 “The isolation structure 20 may have a thickness from 20 nm to 50 nm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness configuration of Yu within the STI film of Miura in view of Hager, in order to achieve the expected result of providing a distinct isolation profile while simultaneously limiting the cost of manufacturing during fabrication of the device. In addition, note that the thickness of the channel materials is 5 to 10 nm (see paragraph 59 of Miura), hence the modification would result in the separation between the first dielectric material and the first sidewall of the upper and lower channel materials by less than the lateral thickness of the STI thickness.
Regarding claim 31, Miura (see, e.g., fig. 6E) shows wherein the second dielectric material (e.g., STI insulating film 2) is between the first dielectric material (e.g., FET isolation insulating film 7) and the first sidewall of the base (e.g., protruding portion of Si substrate 1).
Allowable Subject Matter
Claims 1-5, 7-10, and 32 are allowed.
Claim 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, Miura (US 20210082766 A1) in view of Hager (US 20220311413 A1) teaches most aspects of the integrated circuit (IC) structure.
However, Miura in view of Hager fails to teach the second dielectric material is in direct contact with a second, opposite sidewall of the base along a second majority of the height.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
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/THOMAS WILSON MCCOY/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814