Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is a final office action in response to the communication filed 8/13/2025.
Claims 1-20 are currently pending.
Claims 1, 6, 11, and 16 have been amended.
Claims 5, 8, and 10 have been withdrawn.
Claims 1-4, 6-7, 9, and 11-20 have been examined.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 6, 11, and 16 regarding the addition of "a first power rail coupled to the first device" and "a second power rail coupled to a second device" have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Particularly, in regards to new reference Smith et al, US 20190288004 A1. See below for further detail.
Applicant did not appear to provide a response to the Specification objection in the Non-Final response 4/17/2025. Examiner maintains the specification objection as restated below.
Specification
The disclosure is objected to because of the following informalities: both reference item 122 and 142 if Fig. 1 are labeled as the lower power rail in the specification at paragraphs [0023] .
Appropriate correction is required.
Drawings
While not being raised a drawing objection at this time, Applicant is advised that currently withdrawn claims 5 and 8 include features in the claims that are not shown in the drawings. Specifically, “wherein the first device is electrically isolated from the second device” or “wherein the NMOS device is electrically isolated from the PMOS device.” Under 37 CFR 1.83(a), the drawings must show every feature of the invention specified in the claims. Applicant might consider including drawings which show such feature(s) or canceling the claim(s). No new matter should be entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak, et al. US 20190393214 A1 (hereinafter Lilak) and in view of Lee et al., US 20210226010 A1 (hereinafter Lee) and Smith et al, US 20190288004 A1 (hereinafter Smith).
Regarding claim 1, Lilak discloses:
An integrated circuit structure (Lilak, Abstract, an integrated circuit), comprising:
a first device (Lilak, Fig. 3, lower device layer 320) comprising a first two-dimensional (2D) material layer (nanoribbons 311, Examiner understand nanoribbons to be a 2D structure wherein the width is less than or about equal to 50nm), and a first gate stack around the first 2D material layer (gate structure 313 and gate dielectric layer 35), the first gate stack having a gate electrode (gate structure 313) around a gate dielectric layer (gate dielectric 315); and
a second device stacked on the first device (Fig. 3, upper device layer 340), the second device comprising a second 2D material layer (nanowires 331), and a second gate stack around the second 2D material layer (gate structure 333 and gate dielectric 335), the second gate stack having a gate electrode (gate structure 333) around a gate dielectric layer (gate dielectric 335),
Lilak appears to be silent on “wherein the second 2D material layer has a composition different than a composition of the first 2D material layer” or “a first power rail coupled to the first device and a second power rail coupled to the second device”.
However, Lee, which teaches a transistor including at least one two-dimensional (2D) channel is disclosed (Lee, Abstract), further discloses:
wherein the second 2D material layer has a composition different than a composition of the first 2D material layer. (Lee, Fig. 1, 2D channel layer 1L1, [0040], The channel layer may be of a second 2D material and the concentration of doping material in the channel may be different from the first 2D material in order to selectively have a P-type or N-type device.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak to have the second 2D material layer has a composition different than a composition of the first 2D material layer as modified by Lee for purposes of having the channel layer include a transition metal dichalcogenide 2D material layer of different doping concentrations. (Lee, [0040]).
Lee does teach that “the electron device 1100 may include … a power supply” (Lee, Fig. 11, [0088].) However does not specifically denote that there is “a first power rail coupled to the first device and a second power rail coupled to the second device”.
Smith, which teaches “complementary field-effect transistor (CFET) device in which some or all of the NMOS or PMOS source and drain electrodes/contacts are vertically stacked over one another in the CFET design” (Smith, [0007]), further discloses:
a first power rail (Smith, Fig. 2A, power rail 114b) coupled to the first device (top S/D contact 108a); and
a second power rail (power rail 114c) coupled to the second device. (bottom S/D contact 106b)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak and Lee to have a first power rail coupled to the first device and a second power rail coupled to the second device as modified by Smith for purposes of providing area scaling benefits through track-height reduction scaling. (Smith, [0060].)
Regarding claim 2, Lilak, Lee, and Smith teach the elements of claim 1 as recited above.
Lilak further teaches an NMOS or PMOS device based on the work function of the gate metal. Lilak, [00032]. Lee further teaches the channel layer may be of a second 2D material and the concentration of doping material in the channel may be different from the first 2D material in order to selectively have a P-type or N-type device. Lee, [0040]. Smith teaches specifically teaches that in one embodiment the top FET can be NMOS and the bottom FET can be PMOS and in a separate embodiment the top FET can be PMOS and the bottom FET can be NMOS. Smith, [0056]. Therefore, Lilak, Lee, and Smith teach different ways of creating a PMOS or NMOS device. Also, as the Applicant’s specification does not show that the order of NMOS or PMOS devices to be a critical feature, it would have been obvious to one of ordinary skill in the art at the claims were effectively filed to choose a specific order of PMOS/NMOS structure based on the needed functional requirements of the overall transistor structure and the limited choices. Therefore, Lilak, Lee, and Smith implicitly or explicitly teach a first device being an NMOS device, and the second device is a PMOS device. See also, Lilak [0041], Lee [0010], and Smith [0048].
Regarding claim 3, Lilak, Lee, and Smith teach the elements of claim 1 as recited above.
Lilak further teaches an NMOS or PMOS device based on the work function of the gate metal. Lilak, [00032]. Lee further teaches the channel layer may be of a second 2D material and the concentration of doping material in the channel may be different from the first 2D material in order to selectively have a P-type or N-type device. Lee, [0040]. Smith teaches specifically teaches that in one embodiment the top FET can be NMOS and the bottom FET can be PMOS and in a separate embodiment the top FET can be PMOS and the bottom FET can be NMOS. Smith, [0056]. Therefore, Lilak, Lee, and Smith teach different ways of creating a PMOS or NMOS device. Also, as the Applicant’s specification does not show that the order of NMOS or PMOS devices to be a critical feature, it would have been obvious to one of ordinary skill in the art at the claims were effectively filed to choose a specific order of PMOS/NMOS structure based on the needed functional requirements of the overall transistor structure and the limited choices. Therefore, Lilak, Lee, and Smith implicitly or explicitly teach a first device being an PMOS device, and the second device is a NMOS device. See also, Lilak [0041], Lee [0010], and Smith [0048].
Regarding claim 4, Lilak, Lee, and Smith teach the elements of claim 1 as recited above.
Lilak further teaches:
wherein the first device is electrically coupled to the second device. (Lilak, Fig. 3, via 357, [0057], "via 357, through the insulator layer 355 couples together the transistor 310 and transistor 330”.)
Regarding claim 11, Lilak discloses:
A computing device (Lilak, Fig. 9 computing device 900, which can be used with Figs 8 and 3 regarding the embodiment. [0079]), comprising:
a board (Lilak, Fig. 8, second substrate 804, the second substrate can be a motherboard. The device described in Fig. 8 can be used with the transistor structure described in Fig. 3 [0075].); and
a first device (Lilak, Fig. 3, lower device layer 320) comprising a first two-dimensional (2D) material layer (nanoribbons 311), and a first gate stack around the first 2D material layer (gate structure 313 and gate dielectric layer 35), the first gate stack having a gate electrode (gate structure 313) around a gate dielectric layer (gate dielectric 315); and
a second device stacked on the first device (Fig. 3, upper device layer 340), the second device comprising a second 2D material layer (nanowires 331), and a second gate stack around the second 2D material layer (gate structure 333 and gate dielectric 335), the second gate stack having a gate electrode (gate structure 333) around a gate dielectric layer (gate dielectric 335).
Lilak appears to be silent on “wherein the second 2D material layer has a composition different than a composition of the first 2D material layer” or “a first power rail coupled to the first device and a second power rail coupled to the second device”.
However, Lee, which teaches a transistor including at least one two-dimensional (2D) channel is disclosed (Lee, Abstract), discloses:
wherein the second 2D material layer has a composition different than a composition of the first 2D material layer. (Lee, [0040], The channel layer may be of a second 2D material and the concentration of doping material in the channel may be different from the first 2D material in order to selectively have a P-type or N-type device.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak to have the second 2D material layer has a composition different than a composition of the first 2D material layer as modified by Lee for purposes of having the channel layer include a transition metal dichalcogenide 2D material layer of different doping concentrations. (Lee, [0040]).
Lee does teach that “the electron device 1100 may include … a power supply” (Lee, Fig. 11, [0088].) However does not specifically denote that there is “a first power rail coupled to the first device and a second power rail coupled to the second device”.
Smith, which teaches “complementary field-effect transistor (CFET) device in which some or all of the NMOS or PMOS source and drain electrodes/contacts are vertically stacked over one another in the CFET design” (Smith, [0007]), further discloses:
a first power rail (Smith, Fig. 2A, power rail 114b) coupled to the first device (S/D contact 108a); and a second power rail (power rail 114c) coupled to the second device. (S/D contact 106b)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak and Lee to have a first power rail coupled to the first device and a second power rail coupled to the second device as modified by Smith for purposes of providing area scaling benefits through track-height reduction scaling. (Smith, [0060].)
Regarding claim 12, Lilak, Lee, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
a memory coupled to the board (Lilak, Fig. 9, volatile memory 912, [0081] coupled to the motherboard.)
Regarding claim 13, Lilak, Lee, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
a communication chip coupled to the board. (Lilak, Fig.9, communication chip 908, [0079], couple to the motherboard)
Regarding claim 14, Lilak, Lee, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
a camera coupled to the board. (Lilak, Fig. 9, camera 935, [0081], coupled to the motherboard)
Regarding claim 15, Lilak, Lee, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
wherein the component is a packaged integrated circuit die. (Lilak, [0017], the present devices may be presented in an IC (integrated circuit))
Claims 6, 7, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak in further view of Huang et al., US 20210018780 A1 (hereinafter Huang) and Smith.
Regarding claim 6, Lilak discloses:
An integrated circuit structure (Lilak, Abstract, an integrated circuit), comprising:
an NMOS device comprising: (Lilak, [00032], teaches an NMOS or PMOS device based on the work function of the gate metal.)
a first plurality of vertically stacked two-dimensional (2D) material layers (Lilak lower device layer 320 with a plurality of nanoribbons 311), each of the first plurality of vertically stacked 2D material layers comprising molybdenum and sulfur (Lilak, [0046], non-planar structure material can include molybdenum disulphide); and
a first gate stack around the first plurality of vertically stacked 2D material layers (Lilak, Fig. 3, gate structure 313 and gate dielectric layer 35), the first gate stack having a gate electrode (Lilak, Fig.3, gate structure 313) around a gate dielectric layer (Lilak, Fig. 3, gate dielectric 315); and
a PMOS device stacked on the NMOS device, the PMOS device comprising: (Lilak, [00032], teaches an NMOS or PMOS device.
Lilak further teaches an NMOS or PMOS device based on the work function of the gate metal. Lilak, [00032]. Also, as the Applicant’s specification does not show that the order of NMOS or PMOS devices to be a critical feature, it would have been obvious to one of ordinary skill in the art at the claims were effectively filed to choose a specific order of PMOS/NMOS structure based on the needed functional requirements of the overall transistor structure and the limited choices. Therefore, Lilak implicitly teaches a first device being an PMOS device, and the second device is a NMOS device. See also, Lilak [0041].)
a second plurality of vertically stacked 2D material layers (Lilak, Fig. 3, upper device layer 340 with a plurality of nanowires 331), …
a second gate stack around the second plurality of vertically stacked 2D material layers (Lilak, Fig, 3, gate structure 333 and gate dielectric 335), the second gate stack having a gate electrode (Lilak, Fig.3, gate structure 333) around a gate dielectric layer. (Lilak, gate dielectric 335)
Lilak appears to be silent on “each of the second plurality of vertically stacked 2D material layers comprising tungsten and selenium” and “a first power rail coupled to the NMOS device; and a second power rail coupled to the PMOS device.”
However, Huang, which teaches using transitional metal dichalcogenides (TMDs) for 2D active layers which can be high speed charge transport and low-power consumption (Huang, [0004] – [0005]), discloses:
each of the second plurality of vertically stacked 2D material layers comprising tungsten and selenium. (Huang, WSe2 is a TMD material that can be used for the active layer in a TFT)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak to have a second plurality of vertically stacked 2D material layers comprising tungsten and selenium as modified by Huang for purposes of providing a 2D active layer which is suitable for high-performance FETs. (Huang [0004].)
Lilak and Huang do not appear to disclose “a first power rail coupled to the NMOS device; and a second power rail coupled to the PMOS device.”
Smith, which teaches “complementary field-effect transistor (CFET) device in which some or all of the NMOS or PMOS source and drain electrodes/contacts are vertically stacked over one another in the CFET design” (Smith, [0007]), further discloses:
a first power rail (Smith, Fig. 2A, power rail 114b) coupled to the NMOS device (top S/D contact 108a and [0056] “the top sources/drains can be NMOS sources/drains based on circuit design”); and
a second power rail (power rail 114c) coupled to the PMOS device. (bottom S/D contact 108a and [0056] “the bottom sources/drains can be PMOS sources/drain”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak and Lee to have a first power rail coupled to the NMOS device, and a second power rail coupled to the PMOS device as modified by Smith for purposes of providing area scaling benefits through track-height reduction scaling. (Smith, [0060].)
Regarding claim 7, Lilak, Huang, and Smith teach the elements of claim 1 as recited above.
Lilak further teaches:
wherein the first device is electrically coupled to the second device. (Lilak, Fig. 3, via 357, [0057], "via 357, through the insulator layer 355 couples together the transistor 310 and transistor 330”.)
Regarding claim 16, Lilak discloses:
A computing device (Lilak, Fig. 9, computing device 900), comprising:
a board (Lilak, Fig. 8, second substrate 804, the second substrate can be a motherboard. The device described in Fig. 8 can be used with the transistor structure described in Fig. 3); and
a component (Lilak, Fig. 3, IC 300) coupled to the board (Lilak, Fig.8, second substrate 804 couple to first substrate 802 where the first substrate supports the IC of Fig. 3), the component including an integrated circuit structure, comprising:
an NMOS device comprising:(Lilak, [00032], teaches an NMOS or PMOS device based on the work function of the gate metal.)
a first plurality of vertically stacked two-dimensional (2D) material layers (Lilak lower device layer 320 with a plurality of nanoribbons 311), each of the first plurality of vertically stacked 2D material layers comprising molybdenum and sulfur (Lilak, [0046], non-planar structure material can include molybdenum disulphide); and
a first gate stack around the first plurality of vertically stacked 2D material layers (Lilak, Fig. 3, gate structure 313 and gate dielectric layer 35), the first gate stack having a gate electrode (Lilak, Fig.3 gate structure 313) around a gate dielectric layer (Lilak, Fig. 3, gate dielectric 315); and
a PMOS device stacked on the NMOS device, the PMOS device comprising: (Lilak, [00032], teaches an NMOS or PMOS device.
Lilak further teaches an NMOS or PMOS device based on the work function of the gate metal. Lilak, [00032]. As the Applicant’s specification does not show that the order of NMOS or PMOS devices to be a critical feature, it would have been obvious to one of ordinary skill in the art at the claims were effectively filed to choose a specific order of PMOS/NMOS structure based on the needed functional requirements of the overall transistor structure and the limited choices. Therefore, Lilak implicitly teaches a first device being an PMOS device, and the second device is a NMOS device. See also, Lilak [0041].
a second plurality of vertically stacked 2D material layers (Lilak, Fig. 3, upper device layer 340 with a plurality of nanowires 331), …
a second gate stack around the second plurality of vertically stacked 2D material layers (Lilak, Fig, 3, gate structure 333 and gate dielectric 335), the second gate stack having a gate electrode (Lilak, Fig.3, gate structure 333) around a gate dielectric layer. (Lilak, gate dielectric 335)
Lilak appears to be silent on “each of the second plurality of vertically stacked 2D material layers comprising tungsten and selenium” and “a first power rail coupled to the NMOS device; and a second power rail coupled to the PMOS device.”
However, Huang, which teaches using transitional metal dichalcogenides (TMDs) for 2D active layers which can be high speed charge transport and low-power consumption (Huang, [0004] – [0005]), discloses:
each of the second plurality of vertically stacked 2D material layers comprising tungsten and selenium (Huang, WS2 is a TMD material that can be used for the active layer in a TFT);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak to have a second plurality of vertically stacked 2D material layers comprising tungsten and selenium as modified by Huang for purposes of providing a 2D active layer which is suitable for high-performance FETs. [Huang 0004].
Lilak and Huang do not appear to disclose “a first power rail coupled to the NMOS device; and a second power rail coupled to the PMOS device.”
Smith, which teaches “complementary field-effect transistor (CFET) device in which some or all of the NMOS or PMOS source and drain electrodes/contacts are vertically stacked over one another in the CFET design” (Smith, [0007]), further discloses:
a first power rail (Smith, Fig. 2A, power rail 114b) coupled to the NMOS device (top S/D contact 108a and [0056] “the top sources/drains can be NMOS sources/drains based on circuit design”); and
a second power rail (power rail 114c) coupled to the PMOS device. (bottom S/D contact 108a and [0056] “the bottom sources/drains can be PMOS sources/drain”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak and Lee to have a first power rail coupled to the NMOS device, and a second power rail coupled to the PMOS device as modified by Smith for purposes of providing area scaling benefits through track-height reduction scaling. (Smith, [0060].)
Regarding claim 17, Lilak, Huang, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
a memory coupled to the board (Lilak, Fig. 9, volatile memory 912, [0081] coupled to the motherboard.)
Regarding claim 18, Lilak, Huang, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
a communication chip coupled to the board. (Lilak, Fig.9, communication chip 908, [0079], couple to the motherboard)
Regarding claim 19, Lilak, Huang, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
a camera coupled to the board. (Lilak, Fig. 9, camera 935, [0081], coupled to the motherboard)
Regarding claim 20, Lilak, Huang, and Smith teach the elements of claim 11 as recited above.
Lilak further discloses:
wherein the component is a packaged integrated circuit die. (Lilak, [0017], the present devices may be presented in an IC (integrated circuit))
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak, Huang and Smith as applied to claim 6 above, and further in view of Xie et al. US 20210265348 A1.
The following annotated figure 9 of Xie is used in discussion of claim 9:
PNG
media_image1.png
513
700
media_image1.png
Greyscale
Regarding claim 9, Lilak, Huang, and Smith teach the elements of claim 6 as recited above.
Lilak, Huang, and Smith appear to be silent regarding "wherein the first plurality of vertically stacked 2D material layers is a first plurality of vertically stacked nanosheets, and the second plurality of vertically stacked 2D material layers is a second plurality of vertically stacked nanosheets."
Xie, which teaches a device and method of forming a CFET structure witch channel regions formed of nanosheets (Xie, Abstract), discloses:
wherein the first plurality of vertically stacked 2D material layers is a first plurality of vertically stacked nanosheets (Xie, Fig. 9, device 1, having semiconductor layers 108 wherein semiconductor layer s 108 are nanosheets [0034]. Examiner understands nanosheets to be a 2D structure with a width range of 1-10nm.), and the second plurality of vertically stacked 2D material layers is a second plurality of vertically stacked nanosheets. (Xie, Fig. 9, device 2 having semiconductor layers 108) wherein semiconductor layer s 108 are nanosheets [0034])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lilak, Huang, and Smith to have the first plurality of vertically stacked 2D material layers is a first plurality of vertically stacked nanosheets, and the second plurality of vertically stacked 2D material layers is a second plurality of vertically stacked nanosheets as modified by Xie for purposes of defining p-type and n-type portions of the CFET stack. (Xie, [0034])
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al, US 20200027921 A1 – 2D nanosheet material including MoS2 and TSe2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812