Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-20 are pending.
-Claims 1, 14, and 19 are amended.
-Claims 14-18 are withdrawn.
Response to Arguments
Applicant’s amendments and arguments filed April 3, 2026 have been fully considered and are persuasive as they relate to the rejection of Claim 1 presented in the Non-Final Office Action dated January 8, 2026. However, Examiner notes that in regards to Claim 19, Trivedi et al. (U.S. Pub. 2021/0184001) already discloses the amended limitations (See (115A) and (115B) in Figs. 1B and 1C, respectively; Paragraphs [0023] and [0024]). The rejections have been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, the limitation “the gate structure comprises a gate dielectric and a conductor” is unclear whether the “gate dielectric” is referring to a new dielectric or the same one already claimed. Based on Applicants Specification, e.g. Paragraph [0021]- wherein only one gate dielectric is disclosed, it is the Examiner’s understanding that this is the same dielectric previously established in Claim 1.
For the purposes of this Office Action, Claim 2 will be read as follows:
-- The semiconductor device of claim 1, wherein the gate structure comprises the gate dielectric and a conductor.--
Regarding Claim 3, the claim is rejected due to its dependency on Claim 2.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 3 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 3, the limitation “the conductor comprises a first metal layer that is conformal, and a second metal layer that is a fill material” has no support from the Specification, neither in descriptions of the completed device. With the introduction of “a gate metal” into Claim 1 and already having a “conductor” in Claim 2, the two components disclosed to make up the gate metal in the spec (a workfunction metal and a fill metal, see Paragraph [0022])) are already claimed, and there is no reference to a third metal or conductor within the gate structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (U.S. Pub. 2020/0235098), hereinafter Li, in view of Gaul et al. (U.S. Pub. 2023/0093343), hereinafter Gaul, and in view of Dewey et al. (U.S. Pub. 2020/0105751), hereinafter Dewey.
Regarding Claim 1, Li teaches a semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]), comprising:
-a sheet (‘2D SLAB’ (210N), e.g. (210N(2)); Fig. 2A, Paragraph [0041]) comprising a semiconductor (‘semiconductor channel structures’; Paragraph [0041]), wherein a length dimension (Y-axis direction of Fig. 2A) of the sheet (210N(2)) and a width dimension (X-axis direction of Fig. 2A, e.g. A2L(2)) of the sheet (210N(2)) are greater than a thickness dimension (Z-axis direction of Fig. 2A) of the sheet (210N(2)) (See Paragraph [0041]),
-the sheet (210N(2)) having a first sidewall (the negative X, i.e. the left, side of 210N(2) as in Fig. 2A) laterally opposite to a second sidewall (e.g. the positive X, i.e. the right, side of 210N(2) as in Fig. 2A);
-a gate structure (lower gate (222L) consisting of gate dielectric (226L) and gate conducting portions (225L); Fig. 2A, Paragraph [0044]) around the sheet (210N(2)), the gate structure having a gate dielectric (226L) and a gate metal (225L);
-a first spacer (spacer (224LS) on the left; Fig. 2A, Paragraph [0044]) adjacent to a first end (e.g. on the left side) of the gate structure ((222L));
-a second spacer (spacer (224LD) on the right; Fig. 2A, Paragraph [0044]) adjacent to a second end (e.g. on the right side) of the gate structure ((226L) and (225L));
-a source contact (‘source/drain region’ (214LS); Fig. 2A, Paragraph [0043]) wrapping around the sheet (210N(2)) and adjacent to the first spacer ((224LS) on the left),
-the source contact (214LS) in contact with an entirety of the first sidewall of the sheet (left side of (210N(2))); and
-a drain contact (‘source/drain region’ (214LD); Fig. 2A, Paragraph [0043]) wrapping around the sheet (210N(2)) and adjacent to the second spacer ((224LD) on the right),
-the drain contact (214LD) in contact with an entirety of the second sidewall of the sheet (right side of (210N(2)).
Li does not explicitly disclose:
-the source contact comprising a metal
-the drain contact comprising a metal
Gaul teaches (e.g. in Fig. 11) gate-all-around transistors using 2D materials for channel regions wherein:
-the source contact (consisting of a first material layer (230) and a material fill (240), e.g. on the left of a stack; Fig. 11, Paragraph [0082]) comprises a metal (‘(240) can be a conductive material including, but not limited to, a metal’, Paragraph [0083])
-the drain contact (consisting of a first material layer (230) and a material fill (240), e.g. on the right of a stack; Fig. 11, Paragraph [0082]) comprises a metal (‘(240) can be a conductive material including, but not limited to, a metal’, Paragraph [0083])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gaul into the device of Li such that the source contact comprises a metal and the drain contact comprises a metal. Futhermore, the incorporation would be done such that the source contact and the drain contact comprise a first metal layer that is conformal around the sheet (Gaul, (230) can be formed by a conformal deposition, can be a conductive material…, for example antimony (Sb); Fig. 11, Paragraphs [0078] and [0079])); and a second metal layer this a fill material (Gaul, ‘source/drain material fill’ (240); Fig. 11, Paragraphs [0082] and [0032]). This would be due to the fact that incorporating this source/drain structure would reduce contact resistance with the sheet (Gaul, Paragraphs [0026] and [0079]).
Neither Li nor Gaul explicitly disclose:
-wherein the gate dielectric laterally separates the gate metal from the first spacer
-wherein the gate dielectric laterally separates the gate metal from the second spacer
Dewey teaches a gate-all-around transistor semiconductor device ((‘Lower Device’ (209); Fig. 2a, Paragraph [0027]) comprising a gate structure comprising a gate dielectric (e.g. second from bottom (206); Fig. 2a, Paragraph [0027]) and a gate metal (e.g. second from bottom (203); Fig. 2a, Paragraph [0027]), wherein:
-wherein the gate dielectric (second from bottom (206)) laterally separates the gate metal (second from bottom (203)) from the first spacer (e.g. second from bottom spacer (212) on the left; Fig. 2a, Paragraph [0027])
-wherein the gate dielectric (second from bottom (206)) laterally separates the gate metal (second from bottom (203)) from the second spacer (e.g. second from bottom spacer (212) on the right)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Dewey into the device of Li as modified by Gaul such that the gate dielectric laterally separates the gate metal from the first spacer and the gate dielectric laterally separates the gate metal from the second spacer. This would be due to the fact that doing so would produce the predictable result of incorporating a High-K gate dielectric layer to ensure efficient gating when devices are used (Dewey, Paragraphs [0030] and [0031]).
Regarding Claim 2, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 1, wherein:
-the gate structure comprises the gate dielectric (226L)
-the gate metal (Li, (225L)) comprises a fill material (Li, ‘gate portions form of a conductive gate material (e.g., metal)’; Paragraph [0061]. And, Gaul, ‘conductive gate fill’ (280); Fig. 16, Paragraph [0099])
Li, Gaul, and the initial modification by Dewey do not explicitly disclose:
-the gate structure comprises a conductor.
Dewey further teaches a gate-all-around transistor semiconductor device ((‘Lower Device’ (209); Fig. 2a, Paragraph [0027]) comprising a gate structure comprising a gate dielectric (206) and a conductor (203), wherein:
-the gate structure (as part of (203) comprises a gate metal (‘central metal plug portion’; Paragraph [0031]) and a conductor having a first metal layer that is conformal (‘barrier layers (e.g. platinum) and second metal layer that is a fill material (a work function layer, e.g. an aluminum-containing alloy; Paragraph [0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Dewey into the device of Li as modified by Gaul and initially by Dewey such that the gate structure further comprises a conductor. Furthermore, this would be done such that the conductor comprises a first metal layer that is conformal, and a second metal layer that is a fill material. This would be due to the fact that doing so would incorporate a work function layer, a barrier layer, or a resistance reducing cap layer, depending on desired integration, which would produce the desirable result of increasing device performance (via a work function layer or resistance reducing cap layer) or reducing the risk of doping the surrounding dielectric layer (via barrier layer) (Dewey, Paragraph [0031]).
Regarding Claim 3, Li as modified by Gaul and further modified by Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 2, wherein:
-the conductor comprises a first metal layer that is conformal, and a second metal layer that is a fill material. (Corresponding to Dewey barrier layers and work function layers, Paragraph [0031] as detailed in the incorporation of the further teaching of Dewey in Claim 2 above).
Regarding Claim 4, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 1, wherein:
-the source contact (Li, (214LS) and the drain contact (Li, (214LD)) comprise:
-a first metal layer that is conformal (Gaul, (230), see incorporation of the teachings of Gaul into Li above, Fig. 11, Paragraphs [0078]) around the sheet (Li, (210N(2)); and
-a second metal layer that is a fill material (Gaul, (240), see incorporation of the teachings of Gaul into Li above, Fig. 11, Paragraphs [0082]).
Regarding Claim 5, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 4, wherein:
- the first metal layer comprises antimony (Gaul, (230) can be a conductive material…, for example antimony (Sb); Paragraph [0079]), and
-the second metal layer comprises metal generally (Gaul, (240) ‘can be a conductive material including, but not limited to, a metal, for example, aluminum (Al), tungsten (W)…’, Paragraph [0083])
Li, Gaul, and the initial modification by Dewey do not explicitly disclose:
-the second metal layer comprises gold.
Dewey teaches a gate-all-around transistor semiconductor device ((‘Lower Device’ (209); Fig. 2a, Paragraph [0027]) comprising source/drain regions consisting of a metal layer that is a fill material, wherein:
-the metal layer comprises gold. (Dewey, Paragraph [0033])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Dewey into the device of Li as modified by Gaul such that the second metal layer comprises gold. This is because it would produce the expected result of using a low resistivity metal for the metal fill material.
Regarding Claim 6, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 1, further comprising:
-a second sheet (Li, ‘2D SLAB’ (210N), e.g. (210N(3)); Fig. 2A, Paragraph [0041]) over the sheet (Li, (210N(3))).
Regarding Claim 7, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 6, wherein:
-the gate structure (Li, (222L)) is around the second sheet (Li, (210N(3))), wherein the source contact (Li as modified by Gaul, (214LS)) is around the second sheet (Li, (210N(3))), and wherein the drain contact (Li as modified by Gaul, (214LD)) is around the second sheet (210N(3)).
Regarding Claim 8, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 1, further comprising:
- a plate (Li, ‘isolation layer’ (207U); Fig. 2A, Paragraph [0045]) above the sheet (Li, (210N(2))), wherein the plate (Li, (207U)) is substantially parallel to the sheet (Li, as in Fig. 2A), and wherein the plate comprises an insulator material (Li, Paragraphs [0057] and [0064]).
Regarding Claim 9, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 1, wherein:
-the thickness dimension of the sheet (Li, (210N(2))) is 5nm or smaller. (e.g. 1 nm, Paragraph [0041])
Regarding Claim 10, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 1, further comprising:
-a second semiconductor device (Li, ‘PFET’ (204P); Fig. 2A, Paragraph [0011]) over the semiconductor device (Li, (204N)), wherein the second semiconductor device (Li, (204P)) comprises:
-a second sheet (Li, ‘2D SLAB’ (210P), e.g. (210P(2)); Fig. 2A, Paragraph [0045]) comprising a semiconductor (Li, ‘semiconductor material’; Paragraphs [0045]), wherein a length dimension (Li, perpendicular to the plane of Fig. 2A) of the second sheet (Li, the (210P(2))) and a width dimension (Li, lateral of Fig. 2A) of the second sheet (Li, (210P(2))) are greater than a thickness dimension (vertical of Fig. 2A) of the second sheet (Li, (210P(2))) (See Paragraph [0041])
-a second gate structure (Li, upper gate (222U) consisting of gate dielectric (226U) and gate conducting portions (225U); Fig. 2A, Paragraph [0047]) around the second sheet (Li, 210P(2));
-a third spacer (Li, spacer (224US) on the left; Fig. 2A, Paragraph [0047])) adjacent to a first end (e.g. on the left side) of the second gate structure (Li, (222U));
-a fourth spacer (Li, spacer (224UD) on the right; Fig. 2A, Paragraph [0047]) adjacent to a second end (e.g. on the right side) of the second gate structure (Li, (222U));
-a second source contact (Li, ‘source/drain region’ (214US); Fig. 2A, Paragraph [0046]) around the second sheet (Li, (210P(2))) and adjacent to the third spacer (Li, (224US)); and
-a second drain contact (Li, ‘source/drain region’ (214UD); Fig. 2A, Paragraph [0046]) around the second sheet (Li, (210P(2)) and adjacent to the fourth spacer (Li, (224UD)).
Regarding Claim 11, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 10, wherein:
-the sheet (Li, (210N(2))) comprises an N-type semiconductor (Li, ‘a first type of 2D semiconductor material, such as an N-type material’, in order for (204N) to function as an NMOS device within a CMOS configuration; Paragraphs [0039] and [0042]), and wherein the second sheet (Li, (210P(2)) comprises a P-type semiconductor (Li, ‘a second type of 2D semiconductor material, such as a P-type material’, in order for (204P) to function as an PMOS device within a CMOS configuration; Paragraphs [0039] and [0045])
Regarding Claim 12, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 10, wherein:
-the sheet (Li, (210N(2)) comprises a P-type semiconductor (Li, ‘a semiconductor material of a first type (e.g. P-type)’ in order for (204N) to function as a PMOS within a CMOS configuration; Paragraphs [0011] and [0056]-[0057]), and wherein the second sheet (Li, (210P(2))) comprises an N-type semiconductor (Li, ‘a semiconductor material of a second type (e.g. N-type)’ in order for (204P) to function as an NMOS within a CMOS configuration; Paragraphs [0011], [0056], and [0064])
Regarding Claim 13, Li as modified by Gaul and Dewey teaches the semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) of Claim 10, wherein:
- the second semiconductor device (Li, (204P)) is spaced apart from the semiconductor device (Li, (204N)) by a layer (Li, ‘isolation layer’ (207U); Fig. 2A, Paragraph [0045]), wherein the layer is an insulator material (Li, Paragraphs [0057] and [0064]).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Trivedi et al. (U.S. Pub. 2021/0184001), hereinafter Trivedi, in view of Li.
Regarding Claim 19, Trivedi teaches an electronic system (‘interposer’ (700); Fig. 7, Paragraph [0096]), comprising:
-a board (‘second substrate’ (704); Fig. 7, Paragraph [0096], ‘the second substrate (704) may be, for instance, a memory module, a computer motherboard, or another integrated circuit die’);
-a package substrate (substrate within (702); Fig. 7; [0096] says (702) could be an integrated circuit die, which would include a die coupled to a substrate) coupled to the board (704); and
-a die (die within (702); Fig. 7; [0096]) coupled to the package substrate (substrate within (702)),
-the die (die within (702)) comprises a semiconductor device (‘an electronic device’ (100); Fig. 1A, Paragraph [0020], where Fig. 1B is a cross sectional view along line B-B’ (Paragraph [0005]). See Paragraphs [0098] and [0099] in regards to incorporation) comprising:
-a sheet (nanoribbon (110A), e.g. the bottom (110A); Fig. 1B, Paragraph [0028]) comprising a semiconductor (‘semiconductor materials’, Paragraph [0021]), wherein a length dimension (perpendicular to the plane of Fig. 1B) of the sheet (the bottom (110A)) and a width dimension (lateral of Fig. 1B) of the sheet (the bottom (110A)) are greater than a thickness dimension (vertical of Fig. 1B) of the sheet (the bottom (110A)) (The Examiner notes nanoribbons have a greater width dimension than a thickness dimension by definition, as is apparent in Fig. 1B. Please see Fig. 1A wherein an alternative cross-section is presented where a length of the nanoribbon is demonstrated to be greater than a thickness),
-the sheet (the bottom (110A)) having a first sidewall laterally (e.g. the right side of the bottom (110A) as in Fig. 1B) laterally opposite to a second sidewall (e.g. the left side of the bottom (110A) as in Fig. 1B);
-a gate structure (consisting of gate electrode (130) and gate dielectric (115A); Fig. 1B, Paragraph [0028]) around the sheet (the bottom (110A), the gate structure having a gate dielectric (115A) and a gate metal ((130) is a work function metal Paragraph [0031]));
-a first spacer (spacer (122) on the right side; Fig. 1B, Paragraph [0028]) adjacent to a first end (e.g. on the right side) of the gate structure ((130) and (115A)), wherein the gate dielectric (115A) laterally separates the gate metal (130) from the first spacer (right (122));
-a second spacer (spacer (122) on the left side) adjacent to a second end (e.g. on the left side) of the gate structure ((130) and (115A)), wherein the gate dielectric (115A) laterally separates the gate metal (130) from the second spacer (left (122));
-a source contact (‘source/drain regions’ (120) on the right side; Fig. 1B, Paragraph [0028]) around the sheet (the bottom (110A)) and adjacent to the first spacer ((122) on the right side),
-the source contact (the right (120)) comprising a metal (Paragraph [0029]) in contact with an entirety of the first sidewall of the sheet (the right side of bottom (110A)); and
-a drain contact ((120) on the left side) around the sheet (the bottom (110A)) and adjacent to the second spacer ((122) on the left side)
-the source contact (the left (120)) comprising a metal (Paragraph [0029]) in contact with an entirety of the second sidewall of the sheet (the left side of bottom (110A)).
Trivedi does not explicitly disclose:
-a source contact wrapping around the sheet
-a drain contact wrapping around the sheet
Li teaches a semiconductor device (‘NFET’ (204N); Fig. 2A, Paragraph [0039]) comprising of a transistor including 2D-Slabs/nanoribbons/sheets which is incorporable into integrated circuits (Paragraph [0090]), wherein:
-a source contact (‘source/drain region’ (214LS); Fig. 2A, Paragraph [0043]) wraps around the sheet (‘2D SLAB’ (210N), e.g. (210N(2)); Fig. 2A, Paragraph [0041]).
-a drain contact (‘source/drain region’ (214LD); Fig. 2A, Paragraph [0043]) wraps around the sheet (e.g. (210N(2))).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Li into the device of Trivedi such that a source contact wraps around the sheet and a drain contact wraps around the sheet. Furthermore, these incorporated channels which extend into the source and drain contacts will have a thickness dimension of 5nm or small (Li, e.g. 1 nm, Paragraph [0041]). This would be due to the fact that incorporating the structure of the channels of Li into the device of Trivedi would provide for “high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current.” (Li, Paragraph [0007]).
Regarding Claim 20, Trivedi as modified by Li teaches the electronic system (‘interposer’ (700); Fig. 7, Paragraph [0096]) of Claim 19, wherein:
- wherein the thickness dimension of the sheet is 5nm or smaller. (Li, e.g. 1 nm. As discussed in the incorporation of Li into Trivedi above. See Paragraph [0041])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/D.M./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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