Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/29/2025 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore:
The “second bumps” as described in claim 8 must be shown or the feature(s) canceled from the claim(s). More specifically, claim 1 from which claim 8 depends requires the second bumps to be surrounded by a second layer. Claim 8 also requires the second bumps to be on the same surface as the first bumps, i.e., the first surface. However, the drawings only illustrate a single layer surrounding the first and second bumps of claim 8, i.e., “the first layer”.
The “second layer” as required in the claim 13 sub-combination must be shown or the feature(s) canceled from the claim(s). More specifically, claim 11 from which claim 13 depends requires: the second layer to correspond to bumps related to the third die; and the first layer to correspond to bumps related to the first die. Claim 13 appears to be directed to sub-combination 210, 220A, and 220B of Fig. 2C, however does not include details of the first and second layer. Accordingly, the first and second layer are interpreted as corresponding to a single layer surrounding the second and third bumps of claim 11, i.e., “the first layer”.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210005592 A1).
Regarding claim 1 as noted in the drawings objection, Lee discloses a die (326, Fig. 44), comprising: a substrate (2, as shown with enhanced detail in Fig. 34C) with a first surface (the surface directly facing 100) and a second surface opposite from the first surface (the exposed and opposing surface), wherein the substrate comprises a semiconductor material (“a semiconductor substrate” [0596]); first bumps with a first pitch on the first surface of the substrate (6a, the first pitch corresponding to the pitch of bumps connecting with 467, “20 to 150 micrometers” [0619]); a first layer that surrounds the first bumps (52, the region thereof corresponding to the first bumps, the region encircled as A), wherein the first layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the first bumps (the surfaces are illustrated coplanar), and the dielectric material of the first layer having an innermost surface at a same level as an innermost surface of the first bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other); second bumps with a second pitch on the substrate (6a, the second pitch corresponding to the pitch of bumps connecting with 100), wherein the second pitch is greater than the first pitch (as shown by the greatly exaggerated spacing between 6a with each of the respective groups); and a second layer that surrounds the second bumps (52, the region thereof corresponding to the second bumps, the region being encircled as B; regions A and B being of the same 52 and consistent with Applicant’s disclosed embodiment of Fig. 1B showing a single 123 having two regions respectively surrounding 124 and 126), wherein the second layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the second bumps (the surfaces are illustrated coplanar), and the dielectric material of the second layer having an innermost surface at a same level as an innermost surface of the second bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other).
Further as to claim 1, with respect to the relation of the second and first pitches, i.e. “the second pitch is greater than the first pitch”: although Lee failed to expressly disclose the endpoints of the range of the second pitch, or a relation with the first pitch, it has been held that dimensional differences will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such pitches are critical. Furthermore, Lee illustrates the structures forming the second pitch are merely replicates of the same structures forming the first pitch, though with a different spatial arrangement. Therefore, it is reasonable to expect similar properties related thereto; these physical properties reasonably include pitch range, which includes a plurality of values capable of reading on the claimed pitch relation. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation". In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicants have not established the criticality (see paragraph below) of the pitch relation claimed and the Prior Art shows that the first and second pitches are different in the same way claimed, it would have been obvious to one of ordinary skill in the art to select suitable pitches (i.e. dimensions) for the first and second pitches of Lee. MPEP 2144.05.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed pitch relation or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). MPEP 2144.05.
Illustrated below is a marked and annotated figure of Fig. 44, and Fig. 34C of Lee.
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Regarding claim 2, Lee discloses a die (Fig. 44), wherein a number of the first bumps (including all 6a for all 467 in the count, 4 are shown) is greater than a number of the second bumps (including only 6a for 100 on right in the count, 3 are shown).
Regarding claim 3, Lee discloses a die (Fig. 44), further comprising an active layer between the first surface and the second surface of the substrate (4, as shown with enhanced detail in Fig. 34C), wherein the active layer comprises a transistor device (a transistor is illustrated).
Regarding claim 4, Lee discloses a die (Fig. 44), wherein the transistor device is part of active circuitry that is configured to provide serialization or deserialization of signals between the first bumps and the second bumps (the transistor is connected to the circuitry within die 411, therefore part of the same circuitry; die 411 is “configured for serial-advanced-technology-attachment (SATA) ports” [0538]).
Regarding claim 5, Lee discloses a die (Fig. 44), wherein the transistor device is part of active circuitry that is configured to change a voltage or a frequency of a signal sent between the first bumps and the second bumps (the transistor is connected to the circuitry within die 411, therefore part of the same circuitry; die 411 is “configured to regulate a voltage” [0538], i.e., change a voltage).
Regarding claim 8, Lee discloses a die (Fig. 44), wherein the second bumps are on the first surface of the substrate (the grouping of bumps selected in the claim 1 rejection).
Regarding claim 9, Lee discloses a die (Fig. 34C), further comprising: conductive traces in the substrate (6 within 20) to electrically couple the first bumps to the second bumps.
Lee fails to expressly illustrate the conductive traces electrically coupling the first bumps to the second bumps. However, Lee illustrates variations in the conductive traces, wherein some conductive traces are connected to each of the bumps (each 6a connects to 6) and some conductive traces are not connected to bumps (at least one 6 is not connected to 6a); each conductive trace appearing to be a deliberately formed structure having an intended purpose (a shape chosen for an intended use).
Lee discloses an alternative embodiment with variations in the conductive traces (Fig. 34D), wherein some conductive traces are connected to each of the bumps (each 6a connects to 6), some conductive traces are not connected to bumps (at least one 6 is not connected to 6a), and some conductive traces interconnecting bumps (the two right-most 6a are interconnected by 6); each conductive trace being deliberately formed to have an intended electrical path (a shape chosen for an intended use).
Lee further discloses an alternative embodiment with variations in the conductive traces (67 within 551, Fig. 44), wherein some conductive traces are connected to each of a plurality of bumps (each 563 connects to 67), some conductive traces are not connected to any bumps (at least one 67 is not connected to 563), some conductive traces connected to only one bump of a single die (at least one 563 of 100 is connected to 67), some conductive traces interconnect bumps of a single die (at least two 563 of 100 are interconnected by 67), and some conductive traces interconnect bumps of a plurality of dies (at least two 563 of 411 and 100 are interconnected by 67); each conductive trace being deliberately formed to have an intended electrical path (a shape chosen for an intended use).
Further as to claim 9, with respect to the shape of the conductive traces, i.e., “conductive traces in the substrate to electrically couple the first bumps to the second bumps”, it would have been an obvious matter of design choice to adjust the shape of the conductive traces to be isolated from, separately connecting, or interconnecting the first and second bumps as taught by Lee (see, e.g., Figs. 34C, 34D, 44) who teaches conductive traces being deliberately formed to have intended electrical paths. Moreover, a change in shape is a matter of design choice, which a person within the level of ordinary skill in the art would have found to be obvious absent persuasive evidence that the particular configuration of the claimed conductive traces was significant, and a change in shape is generally recognized as being within the level of ordinary skill in the art. Therefore, it would have been obvious to have the claimed conductive trace configuration because it is a variation in shape to have in intended electrical path. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04 (IV)(B).
Regarding claim 10, Lee discloses a die (Fig. 44), wherein the first pitch is approximately 20µm or smaller (the range cited in claim 1 has an overlapping endpoint at 20µm).
Regarding independent claim 11 as noted in the drawings objection, Lee discloses a die module (Fig. 44), comprising: a first die (467), wherein the first die has first bumps with a first pitch (6a, “20 to 150 micrometers” [0619]); a second die coupled to the first die (326), wherein the second die has second bumps with the first pitch (6a, the ones connecting with 467) and third bumps with a second pitch (6a, the second pitch corresponding to the pitch of bumps connecting with 100) that is greater than the first pitch (as shown by the greatly exaggerated spacing between 6a with each of the respective groups), wherein the second bumps are bonded to the first bumps on the first die (directly bonded), a first layer that surrounds the second bumps (52, the region thereof corresponding to the second bumps, the region encircled as A), wherein the first layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the second bumps (the surfaces are illustrated coplanar), and the dielectric material of the first layer having an innermost surface at a same level as an innermost surface of the second bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other), and a second layer that surrounds the third bumps (52, the region thereof corresponding to the third bumps, the region being encircled as B; regions A and B being of the same 52 and consistent with Applicant’s disclosed embodiment of Fig. 1B showing a single 123 having two regions respectively surrounding 124 and 126), wherein the second layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the third bumps (the surfaces are illustrated coplanar), and the dielectric material of the second layer having an innermost surface at a same level as an innermost surface of the third bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other); and a third die coupled to the second die (100), wherein the third die has fourth bumps with the second pitch (6a), wherein the fourth bumps are bonded to the third bumps on the second die (directly bonded).
Further as to claim 11, with respect to the relation of the second and first pitches, i.e. “a second pitch that is greater than the first pitch”: although Lee failed to expressly disclose the endpoints of the range of the second pitch, or a relation with the first pitch, it has been held that dimensional differences will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such pitches are critical. Furthermore, Lee illustrates the structures forming the second pitch are merely replicates of the same structures forming the first pitch, though with a different spatial arrangement. Therefore, it is reasonable to expect similar properties related thereto; these physical properties reasonably include pitch range, which includes a plurality of values capable of reading on the claimed pitch relation. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation". In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicants have not established the criticality (see paragraph below) of the pitch relation claimed and the Prior Art shows that the first and second pitches are different in the same way claimed, it would have been obvious to one of ordinary skill in the art to select suitable pitches (i.e. dimensions) for the first and second pitches of Lee. MPEP 2144.05.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed pitch relation or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). MPEP 2144.05.
Regarding claim 12, Lee discloses a die module (Fig. 44), wherein the second die is over the first die (over in the direction away from 551), and wherein the third die is over the second die (over in the direction towards 551).
Regarding claim 13, Lee discloses a die module (Fig. 44), wherein the third die is adjacent to the first die (directly adjacent), and wherein the second die is under the first die and the third die (under in the direction away from 551).
Regarding claim 14, Lee discloses a die module (Fig. 44), wherein the second die comprises active circuitry with a transistor device (4, as shown with enhanced detail in Fig. 34C, a transistor is illustrated).
Regarding claim 15, Lee discloses a die module (Fig. 44), wherein the transistor device is part of circuitry configured to change a frequency of a signal sent between the first die and the third die (the transistor is connected to the circuitry within die 411, therefore part of the same circuitry; the plurality of circuitry features within 411 include DC as well as radio-frequency signals, both appearing requisite for device function, therefore changing frequency, [0538]; the circuitry is illustrated spatially between the first and third die, and operates on signals sent within a space between the first and third die; the second die being between the first and third die).
Regarding claim 16, Lee discloses a die module (Fig. 44), wherein the transistor device is part of circuitry configured to change a voltage of a signal sent between the first die and the third die (the transistor is connected to the circuitry within die 411, therefore part of the same circuitry; die 411 is “configured to regulate a voltage” [0538], i.e., change a voltage; the second die being between the first and third die).
Regarding claim 17, Lee discloses a die module (Fig. 44), wherein the transistor device is part of circuitry configured to provide serialization or deserialization of signals sent between the first die and the third die (the transistor is connected to the circuitry within die 411, therefore part of the same circuitry; die 411 is “configured for serial-advanced-technology-attachment (SATA) ports” [0538]; the second die being between the first and third die).
Regarding claim 18, Lee discloses a die module (Fig. 44), wherein the first pitch is approximately 20µm or smaller (the range cited in claim 11 has an overlapping endpoint at 20µm).
Regarding claim 19, Lee discloses a die module (Fig. 44), wherein the second bumps are bonded to the first bumps with a hybrid bonding interconnect architecture (the bumps and first and second layers cited in the claim 11 rejection collectively form a hybrid bonding architecture).
Regarding claim 20, Lee discloses a die module (Fig. 44), wherein the third bumps are bonded to the fourth bumps with a hybrid bonding interconnect architecture (the bumps and first and second layers cited in the claim 11 rejection collectively form a hybrid bonding architecture).
Regarding claim 21, Lee discloses a die module (Fig. 44), further comprising: a fourth die coupled to the first die (551); and a fifth die coupled to the fourth die (537).
Regarding claim 22, Lee discloses a die module (Fig. 44), wherein the fourth die comprises fifth bumps with a third pitch (570, and the illustrated pitch thereof) with the fifth bumps coupled to the first die (indirectly coupled through internal wirings within 551), and sixth bumps with a fourth pitch (563, and the illustrated pitch thereof), wherein the fifth die is coupled to the sixth bumps (indirectly coupled through internal wirings within 551).
Regarding claim 23, Lee discloses a die method (Fig. 44), wherein the fourth pitch is smaller than the third pitch (the fourth pitch includes a denser arrangement of 563 within a span of overlying structure 100, relative to the sparser arrangement of 570 within the same span of overlying structure 100).
Regarding independent claim 24, Lee discloses an electronic system (Fig. 44), comprising: a board (537); a package substrate coupled to the board (551); and a die module coupled to the package substrate (coupled by 563), wherein the die module comprises: a first die (467), wherein the first die has first bumps with a first pitch (6a, “20 to 150 micrometers” [0619]); a second die coupled to the first die (326), wherein the second die has second bumps with the first pitch (6a, the ones connecting with 467) and third bumps with a second pitch (6a, the second pitch corresponding to the pitch of bumps connecting with 100) that is greater than the first pitch (as shown by the greatly exaggerated spacing between 6a with each of the respective groups), wherein the second bumps are bonded to the first bumps on the first die (directly bonded), a first layer that surrounds the second bumps (52, the region thereof corresponding to the second bumps), wherein the first layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the second bumps (the surfaces are illustrated coplanar), and the dielectric material of the first layer having an innermost surface at a same level as an innermost surface of the second bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other), and a second layer that surrounds the third bumps (52, the region thereof corresponding to the third bumps), wherein the second layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the third bumps (the surfaces are illustrated coplanar), and the dielectric material of the second layer having an innermost surface at a same level as an innermost surface of the third bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other); and a third die coupled to the second die (100), wherein the third die has fourth bumps with the second pitch (6a), wherein the fourth bumps are bonded to the third bumps on the second die (directly bonded).
Further as to claim 24, with respect to the relation of the second and first pitches, i.e. “a second pitch that is greater than the first pitch”: although Lee failed to expressly disclose the endpoints of the range of the second pitch, or a relation with the first pitch, it has been held that dimensional differences will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such pitches are critical. Furthermore, Lee illustrates the structures forming the second pitch are merely replicates of the same structures forming the first pitch, though with a different spatial arrangement. Therefore, it is reasonable to expect similar properties related thereto; these physical properties reasonably include pitch range, which includes a plurality of values capable of reading on the claimed pitch relation. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation". In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicants have not established the criticality (see paragraph below) of the pitch relation claimed and the Prior Art shows that the first and second pitches are different in the same way claimed, it would have been obvious to one of ordinary skill in the art to select suitable pitches (i.e. dimensions) for the first and second pitches of Lee. MPEP 2144.05.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed pitch relation or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). MPEP 2144.05.
Regarding claim 25, Lee discloses an electronic system (Fig. 44), wherein the second die is over the first die (over in the direction away from 551) and the third die is over the second die (over in the direction towards 551), or wherein the third die is adjacent to the first die and the second die is under the first die and the third die.
Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dabral (US 20230085890 A1).
Note that claim 1 was previously address above, however, it’s being addressed differently here based on the reading of the reference, particularly to the assignment of the die and bumps in order to address the separate and distinct species of dependent claim 6.
Regarding claim 1, Lee discloses a die (411, Fig. 44), comprising: a substrate (2, as shown with enhanced detail in Fig. 34D) with a first surface (the surface directly facing 551) and a second surface opposite from the first surface (the surface directly facing 326), wherein the substrate comprises a semiconductor material (“a semiconductor substrate” [0596]); first bumps with a first pitch on the first surface of the substrate (563, the first pitch corresponding to the pitch of the bumps connecting with 551); second bumps with a second pitch on the substrate (6a, the second pitch corresponding to the pitch of bumps connecting with 326), wherein the second pitch is greater than the first pitch (the layout of 6a is sparser within the same span of 411 than the layout of 563 within the same span of 411, therefore greater pitch); and a second layer that surrounds the second bumps (52, the region thereof corresponding to the first bumps), wherein the second layer comprises a dielectric material (“a silicon-oxide layer” [0609]) having an outermost surface at a same level as an outermost surface of the second bumps (the surfaces are illustrated coplanar), and the dielectric material of the second layer having an innermost surface at a same level as an innermost surface of the second bumps (selecting the surfaces of 52 and 6a parallel with, nearest, and directly facing 2 as the respective innermost surfaces, these innermost surfaces being coplanar with each other).
Lee fails to teach a first layer that surrounds the first bumps, wherein the first layer comprises a dielectric material having an outermost surface at a same level as an outermost surface of the first bumps, and the dielectric material of the first layer having an innermost surface at a same level as an innermost surface of the first bumps. However, in an alternative embodiment Lee discloses bump species may be selected from a finite selection of known bump species, the bump species including: bumps with a coplanar dielectric material (the species of Fig. 34D); and bumps with a protruding portion (the species of Fig. 34B). Thus, Lee teaches the bump species configuration of the die may be varied and is not critical to device operation. Nonetheless, Lee fails to teach the specific combination of bump species, i.e., the first and second bumps each are coplanar with a dielectric material.
Dabral discloses a die with first and second bumps (Fig. 14, die 102A, bumps 174 and 112, respectively), and further teaches the die may include a bump species configuration wherein the first and second bumps respectively include a surrounding first and second layer (177 and 139, respectively, greater detail shown in Fig. 1B), wherein the first layer comprises a dielectric material (“a back side passivation layer” necessarily being a dielectric material to prevent shorting among the first bumps [0047]) having an outermost surface at a same level as an outermost surface of the first bumps (the surfaces are illustrated coplanar), and the dielectric material of the first layer having an innermost surface at a same level as an innermost surface of the first bumps (selecting the surfaces of 177 and 174 parallel with, nearest, and directly facing 102B as the respective innermost surfaces, these innermost surfaces being coplanar with each other); and the second layer comprises a dielectric material (“a dielectric material” [0051]) having an outermost surface at a same level as an outermost surface of the second bumps (the surfaces are illustrated coplanar), and the dielectric material of the second layer having an innermost surface at a same level as an innermost surface of the second bumps (selecting the surfaces of 139 and 112 parallel with, nearest, and directly facing 102B as the respective innermost surfaces, these innermost surfaces being coplanar with each other). Thus, Dabral teaches bump species configuration may include first and second bumps that are each coplanar with a dielectric material.
A person of ordinary skill in the art at the time of filing could have modified the bump species configuration of Lee by selecting the first bump species from the known finite selection (i.e., selecting bumps with a coplanar dielectric material), and would have had predictable results because this specific species configuration was known in the art (Dabral). Doing so would arrive at the claimed bump and layer configuration. Therefore, it would have been obvious to have the claimed first and second bump and layer configuration because it is a selection of species from a known finite selection according to configurations known in the art.
Regarding claim 6, Lee in view of Dabral discloses a die (Lee, Fig. 44), wherein the second bumps are on the second surface of the substrate (as cited in the claim 1 rejection).
Regarding claim 7, Lee in view of Dabral discloses a die (Lee, Fig. 44), further comprising: through substrate vias (TSVs) through a thickness of the substrate to electrically couple first pads to second pads (157).
Response to Arguments
Applicant's arguments filed 6/30/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Lee does not disclose…the dielectric material of the first layer having an innermost surface at a same level as an innermost surface of the first bumps,…where the second layer comprises a dielectric material having an outermost surface at a same level as an outermost surface of the second bumps, and the dielectric material of the second layer having an innermost surface at a same level as an innermost surface of the second bumps, as is required by Applicant's claims”. Applicant asserts similar arguments regarding substantially similar amendments to independent claims 11 and 24. Remarks at pg. 11.
Examiner’s reply:
The examiner disagrees and does not find the argument persuasive because Applicant's arguments point to feature 12 of Lee as the contended dielectric layers. However, the examiner has not relied upon this feature in the claim rejection under 35 U.S.C. 103 as the contended dielectric layer, and instead has relied upon feature 52 of Lee. Thus, the examiner finds the instant Office action having a dielectric layer consistent with the surface configuration of the claim amendments (Lee, 52, as cited herein).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817