DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed December 15th, 2025 in response to the Non-Final Office Action mailed 09/17/2025 are noted.
Applicant’s amendments to the claims are noted.
3. Claims 1-20 remain pending in the application; Claims 12-17 are now withdrawn.
4. Claims 1-11 and 18-20 have been fully considered in examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 4-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (U.S. PG Pub No US2020/0373420A1) (of record) in view of Li (U.S. PG Pub No US2019/0189779A1) (of record) and Yanagisawa (JP Pub No JP2008028110A) (of record). *(see translation made of record 9/17/2025 for line ref # citations)*
Regarding claim 1, Chou teaches a transistor device (100) fig. 6 [0020], comprising:
a channel (112) fig. 6 [0020], wherein the channel (112) comprises a first semiconductor material (AlGaN) [0023];
a source contact (132) fig. 6 [0039] at a first (left) end of the channel (112);
a drain contact (142) fig. 6 [0039] at a second end of the channel (112);
a gate electrode (121) fig. 6 [0020] between the source contact (132) and the drain contact (142);
a field plate (122) fig. 6 [0034] that extends from the gate electrode (121) towards the drain contact (142);
a plurality of protrusions (see annotated fig. 6 below) that extend out (downward) from the field plate (122) towards the channel (112), wherein the protrusions (of field plate comprise) a second semiconductor material (silicon in NiSi silicide [0035]); and
a protrusion (142-circled area protruding into 141) that extends (vertically) out from the drain contact (142) towards the channel (112) (see annotated fig. 6-II below).
[AltContent: textbox (1st Stepped Surface)][AltContent: textbox (2nd stepped surface)][AltContent: arrow][AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (P-Top Height )][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Protrusions )][AltContent: connector][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: connector]
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Annotated fig. 6 of Chou designating relevant features of field plates (122) and (134)
[AltContent: arrow][AltContent: textbox (112)][AltContent: connector][AltContent: textbox (142-protrusion directed vertically towards 112-channel )][AltContent: textbox (142-protrusion into 141 )][AltContent: oval]
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Annotated fig. 6-II of Chou with close-up of 142 protruding into 141 towards 112
However, Chou does not explicitly disclose wherein each of the plurality of protrusions (of field plate) is a second semiconductor material (overall), wherein each of the plurality of protrusions (of field plate) is discontinuous with one another.
Li teaches a transistor device (100) fig. 1 [0012] wherein each of the plurality of protrusions (of field plate 150) fig. 1 [0019, 0032] is a second semiconductor material (142 material polysilicon gate electrode [0017, 0032]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductive gate material constituting the entirety of the field plate - comprising protrusions – in Chou to be composed of polysilicon instead of a metal-based conductor [0017] in order to enable the formation of a gate dielectric by oxidation [0017] of the plate as well as the material’s favorable electric field response properties [0032], as taught by Li.
However, Chou in view of Li does not explicitly disclose wherein each of the plurality of protrusions (of field plate) is discontinuous with one another.
Yanagisawa teaches a transistor device [see fig. 8, 0045] wherein each of the plurality of protrusions (individual of 43) fig. 8 [0045-0046] (protruding from/of field plate 34) fig. 8 [0045] is discontinuous with one another (individual 43s discontinuous with surrounding elements).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the field plate protrusions of Chou in view of Li to further comprise individual, discontinuous portions of contact material [0045-0046] in order to enhance the interconnectivity of the field plate with adjacent circuitry [0038, 0043, 0046], as taught by Yanagisawa.
Regarding claim 2, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. Chou also teaches wherein the protrusions (of field plate (122) fig. 6 [0034]) have a first distribution density (proportional to field intensity) [0003] proximate to the gate electrode (121) fig. 6 [0020] and a second distribution density (proportional to field intensity) [0003] proximate to an end (right end adjacent the drain) of the field plate (122), wherein the second distribution density is smaller than the first distribution density (field intensity/distribution density of field plate near drain smaller than nearer gate [0003]).
Regarding claim 4, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. Chou also teaches wherein the channel (112) fig. 6 [0020] comprises gallium and nitrogen (AlGaN) [0023].
Regarding claim 5, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. Chou also teaches wherein the plurality of protrusions (of field plate (122) fig. 6 [0034]) have a uniform height (at top; P-Top level - see annotated fig. 6 of Chou above).
Regarding claim 6, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. Chou also teaches further comprising:
a second field plate (134) fig. 6 [0039] extending out from the source contact (132) fig. 6 [0039], wherein the second field plate (134) extends past an (top/right/left) end of the field plate (122) fig. 6 [0020, 0034].
Regarding claim 7, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 6. Chou also teaches further comprising:
a second plurality of protrusions (see annotated fig. 6 above), wherein the second plurality of protrusions extend down from the second field plate (134) fig. 6 [0039], and wherein the second plurality of protrusions comprise a semiconductor material (may comprise silicon in NiSi silicide [0035], same as field plate 122 material [0039]).
Regarding claim 8, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 7. Chou also teaches wherein the second plurality of protrusions (of field plate 134) fig. 6 [0039] have a first distribution density towards a center of the second field plate (near gate) and a second distribution density towards an end of the second field plate (near drain), wherein the second distribution density is lower than the first density (field intensity/distribution density of field plate near drain smaller than nearer gate [0003]).
Regarding claim 9, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. Chou also teaches wherein the field plate (122) fig. 6 [0034] has a first stepped surface and a second stepped surface that is further (higher) from the channel (112) fig. 6 [0020] than the first stepped surface (stepped surfaces created by protrusion steps) (see annotated fig. 6 of Chou above).
Regarding claim 10, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 9. Chou also teaches wherein the plurality of protrusions (of field plate 122) [0034] are on the second stepped surface (see annotated fig. 6 of Chou above).
Regarding claim 11, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. Chou also teaches wherein a dielectric (150) fig. 6 [0029] surrounding the protrusions has a compositional gradient (may include a multilayer of compositionally distinct materials establishing a graduated/variable composition profile [0029]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chou (U.S. PG Pub No US2020/0373420A1) (of record) in view of Li (U.S. PG Pub No US2019/0189779A1) (of record) and Yanagisawa (JP Pub No JP2008028110A) (of record), as applied in claim 1 above, and further in view of Kim (U.S. PG Pub No US2020/0212218A1) (of record).
Regarding claim 3, Chou in view of Li and Yanagisawa teaches the transistor device (100) fig. 6 [0020] as discussed above in claim 1. However, Chou does not explicitly disclose wherein the plurality of protrusions (of field plate 122) [0035] are P-doped [0035].
Kim teaches a transistor device (200) fig. 2 [0023] wherein the protrusions (of field plate 105b, 105c) fig. 2 [0023] are p-doped (possibly p-doped poly-Si) [0023].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Chou such that the conductive field plate(s) is/are composed of polysilicon because of the material’s favorable doping properties [0023] that offer control and possible improvement of device operating parameters [0006], as taught by Kim.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (U.S. PG Pub No US2020/0373420A1) (of record) in view of Kim (U.S. PG Pub No US2020/0212218A1) (of record) and Yanagisawa (JP Pub No JP2008028110A) (of record).
Regarding claim 18, Chou teaches an electronic system (100) fig. 6 [0020] comprising:
a transistor device (100) fig. 6 [0020], wherein the transistor device (100) comprises:
a channel (112) fig. 6 [0020], wherein the channel (112) comprises a first semiconductor material (AlGaN) [0023];
a source contact (132) fig. 6 [0039] at a first (left) end of the channel (112);
a drain contact (142) fig. 6 [0039] at a second end of the channel (112);
a gate electrode (121) fig. 6 [0020] between the source contact (132) and the drain contact (142);
a field plate (122) fig. 6 [0034] that extends from the gate electrode (121) towards the drain contact (142); and
a plurality of protrusions (see annotated fig. 6 below) that extend out (downward) from the field plate (122) towards the channel (112), wherein the protrusions (of field plate comprise) a second semiconductor material (silicon in NiSi silicide [0035]).
a protrusion (142-circled area protruding into 141) that extends (vertically) out from the drain contact (142) towards the channel (112) (see annotated fig. 6-II below).
[AltContent: textbox (1st Stepped Surface)][AltContent: textbox (2nd stepped surface)][AltContent: arrow][AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (P-Top Height )][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Protrusions )][AltContent: connector][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: connector]
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Annotated fig. 6 of Chou designating relevant features of field plates (122) and (134)
[AltContent: arrow][AltContent: textbox (112)][AltContent: connector][AltContent: textbox (142-protrusion directed vertically towards 112-channel )][AltContent: textbox (142-protrusion into 141 )][AltContent: oval]
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Annotated fig. 6-II of Chou with close-up of 142 protruding into 141 towards 112
However, Chou does not explicitly disclose an electronic system comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises a/the transistor device (100),
wherein each of the plurality of protrusions (of field plate) is a second semiconductor material (overall),
wherein each of the plurality of protrusions (of field plate) is discontinuous with one another.
Kim teaches an electronic system [see title] comprising:
a board (PCB) [0002];
a package substrate (surface mount package) [0002] coupled to (assembled on) [0002] the board; and
a die [0002, 0004] coupled to the package substrate, wherein the die [0004] comprises a/the transistor device (MOSFET included on the die) [0002, 0004],
wherein each of the plurality of the protrusions (of field plate 105b, 105c) fig. 2 [0023] is/are a second semiconductor material (possibly p-doped poly-Si) [0023].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Chou to be configured in the the well-known PCB-package-die electronic system assembly [0002-0004] disclosed by Kim in order to host a large number of MOSFET cells [0002] capable of handling a significant amount of power [0002-0004], as taught by Kim. Moreover, the conductive field plate(s) being composed of polysilicon instead of a metal-silicide enables the silicon-semiconductor material’s favorable doping properties [0023] to offer control and possible improvement of device operating parameters [0006], as taught by Kim.
However, Chou in view of Kim does not explicitly disclose wherein each of the plurality of protrusions (of field plate) is discontinuous with one another.
Yanagisawa teaches a transistor device [see fig. 8, 0045] wherein each of the plurality of protrusions (individual of 43) fig. 8 [0045-0046] (protruding from/of field plate 34) fig. 8 [0045] is discontinuous with one another (individual 43s discontinuous with surrounding elements).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the field plate protrusions of Chou in view of Kim to further comprise individual, discontinuous portions of contact material [0045-0046] in order to enhance the interconnectivity of the field plate with adjacent circuitry [0038, 0043, 0046], as taught by Yanagisawa.
Regarding claim 19, Chou in view of Kim and Yanagisawa teaches the electronic system (100) fig. 6 [0020] as discussed above in claim 18. Chou also teaches wherein the protrusions (of field plate (122) fig. 6 [0034]) have a first distribution density (proportional to field intensity) [0003] proximate to the gate electrode (121) fig. 6 [0020] and a second distribution density (proportional to field intensity) [0003] proximate to an end (right end adjacent the drain) of the field plate (122), wherein the second distribution density is smaller than the first distribution density (field intensity/distribution density of field plate near drain smaller than nearer gate [0003]).
Regarding claim 20, Chou in view of Kim and Yanagisawa teaches the electronic system (100) fig. 6 [0020] as discussed above in claim 18. However, Chou does not explicitly disclose wherein the plurality of protrusions (of field plate 122) [0035] are P-doped [0035].
Kim teaches a transistor device (200) fig. 2 [0023] wherein the protrusions (of field plate 105b, 105c) fig. 2 [0023] are p-doped (possibly p-doped poly-Si) [0023].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Chou such that the conductive field plate(s) is/are composed of polysilicon because of the material’s favorable doping properties [0023] that offer control and possible improvement of device operating parameters [0006], as taught by Kim.
Response to Arguments
Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive.
With respect to Applicant’s argument(s) of amended claims 1 and 18 that “Applicant does not understand Chou as disclosing a protrusion that extends out from the drain contact towards the channel” – it is visually apparent from annotated fig. 6-II of Chou reproduced below that the drain contact 142 possesses a convex portion that protrudes downward into 141 in the direction of underlying channel 112.
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Applicant has not specifically addressed why the convex portion of drain contact 142 of Chou cannot be considered to read on the newly-added limitation of “a protrusion (142-circled area protruding into 141) that extends (vertically) out from the drain contact (142) towards the channel (112) (see annotated fig. 6-II above)”, as applied in the 35 U.S.C. 103 rejection of claims 1 and 18 above. Therefore, the revised 35 U.S.C. 103 rejection of claims 1 and 18 is considered to be a sufficient response-to-arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references disclosed on the PTO-892 form (of record) are considered relevant to the present disclosure because they disclose other examples of transistor devices comprising field plates with multiple, separate/discontinuous protrusions.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/09/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892