DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The amendment filed on May 13th, 2025 has been amended. By this amendment claims 1 and 23 have been amended. Accordingly, claims 1-25 are pending in the present applicant in which claims 13-22 have been withdrawn from further consideration as being drawn to non-elected invention.
New Grounds of Rejection
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 and 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (U.S. Pub. 2020/0098926).
In re claim 1, Sharma discloses a transistor gate stack, comprising a semiconductor channel 102 (see paragraph [0020] and figs. 8A-B); an interlayer (IL) 104 over and in direct physical contact with the semiconductor channel 102 (see paragraph [0023] and figs. 8A-B), wherein the IL 104 has a thickness 112 of (between 1 nm and 3 nm) and comprises zirconium (see paragraph [0029] and figs. 8A-B, note that, Sharma discloses that the IL may include zirconium oxide); a gate dielectric (105,106) over the IL 104; and a gate metal 108 over the gate dielectric (105,106) (see paragraph [0030] and figs. 8A-B).
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Sharma discloses that the IL 104 has a thickness 112 of between 1 nm and 3 nm (see paragraph [0029]) but is silent to wherein the IL has a thickness of 1 nm or less.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness range of the IL in Sharma during routine experimentation to be in a range of 1 nm or less since the thickness range of the IL in Sharma is overlapping with the thickness range of the IL of the claimed invention and therefore it is respectfully submitted that there is no evidence indicating the thickness range of the IL is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
In re claim 2, as applied to claim 1 above, Sharma discloses wherein the IL 104 further comprises oxygen (see paragraph [0029] and figs. 8A-B, note that, Sharma discloses that the IL 104 may include zirconium oxide).
In re claim 3, as applied to claim 2 above, Sharma discloses wherein
the IL 104 comprises a monolayer (see paragraph [0029] and figs. 8A-B).
In re claim 4, as applied to claim 3 above, Sharma discloses that the IL 104 have a thickness 112 of between 1 nm and 3 nm (see paragraph [0029]) but is silent to wherein the IL has a thickness of 0.5nm or less.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness range of the IL in Sharma during routine experimentation to be in a range of 0.5nm or less since it is respectfully submitted that there is no evidence indicating the thickness range of the IL is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
In re claim 5, as applied to claim 1 above, Sharma in the current embodiment is silent to wherein the gate stack is a planar gate stack.
However, Sharma discloses in another embodiment as shown in (paragraph [0052]) that the transistors may include a wide variety of other types and configurations such as planar transistors, non-planar transistors, or a combination of both.
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught in the another embodiment of Sharma into the current embodiment of Sharma to have the transistor gate stack to include a planar gate-stack in order to improve integration and performance of the device.
In re claim 6, as applied to claim 1 above, Sharma discloses wherein the gate stack is a non-planar gate stack (see paragraph [0006] and figs. 8A-B).
In re claim 7, as applied to claim 6 above, Sharma discloses the semiconductor channel 102 is a fin (see paragraph [0041] and figs. 8A-B), and wherein the IL 104 is on a top surface of the fin 102 and sidewall surfaces of the fin 102 (see paragraph [0041] and figs. 8A-B).
In re claim 8, as applied to claim 6 above, Sharma discloses wherein the semiconductor channel 102 is a nanowire or a nanoribbon, and wherein the IL 104 surrounds a perimeter of the nanowire or the nanoribbon 102 (see paragraph [0043] and figs. 9A-B).
In re claim 9, as applied to claim 1 above, Sharma discloses wherein the semiconductor channel 102 comprises silicon (see paragraph [0021] and figs. 8A-B and 9A-B).
In re claim 10, as applied to claim 1 above, Sharma discloses wherein the transistor gate stack 108-2 is between a source region 116 and a drain region 118 (see paragraphs [0039], [0040] and figs. 6-9).
In re claim 11, as applied to claim 1 above, Sharma discloses wherein the gate dielectric is a high-k dielectric (see paragraph [0053]).
In re claim 12, as applied to claim 1 above, Sharma discloses wherein the gate dielectric is a ferroelectric gate oxide (see paragraph [0023]).
In re claim 23, Sharma discloses an electronic system, comprising a board 1502; a package substrate 1504 coupled to the board 1502 (see paragraph [0068] and fig. 14); and a die 1520 coupled to the package substrate 1504, wherein the die 1520 comprises a gate stack (see paragraph [0068] and figs. 8A-B and 14), comprising a semiconductor channel 102 (see paragraph [0020] and figs. 8A-B); an interlayer (IL) 104 over and in direct physical contact with the semiconductor channel, 102 (see paragraph [0023] and figs. 8A-B) wherein the IL 104 has a thickness of between 1 nm and 3 nm (see paragraph [0029] and figs. 8A-B), and wherein the IL comprises zirconium and oxygen (see paragraph [0029] and figs. 8A-B); a gate dielectric (105,106) over the IL 104; and a gate metal 108 over the gate dielectric (105,106) (see paragraph [0030] and figs. 8A-D).
Sharma discloses that the IL 104 has a thickness 112 of between 1 nm and 3 nm (see paragraph [0029]) but is silent to wherein the IL has a thickness of 1 nm or less.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness range of the IL in Sharma during routine experimentation to be in a range of 1 nm or less since the thickness range of the IL in Sharma is overlapping with the thickness range of the IL of the claimed invention and therefore it is respectfully submitted that there is no evidence indicating the thickness range of the IL is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
In re claim 24, as applied to claim 23 above, Sharma in the current embodiment is silent to wherein the gate stack is a planar gate stack.
However, Sharma discloses in another embodiment as shown in {paragraph [0052]) that the transistors may include a wide variety of other types and configurations such as planar transistors, non-planar transistors, or a combination of both.
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught in the another embodiment of Sharma into the current embodiment of Sharma to have the transistor gate stack to include a planar gate-stack in order to improve integration and performance of the device.
In re claim 25, as applied to claim 23 above, Sharma discloses wherein the gate stack is a non-planar gate stack.(see paragraph [0006] and figs. 8A-B).
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (U.S. Pub. 2020/0098925).
In re claim 1, Dewey discloses a transistor gate stack, comprising a semiconductor channel 125 (see paragraph [0023] and fig. 2); an interlayer (IL) 130 over and in direct physical contact with the semiconductor channel 125 (see paragraph [0026] and fig. 2), wherein the IL 130 has a thickness T3 of (about 0.8 nm to 3.8 nm) and comprises zirconium (see paragraph [0026] and fig. 2); a gate dielectric 140 over the IL (see paragraph [0027] and fig. 2); and a gate metal 150 over the gate dielectric 140 (see paragraph [0029] and fig. 2).
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Dewey discloses that the IL 130 has a thickness T3 of about 0.8 nm to 3.8 nm (see paragraph [0026]) but is silent to wherein the IL has a thickness of 1 nm or less.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness range of the IL in Dewey during routine experimentation to be in a range of 1 nm or less since the thickness range of the IL in Dewey is overlapping with the thickness range of the IL of the claimed invention and therefore it is respectfully submitted that there is no evidence indicating the thickness range of the IL is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
In re claim 2, as applied to claim 1 above, Dewey discloses wherein the IL 130 further comprises oxygen (see paragraph [0026]).
In re claim 3, as applied to claim 2 above, Dewey discloses wherein
the IL 130 comprises a monolayer (see paragraph [0026] and fig. 2).
In re claim 4, as applied to claim 3 above, Dewey discloses that the IL 130 have a thickness T3 of about 0.5 nm to 10 nm (see paragraph [0026]) but is silent to wherein the IL has a thickness of 0.5nm or less.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness range of the IL in Dewey during routine experimentation to be in a range of 0.5nm or less since it is respectfully submitted that there is no evidence indicating the thickness range of the IL is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
In re claim 5, as applied to claim 1 above, Dewey discloses wherein the gate stack is a planar gate stack (see paragraph [0022] and fig. 2).
In re claim 6, as applied to claim 1 above, Dewey discloses wherein the gate stack is a non-planar gate stack (see paragraph [0022] and fig. 2).
In re claim 7, as applied to claim 6 above, Dewey discloses the semiconductor channel is a fin, and wherein the IL is on a top surface of the fin and sidewall surfaces of the fin (see paragraph [0022]).
In re claim 8, as applied to claim 6 above, Dewey discloses wherein the semiconductor channel is a nanowire or a nanoribbon, and wherein the IL surrounds a perimeter of the nanowire or the nanoribbon (see paragraph [0022]).
In re claim 9, as applied to claim 1 above, Dewey discloses wherein the semiconductor channel 102 comprises silicon (see paragraph [0023] and fig. 2).
In re claim 10, as applied to claim 1 above, Dewey discloses wherein the transistor gate stack is between a source region and a drain region 160 (see paragraph [0030] and fig. 2).
In re claim 11, as applied to claim 1 above, Dewey discloses wherein the gate dielectric 140 is a high-k dielectric (see paragraph [0027]).
In re claim 12, as applied to claim 1 above, Dewey discloses wherein the gate dielectric 140 is a ferroelectric gate oxide (see paragraph [0027]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, and 8 of copending Application No. 17/702,593 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 6, and 8 of Application No. 17/702,593 discloses a transistor gate stack comprising a semiconductor channel (see claim 1, line 2); an interlayer (IL) (additionally interface layer) over and in direct physical contact with the semiconductor channel (see claim 6, lines 1-2), wherein the IL has a thickness below 3 nm (see claim 8, line 2) and comprises zirconium (see claim 7, line 3); a gate dielectric (hysteretic element) over the IL (see claim 1, line 5); and a gate metal over the gate dielectric (see claim 1, line 5).
With respect to the limitation of wherein the IL has a thickness of 1 nm or less, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness range of the IL during routine experimentation to be in a range of 1 nm or less since it is respectfully submitted that there is no evidence indicating the thickness range of the IL is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Response to Applicant’s Amendment and Arguments
Applicant's arguments filed May 13th, 2025 have been fully considered but they are not persuasive.
With respect to independent claims 1 and 23, Applicant contends that the cited prior art does not disclose an interlayer (IL) over and in direct physical contact with the semiconductor channel.
However, it is respectfully submitted that Applicant’s above argument is not persuasive because Sharma discloses a transistor gate stack, including, inter-alia, a semiconductor channel 102 (see paragraph [0020] and figs. 8A-B); an interlayer (IL) 104 over and in direct physical contact with the semiconductor channel 102 (see paragraph [0023] and figs. 8A-B), wherein the IL 104 has a thickness 112 of (between 1 nm and 3 nm) and comprises zirconium (see paragraph [0029] and figs. 8A-B, note that, Sharma discloses that the IL may include zirconium oxide); a gate dielectric (105,106) over the IL 104; and a gate metal 108 over the gate dielectric (105,106) (see paragraph [0030] and marked-up version of Fig. 8A below).
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Additionally, Dewey discloses a transistor gate stack, including, inter-alia, a semiconductor channel 125 (see paragraph [0023] and fig. 2); an interlayer (IL) 130 over and in direct physical contact with the semiconductor channel 125 (see paragraph [0026] and fig. 2), wherein the IL 130 has a thickness T3 of (about 0.8 nm to 3.8 nm) and comprises zirconium (see paragraph [0026] and fig. 2); a gate dielectric 140 over the IL (see paragraph [0027] and fig. 2); and a gate metal 150 over the gate dielectric 140 (see paragraph [0029] and marked-up version of fig. 2 below).
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For this reason, it is respectfully submitted that the rejection is proper.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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