DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed April 17, 2026. Claims 1, 11-13, 19, and 24 have been amended. No claims have been added. Claims 5-8, and 17 have been canceled. Claims 20-23 stand withdrawn. Currently, claims 1-4, 9-16, 18-19, and 24-25 are pending.
Response to Arguments
Applicant's arguments filed April 17, 2026 with regards to the limitations previously presented in claims 5-8 and now incorporated into amended claim 1 have been fully considered but they are not persuasive.
Applicant asserts that Chang fails to disclose the limitations of claim 5-8 and points to pages 4-6 and 8 of the previous Office Action. However, as outlined on pages 7-9 and 13 of the previous Office Action, Chang was not relied upon to disclose the limitations of claims 5-8. Instead, these limitations were disclosed by secondary references Ha and Lin which were not addressed in Applicant’s response. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant’s arguments with respect to the newly added limitations of claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “self-assembled monolayer between the channel and the gate dielectric” of claim 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-13, 15, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. (US 20210399104 A1) herein after “Chang”.
Regarding claim 11, Figs. 9-10 and 18A of Chang disclose a semiconductor device (Fig. 18A, NFET 200N, ¶ [0011]), comprising:
a sub-fin (Fig. 18A, semiconductor layers 215, ¶ [0026]), wherein the sub-fin (215) comprises a semiconductor material (“The semiconductor layer stack is patterned into a shape of a fin protruding above the substrate 202”, ¶ [0026]), the sub-fin (215) extending through a trench isolation structure (Fig. 18A, isolation features 230, ¶ [0028]);
a channel (Fig. 18A, “the semiconductor layers 215 are also referred to as channel layers 215”, ¶ [0026]) above the sub-fin (215), wherein the channel (215) is physically spaced away from the sub-fin (215);
a first layer (Fig. 10, high-k dielectric layer 284, ¶ [0041]) over the sub-fin (215) between the channel (215) and the sub-fin (215), wherein the first layer (284) is an insulating material (“The high-k dielectric layer 284 includes… high-k dielectric material, such as HfSiO”, ¶ [0041]);
a gate dielectric (Fig. 9, portion high-k dielectric layers 282 surrounding 215, ¶ [0040]) around a perimeter of the channel (215) , and wherein the first layer (284) completely separates the gate dielectric (282) from the trench isolation structure (230);
a gate electrode (Fig. 18A, bulk metal layer 350, ¶ [0052]) surrounding the gate dielectric (282); and
a second layer (Fig. 9, portion high-k dielectric layers 282 over the sub-fin, ¶ [0040]) over the sub-fin (215), wherein the second layer (282) and the gate dielectric (282) comprise the same material, and wherein the second layer (282) is intervening between the first layer (284) and the top of the sub-fin (215) and between the first layer (284) and the trench isolation structure (230).
Regarding claim 12, Figs. 9-10 and 18A of Chang disclose the semiconductor device of claim 11 as applied above, and Chang further discloses wherein the first layer (284) comprises silicon and oxygen (“the high-k dielectric layer 284 includes another hafnium-containing high-k dielectric material, such as HfSiO”, ¶ [0041]).
Regarding claim 13, Figs. 9-10 and 18A of Chang disclose the semiconductor device of claim 11 as applied above, and Chang further discloses wherein the first layer (284) comprises silicon and nitrogen (“the high-k dielectric layer 284 includes another hafnium-containing high-k dielectric material, such as… HfSiON”, ¶ [0041]).
Regarding claim 15, Figs. 9-10 and 18A of Chang disclose the semiconductor device of claim 11 as applied above, and Fig. 18A of Chang further discloses comprising:
a plurality of channels (215) above the sub-fin (215).
Regarding claim 18, Figs. 9-10 and 18A of Chang disclose the semiconductor device of claim 11 as applied above, and Chang further discloses wherein channel (215) is a nanowire or nanosheet (“the channel layers 215 may be cylindrical-shaped (e.g., nanowire), rectangular-shaped (e.g., nanobar), sheet-shaped (e.g., nanosheet), etc.”, ¶ [0027]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210399104 A1) in view of Ha et al. (US 20200013870 A1) herein after “Ha”.
Regarding claim 1, Figs. 9-10 and 18A of Chang disclose a semiconductor device (200N), comprising:
a sub-fin (215), wherein the sub-fin (215) comprises a semiconductor material (“The semiconductor layer stack is patterned into a shape of a fin protruding above the substrate 202”, ¶ [0026]), the sub-fin (215) extending through a trench isolation structure (230);
a channel (215) above the sub-fin (215), wherein the channel (215) is physically detached from the sub-fin (215);
a gate dielectric (282) surrounding a perimeter of the channel (215);
a first layer (284) over a top the sub-fin (215), wherein the first layer (284) comprises a first material composition (“The high-k dielectric layer 284 includes… high-k dielectric material, such as HfSiO”, ¶ [0041]);
a second layer (286) over the first layer (284), wherein the second layer (286) comprises a second material composition that is different than the first material composition (“the high-k dielectric layers 282, 284, and 286 include different materials from each other”, ¶ [0049]), and wherein the first layer (284) completely separates the second layer (286) from the trench isolation structure (230); and
a third layer (282) over the sub-fin (215), wherein the third layer (282) and the gate dielectric (282) comprise the same material, and
wherein the third layer (282) is intervening between the sub-fin (215) and the first layer (284) and between the first layer (284) and the trench isolation layer (230).
Chang fails to disclose the first layer along sides of the sub-fin.
In the similar field of endeavor of semiconductor devices, Fig. 2E of Ha discloses a first layer (Fig. 2E, ferroelectric pattern FE, ¶ [0043]) along sides of the sub-fin (Fig. 2E, second active pattern AP2, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Chang with the first layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Regarding claim 2, Chang and Ha together disclose the semiconductor device of claim 1 as applied above, and Chang further discloses wherein the first layer (284) comprises silicon and oxygen (“The high-k dielectric layer 284 includes… high-k dielectric material, such as HfSiO”, ¶ [0041]).
Regarding claim 3, Chang and Ha together disclose the semiconductor device of claim 1 as applied above, and Chang further discloses wherein the second layer (286) comprises silicon and nitrogen (“the high-k dielectric layer 286 includes… Si.sub.3N.sub.4”, ¶ [0049]).
Regarding claim 4, Chang and Ha together disclose the semiconductor device of claim 1 as applied above, and Fig. 18A of Chang further discloses wherein the channel (215) is a nanosheet or a nanowire (“the channel layers 215 may be cylindrical-shaped (e.g., nanowire), rectangular-shaped (e.g., nanobar), sheet-shaped (e.g., nanosheet), etc.”, ¶ [0027]).
Regarding claim 9, Chang and Ha together disclose the semiconductor device of claim 1 as applied above, and Fig. 18A of Chang further discloses comprising:
a plurality of channels (215) above the sub-fin (215).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210399104 A1) and Ha (US 20200013870 A1) in further view of Hsiao et al. (US 20210050457 A1) herein after “Hsiao”.
Regarding claim 10, Chang and Ha together disclose the semiconductor device of claim 9 as applied above, but the combination fails to disclose wherein a spacing between the plurality of channels has a first distance, and wherein a spacing between the sub-fin and a bottommost channel has a second distance, wherein the second distance is greater than the first distance.
In the similar field of endeavor of gate-all-around structures, Fig. 4 of Hsiao discloses wherein a spacing (Fig. 4, spaces S2′, S3′, S4′, and S5′, ¶ [0029]) between the plurality of channels (Fig. 4, Si nanowires 101B, 102B, 103B, 104B, 105B, ¶ [0028]) has a first distance, and wherein a spacing (Fig. 4, space S1′, ¶ [0029]) between the sub-fin (Fig. 4, material layer 100B, ¶ [0014]) and a bottommost channel (101B) has a second distance (Fig. 4, “space S1′ is greater than any of the spaces S2′, S3′, S4′, and S5′”, ¶ [0029]), wherein the second distance is greater than the first distance.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the channels disclosed by Chang with the spacings as disclosed by Hsiao, to ensure improve scale uniformity (see Hsiao, ¶ [0019]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210399104 A1) further view of Huang et al. (US 20190341317 A1) herein after “Huang”.
Regarding claim 14, Figs. 9-10 and 18A of Chang disclose the semiconductor device of claim 11 as applied above, but Chang fails to disclose a self-assembled monolayer between the channel and the gate dielectric.
In the similar field of endeavor of integrated circuit technologies, Fig. 14 of Huang discloses a self-assembled monolayer (Fig. 14, SAM layer 139, ¶ [0045]) between the channel (Fig. 14, trench 116a, ¶ [0022]) and the gate dielectric (Fig. 14, gate dielectric layer 122, ¶ [0023]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Chang to include the self-assembled monolayer as disclosed by Huang, to adjust the threshold voltage (see Huang, ¶ [0045]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210399104 A1) in view of Hsiao (US 20210050457 A1).
Regarding claim 16, Fig. 18A of Chang discloses the semiconductor device of claim 15 as applied above, but Chang fails to disclose wherein a spacing between channels is a first distance, and a spacing between a bottommost channel and the sub-fin is a second distance, wherein the second distance is greater than the first distance.
In the similar field of endeavor of gate-all-around structures, Fig. 4 of Hsiao discloses wherein a spacing (S2′, S3′, S4′, S5′) between the channels (101B, 102B, 103B, 104B, 105B) is a first distance, and wherein a spacing (S1′) between a bottommost channel (101B) and the sub-fin (100B) is a second distance (Fig. 4, “space S1′ is greater than any of the spaces S2′, S3′, S4′, and S5′”, ¶ [0029]), wherein the second distance is greater than the first distance.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the channels disclosed by Chang with the spacings as disclosed by Hsiao, to ensure improve scale uniformity (see Hsiao, ¶ [0019]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210399104 A1) in view of Hsu et al. (US 20220084830 A1) herein after “Hsu”.
Regarding claim 19, Figs. 9-10 and 18A of Chang disclose the semiconductor device of claim 11 as applied above, but Chang fails to disclose wherein a thickness of the first layer is greater than a thickness of the gate dielectric.
In the similar field of endeavor of GAA devices, Fig. 14 of Hsu discloses wherein a thickness of the first layer (Fig. 14, high-k dielectric layer 282, ¶ [0025]) is greater than a thickness of the gate dielectric (Fig. 14, interfacial layer 280, ¶ [0025]) (“the interfacial layer 280 has a thickness of about 5 Å to about 15 Å”, “the high-k dielectric layer 282 has a thickness of about 1 nm to about 2 nm”, ¶ [0024-0025]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the channels disclosed by Chang with the spacings as disclosed by Hsu, to ensure reliability and allow for subsequent layer formation (see Hsu, ¶ [0024]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210399104 A1) in view of Rachmady et al. (US 20140225065 A1) herein after “Rachmady” and Ha (US 20200013870 A1).
Regarding claim 24, Figs. 9-10 and 18A of Chang disclose a electronic system (“The device 200 is a multi-gate (or multigate) device in the present embodiments, and may be included in a microprocessor, a memory, and/or other IC device”, ¶ [0021]), comprising:
a die coupled to the package substrate (“the device 200 is a portion of an IC chip”, ¶ [0021]), wherein the die comprises:
a sub-fin (215), wherein the sub-fin (215) comprises a semiconductor material the sub-fin (215) extending through a trench isolation structure(230);
a channel (215) above the sub-fin (215), wherein the channel (215) is physically detached from the sub-fin (215);
a gate dielectric (282) surrounding a perimeter of the channel (215);
a first layer (284) over a top of the sub-fin (215), wherein the first layer (284) comprises a first material composition;
a second layer (286) over the first layer (284), wherein the second layer (286) comprises a second material composition that is different than the first material composition, and wherein the first layer (284) completely separates the second layer (286) from the trench isolation structure (230); and
a third layer (282) over the sub-fin (215), wherein the third layer (282) and the gate dielectric (282) comprise the same material, and
wherein the third layer (282) is intervening between the sub-fin (215) and the first layer (284) and between the first layer (284) and the trench isolation layer (230).
Chang fails to explicitly disclose a board;
a package substrate coupled to the board,
the first layer along sides of the sub-fin.
In the similar field of endeavor of gate all-around devices, Fig. 4 of Rachmady discloses a board (Fig. 4, board 402, ¶ [0055]);
a package substrate (“processor 404 of the computing device 400 includes an integrated circuit die packaged”, ¶ [0058]) coupled to the board (402).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Chang with the board as disclosed by Rachmady, to house components (see Rachmady, ¶ [0055]).
Rachmady fails to disclose the first layer along sides of the sub-fin.
In the similar field of endeavor of semiconductor devices, Fig. 2E of Ha discloses a first layer (Fig. 2E, ferroelectric pattern FE, ¶ [0043]) along sides of the sub-fin (Fig. 2E, second active pattern AP2, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Chang with the first layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Regarding claim 25, Chang, Rachmady and Ha together disclose the electronic system of claim 24 as applied above, and Chang further discloses wherein the first layer (284) comprises silicon and oxygen (“the high-k dielectric layer 284 includes another hafnium-containing high-k dielectric material, such as HfSiO”, ¶ [0041]), and wherein the second layer (286) comprises silicon and nitrogen (“the high-k dielectric layer 286 includes… Si.sub.3N.sub.4”, ¶ [0049]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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