DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 5, 2025 has been entered.
Response to Amendment
This Office Action is in response to Applicant's amendments filed October 3, 2025. Claims 1, 11, and 24 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-19, and 24-25 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “self-assembled monolayer between the channel and the gate dielectric” of claim 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20220199796 A1) herein after “Zhang” in view of Ha et al. (US 20220190136 A1) herein after “Ha” and Yu et al. (US 20210305408 A1) herein after “Yu”.
Regarding claim 1, Fig. 13 of Zhang discloses semiconductor device (Fig. 13, semiconductor structure 100, ¶ [0031]), comprising:
a sub-fin (see Annotation 1, Fig. 13 of Zhang, “Fin portions”), wherein the sub-fin (fin portion) comprises a semiconductor material (Fig. 13, “The substrate 10 may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials”, ¶ [0033]), the sub-fin (fin portions) extending through a trench isolation structure (Fig. 13, shallow trench isolation region (hereinafter “STI region”) 22, ¶ [0032]);
a channel (Fig. 13, semiconductor channel material layer 18, ¶ [0037]) above the sub-fin (fin portion), wherein the channel (18) is physically detached from the sub-fin (fin portion);
a first layer (Fig. 13, bottom isolation layer 12, ¶ [0032]) over the sub-fin (fin portion), wherein the first layer (12) comprises a first material composition (Fig. 13, “The bottom isolation layer 12 may be composed of silicon dioxide”, ¶ [0046]); and
a second layer (Fig. 13, gate dielectric 24 over the STI regions 22 and the bottom isolation layer 12, ¶ [0051]) over the first layer (12), wherein the second layer (24) comprises a second material composition that is different than the first material composition (Fig. 13, “the gate dielectric 24 can be a high-k material”, ¶ [0052]).
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Annotation 1, Fig. 13 of Zhang
Zhang discloses that the gate dielectric (24) may be a multilayered structure (see Zhang, ¶ [0052]), but Zhang fails to disclose the first layer is over a top and along sides of the sub-fin,
and wherein the first layer completely separates the second layer from the trench isolation structure.
In the similar field of endeavor of semiconductor devices, Fig. 2E of Ha discloses a first layer (Fig. 2E, ferroelectric pattern FE, ¶ [0043]) over a top and along sides of the sub-fin (Fig. 2E, second active pattern AP2, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the first layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Ha fails to disclose wherein the first layer completely separates the second layer from the trench isolation structure.
In the similar field of endeavor of multigate devices, Fig. 23B of Yu discloses wherein the first layer (Fig. 23B, interfacial layer 280, ¶ [0031]) completely separates the second layer (Fig. 23B, high-k dielectric layer 282, ¶ [0031]) from the trench isolation structure (Fig. 23B, isolation features 230, ¶ [0033]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the first and second layer as disclosed by Yu, as part of the multilayer structure described by Zhang (see Zhang, ¶ [0052]).
Regarding claim 2, Zhang, Ha, and Yu together disclose the semiconductor device of claim 1 as applied above, and Fig. 13 of Zhang further discloses wherein the first layer (12) comprises silicon and oxygen (Fig. 13, “The bottom isolation layer 12 may be composed of silicon dioxide”, ¶ [0046]).
Regarding claim 3, Zhang, Ha, and Yu together disclose the semiconductor device of claim 1 as applied above, and Fig. 13 of Zhang further discloses wherein the second layer (24) comprises silicon and nitrogen (Fig. 13, “the gate dielectric 24 can be a high-k material. Exemplary high-k dielectrics include, but are not limited to… SiN.sub.x”, ¶ [0052]).
Regarding claim 4, Zhang, Ha, and Yu together disclose the semiconductor device of claim 1 as applied above, and Fig. 13 of Zhang further discloses wherein the channel (18) is a nanosheet or a nanowire (Fig. 13, “the semiconductor channel material layers 18 of the nanosheet stack”, ¶ [0072]).
Regarding claim 5, Zhang, Ha, and Yu together disclose the semiconductor device of claim 1 as applied above, and Fig. 13 of Zhang further discloses comprising:
a gate dielectric (Fig. 13, gate dielectric 24 surrounding the semiconductor channel material layers 18, ¶ [0051]) surrounding a perimeter of the channel (18) (Fig. 13, “a gate dielectric 24 is formed in each cavity and surrounding suspended portions of the semiconductor channel material layers 18”, ¶ [0051]) (Fig. 13 of Zhang shows that the gate dielectric layer 24 covers both the sub-fin and the channel layers 18 in the same way that Fig. 4 of the instant application shows the second layer 431 and the gate dielectric layer 421 covering the sub-fin 405 and the channel regions 410, respectively. Therefore, layer 24 is being treated as both the second layer and the gate dielectric layer).
Regarding claim 6, Zhang, Ha, and Yu together disclose the semiconductor device of claim 5 as applied above, and further discloses that the gate dielectric (24) may be a multilayered structure (see Zhang, ¶ [0052]), but Zhang and Yu fail to explicitly disclose comprising:
a third layer over the sub-fin, wherein the third layer and the gate dielectric comprise the same material.
In the similar field of endeavor of integrated circuit technologies, Fig. 2E of Ha discloses a third layer (Fig. 2E, interface layer IL over AP2, ¶ [0042]) over the sub-fin (AP2), wherein the third layer (IL) and the gate dielectric (Fig. 2E, interface layer IL over channel patterns CH2, ¶ [0042]) comprise the same material (Fig. 2E of Ha shows that the interface layer IL covers both the sub-fin AP2 and the channel layers CH2 in the same way that Fig. 1 of the instant application shows the third layer 131 and the gate dielectric layer 121 covering the sub-fin 105 and the channel regions 110, respectively).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the third layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Regarding claim 8, Zhang, Ha, and Yu together disclose the semiconductor device of claim 6 as applied above, but Zhang and Yu fail to disclose wherein the third layer is between the sub-fin and the first layer.
In the similar field of endeavor of semiconductor devices, Fig. 2E of Ha discloses wherein the third layer (IL) is between the sub-fin (AP2) and the first layer (FE).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the third layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Regarding claim 9, Zhang, Ha, and Yu together disclose the semiconductor device of claim 1 as applied above, and Fig. 13 of Zhang further discloses comprising:
a plurality of channels (18) above the sub-fin (fin portion) (Fig. 13, “the nanosheet stack 20 includes… three layers of semiconductor channel material layer 18”, ¶ [0037]).
Regarding claim 10, Zhang, Ha, and Yu together disclose the semiconductor device of claim 9 as applied above, and Fig. 13 of Zhang further discloses wherein a spacing between the plurality of channels (18) has a first distance (see Annotation 1, Fig. 13 of Zhang, “S1”), and wherein a spacing between the sub-fin (fin portion) and a bottommost channel (18) has a second distance (see Annotation 1, Fig. 13 of Zhang, “S2”), wherein the second distance (S2) is greater than the first distance (S1).
Regarding claim 11, Fig. 13 of Zhang discloses a semiconductor device (100), comprising:
a sub-fin (fin portion), wherein the sub-fin (fin portion) comprises a semiconductor material (Fig. 13, “The substrate 10 may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials”, ¶ [0033]) the sub-fin (fin portion) extending through a trench isolation structure (22);
a channel (18) above the sub-fin (fin portion), wherein the channel (18) is physically spaced away from the sub-fin (fin portion);
a layer (12) over the sub-fin (fin portion), the layer (12) between the channel (18) and the sub-fin (fin portion), wherein the layer (12) is an insulating material (Fig. 13, “The bottom isolation layer 12 may be composed of silicon dioxide”, ¶ [0046]);
a gate dielectric (24) around a perimeter of the channel (18); and
a gate electrode (Fig. 13, work function metal 40, ¶ [0086]) surrounding the gate dielectric (24).
Zhang discloses that the gate dielectric (24) may be a multilayered structure (see Zhang, ¶ [0052]), but Zhang fails to disclose the first layer is over a top and along sides of the sub-fin,
and wherein the layer completely separates the gate dielectric from the trench isolation structure
In the similar field of endeavor of semiconductor devices, Fig. 2E of Ha discloses a first layer (Fig. 2E, ferroelectric pattern FE, ¶ [0043]) over a top and along sides of the sub-fin (Fig. 2E, second active pattern AP2, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the first layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Ha fails to disclose wherein the layer completely separates the gate dielectric from the trench isolation structure.
In the similar field of endeavor of multigate devices, Fig. 23B of Yu discloses wherein the layer (280) completely separates the gate dielectric (282) from the trench isolation structure (230).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the first and second layer as disclosed by Yu, as part of the multilayer structure described by Zhang (see Zhang, ¶ [0052]).
Regarding claim 12, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Zhang further discloses wherein the layer (12) comprises silicon and oxygen (Fig. 13, “The bottom isolation layer 12 may be composed of silicon dioxide”, ¶ [0046]).
Regarding claim 13, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Zhang further discloses that the layer (12) comprises a low-k dielectric material (see Zhang, ¶ [0046]), but Zhang and Ha fail to explicitly disclose wherein the layer comprises silicon and nitrogen.
In the similar field of endeavor of multigate devices, Fig. 23B of Yu discloses wherein the layer (280) comprises silicon and nitrogen (Fig. 23B, “Interfacial layer 280 includes a dielectric material, such as… SiON”, ¶ [0031]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the layer as disclosed by Yu, to isolate the gate structures (see Yu, ¶ [0044]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 15, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Zhang further discloses comprising:
a plurality of channels (18) above the sub-fin (fin portion) (Fig. 13, “the nanosheet stack 20 includes… three layers of semiconductor channel material layer 18”, ¶ [0037]).
Regarding claim 16, Zhang, Ha, and Yu together disclose the semiconductor device of claim 15 as applied above, and Fig. 13 of Zhang further discloses wherein a spacing between channels (18) is a first distance (see Annotation 1, Fig. 13 of Zhang, “S1”), and a spacing between a bottommost channel (18) and the sub-fin (fin portion) is a second distance (see Annotation 1, Fig. 13 of Zhang, “S2”), wherein the second distance (S2) is greater than the first distance (S1).
Regarding claim 17, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Zhang further discloses comprising:
a second layer (24) over the layer (12), wherein the second layer (24) and the gate dielectric (24) comprise the same material (Fig. 13, “The gate dielectric 24 further covers the STI regions 22 and the bottom isolation layer 12”, “and surrounding suspended portions of the semiconductor channel material layers 18”, ¶ [0051]).
Regarding claim 18, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Zhang further discloses wherein channel (18) is a nanowire or nanosheet (Fig. 13, “the nanosheet stack 20 includes… three layers of semiconductor channel material layer 18”, ¶ [0037]).
Regarding claim 19, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Zhang further discloses wherein a thickness (see Annotation 1, Fig. 13 of Zhang, “T1”) of the layer (12) is greater than a thickness (see Annotation 1, Fig. 13 of Zhang, “T2”) of the gate dielectric (24).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20220199796 A1), Ha (US 20220190136 A1) and Yu (US 20210305408 A1) in further view of Lin et al. (US 20240397694 A1) herein after “Lin”.
Regarding claim 7, Zhang, Ha, and Yu together disclose the semiconductor device of claim 6 as applied above, Fig. 13 of Zhang discloses that the gate dielectric (24) may be a multilayered structure (see Zhang, ¶ [0052]), but the combination fails to explicitly disclose wherein the third layer is over the second layer.
In the similar field of endeavor of integrated circuit technologies, Fig. 20A of Lin discloses wherein the third layer (604) is over the second layer (Fig. 20A, interfacial layer 602, ¶ [0034]) (Fig. 20A, “the gate dielectric layer 604 disposed over the interfacial layer 602”, ¶ [0050]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang with the third layer over the second layer as disclosed by Lin, as part of the multilayer structure described by Zhang (see Zhang, ¶ [0052]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20220199796 A1), Ha (US 20220190136 A1) and Yu (US 20210305408 A1) in further view of Huang et al. (US 20190341317 A1) herein after “Huang”.
Regarding claim 14, Zhang, Ha, and Yu together disclose the semiconductor device of claim 11 as applied above, but the combination fails to disclose a self-assembled monolayer between the channel and the gate dielectric.
In the similar field of endeavor of integrated circuit technologies, Fig. 14 of Huang discloses a self-assembled monolayer (Fig. 14, SAM layer 139, ¶ [0045]) between the channel (Fig. 14, trench 116a, ¶ [0022]) and the gate dielectric (Fig. 14, gate dielectric layer 122, ¶ [0023]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Zhang to include the self-assembled monolayer as disclosed by Huang, to adjust the threshold voltage (see Huang, ¶ [0045]).
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (US 20140225065 A1) herein after “Rachmady” in view of Ha (US 20220190136 A1).
Regarding claim 24, Figs. 1C and 4 of Rachmady disclose an electronic system (Fig. 4, computing device 400, ¶ [0055]), comprising:
a board (Fig. 4, board 402, ¶ [0055]);
a package substrate (“processor 404 of the computing device 400 includes an integrated circuit die packaged”, ¶ [0058]) coupled to the board (402); and
a die coupled to the package substrate (“the integrated circuit die of the processor includes one or more devices, such as non-planar gate all-around transistor devices, that are formed in accordance with implementations of the invention”, ¶ [0058]), wherein the die comprises:
a sub-fin (Fig. 1C, fin portion of substrate 102, ¶ [0014]), wherein the sub-fin (fin) comprises a semiconductor material (Fig. 1C, “substrate 102 is silicon germanium”, ¶ [0015]) the sub-fin (fin) extending through a trench isolation structure (Fig. 1C, shallow trench isolation layer 105, ¶ [0017]);
a channel (Fig. 1C, channel nanowires 110, ¶ [0014]) above the sub-fin (fin), wherein the channel (110) is physically detached from the sub-fin (fin);
a first layer (Fig. 1C, bottom gate isolation 114, ¶ [0018]) over the sub-fin (fin); and
a second layer (Fig. 1C, gate dielectric layer 116, ¶ [0014]) over the first layer (114), wherein the second layer (“Gate dielectric layer 116 may be any well-known gate dielectric layer, such as, but not limited to… SiN”, ¶ [0029]) is different than the first layer (“bottom gate isolation 114 is composed of a silicon oxide layer”, ¶ [0018]).
Rachmady fails to disclose the first layer is over a top and along sides of the sub-fin,
and wherein the first layer completely separates the second layer from the trench isolation structure.
In the similar field of endeavor of semiconductor devices, Fig. 2E of Ha discloses a first layer (Fig. 2E, ferroelectric pattern FE, ¶ [0043]) over a top and along sides of the sub-fin (Fig. 2E, second active pattern AP2, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Rachmady with the first layer as disclosed by Ha, to change the operating voltage (see Ha, ¶ [0044]).
Ha fails to disclose wherein the first layer completely separates the second layer from the trench isolation structure.
In the similar field of endeavor of multigate devices, Fig. 23B of Yu discloses wherein the first layer (280) completely separates the second layer (282) from the trench isolation structure (230).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure disclosed by Rachmady with the first and second layer as disclosed by Yu, to isolate the gate structures (see Yu, ¶ [0044]).
Regarding claim 25, Rachmady, Ha, and Yu together disclose the electronic system of claim 24 as applied above, and Fig. 1C of Rachmady further discloses wherein the first layer (114) comprises silicon and oxygen (Fig. 1C, “bottom gate isolation 114 is composed of a silicon oxide layer”, ¶ [0018]), and wherein the second layer (116) comprises silicon and nitrogen (Fig. 1C, “Gate dielectric layer 116 may be any well-known gate dielectric layer, such as, but not limited to… SiN”, ¶ [0029]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893