DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Status of claims
Claims 1-4, 9-10, 12-17 and 23-25 are pending in this application. Claims 5, 11 and 18-22 were previously withdrawn as set forth in the office action mailed 3/5/2025. Claims 6-8 were cancelled as stated by the applicant in the reply filed 12/29/2025.
Drawings
Prior objection to drawing is withdrawn in view of cancellation of claim 6.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung et al. (US 2015/0255427 A1, newly cited).
Re Claim 1, Sung teaches an electronic package, comprising:
a package substrate (100, Fig. 1, para [0031]) with a stepped top surface (see Fig. 1);
a first die (213, Fig. 1, paras [0031] and [0039]) on a first plateau of the stepped top surface (1st plateau of 100);
a second die (230, Fig. 1, para [0031]) on a second plateau of the stepped top surface (2nd plateau of 100), wherein the second die (230) extends over the first die (213, see Fig. 1), wherein the first die (213) is partially outside of a footprint of the second die (230, see Fig. 1), and wherein the first die has a top surface below the second plateau (top surface of 213 is below the 2nd plateau of 100, see Fig. 1); and
a third die (250, Fig. 1, para [0031]) on a third plateau of the stepped top surface (3rd plateau of 100), wherein the third die (250) extends over the second die (230, Fig. 1), wherein the second die (230) is partially outside of a footprint of the third die (250, see Fig. 1), and wherein the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1).
Re Claim 3, Sung teaches the electronic package of claim 1, wherein the third die (250) is communicatively coupled (para [0047]) to the second die (230), and wherein the second die (230) is communicatively coupled (para [0047]) to the first die (213).
Rejection 2:
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-4, 9, 12, 16-17, 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 2020/0219815 A1, of record), and further in view of Ho et al. (US 2017/0047308 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited).
Re Claim 1, Elsherbini teaches an electronic package (Fig. 7), comprising:
a package substrate (102, Fig. 7, para [0062]) with a stepped top surface (Fig. 7);
a first die (114-1, Fig. 7, para [0062]) on a first plateau of the stepped top surface (marked “P1” in annotated Fig. 7 below);
a second die (114-6, Fig. 7, para [0062]) on a second plateau of the stepped top surface (marked “P2” in annotated Fig. 7 below), wherein the second die (114-6) extends over the first die (114-1, see Fig. 7), wherein the first die (114-1) is partially outside of a footprint of the second die (114-6, see Fig. 7); and
a third die (114-8, Fig. 7, para [0062]) on a third plateau of the stepped top surface (marked “P3” in annotated Fig. 7 below), wherein the third die (114-8) extends over the second die (114-6, see Fig. 7), wherein the second die (114-6) is partially outside of a footprint of the third die (114-8, see Fig. 7).
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Elsherbini does not disclose that the first die has a top surface below the second plateau and that the second die has a top surface below the third plateau. Elsherbini discloses that the first die (114-1, Fig. 7) has a top surface above the second plateau (“P2”, Fig. 7) and that the second die (114-6, Fig. 7) has a top surface above the third plateau (“P3”, Fig. 7).
However, Examiner notes that the relative position of the top surface of the die and the corresponding plateau is a design choice which is well-known in this field of art. For example, prior art Ho shows that the top surface of the first die (104, Fig. 3) can be approximately at the same level as the second plateau (top surface of 120, Fig. 3), and that the top surface of the second die (154, Fig. 3) can be approximately at the same level as the third plateau (top surface of 142, Fig. 3). Similarly, related art Sung teaches that the first die has a top surface below the second plateau (top surface of die 213 is below the 2nd plateau of 100, see Fig. 1) and the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1), as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to realize that there are only three predictable outcomes depending on the design choice of the device where the top surface of the die can be either above (as shown by Elsherbini), nearly at the same level (as shown by Ho), or below (as shown by Sung) the top surface of the corresponding plateau. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Additionally, the relative position of the top surface of the die and the corresponding plateau will not hinder the performance of the device, and the device will not perform any differently if the top surface of the die is either above (as shown by Elsherbini), nearly at the same level (as shown by Ho), or below (as shown by Sung) the top surface of the corresponding plateau. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04-IV-A).
Re Claim 3, Elsherbini modified by Ho and Sung teaches the electronic package of claim 1, wherein the third die (114-8, Elsherbini) is communicatively coupled (electrically coupled, Fig. 7) to the second die (114-6, Fig. 7, para [0062]), and wherein the second die (114-6) is communicatively coupled (electrically coupled, Fig. 7) to the first die (114-1, Fig. 7, para [0062]).
Re Claim 4, Elsherbini modified by Ho and Sung teaches the electronic package of claim 1, wherein the first die (114-1, Elsherbini) is coupled to the package substrate (102) by a solder (150-1, Fig. 7, para [0048]).
Re Claim 9, Elsherbini modified by Ho and Sung teaches the electronic package of claim 1, wherein a thickness of the second die (114-6, Elsherbini) is greater than one routing layer in the electronic package (thickness of one routing layer is marked “d1” in annotated Fig. 7 above, and the thickness of 114-6 is greater than “d1”).
Re Claim 12, Elsherbini teaches an electronic system, comprising:
a package substrate (102, Fig. 7, para [0062]), wherein the package substrate (102) comprises a bottom surface (bottom surface of 102) and a stepped top surface (see Fig. 7);
a first die (114-1, Fig. 7, para [0062]) adjacent to the package substrate (102, Fig. 7);
a second die (114-6, Fig. 7, para [0062]) on a first plateau (marked “P2” in annotated Fig. 7 above) of the stepped top surface of the package substrate (102), wherein the second die (114-6) extends over the first die (114-1), wherein the first die (114-1) is partially outside of a footprint of the second die (114-6, see Fig. 7); and
a third die (114-8, Fig. 7, para [0062]) on a second plateau (marked “P3” in annotated Fig. 7 above) of the stepped top surface of the package substrate (102), wherein the third die (114-8) extends over the second die (114-6, see Fig. 7), wherein the second die (114-6) is partially outside of a footprint of the third die (114-8, see Fig. 7).
Elsherbini does not disclose a board coupled to the package substrate in Fig. 7. However, in another embodiment in Fig. 1, Elsherbini discloses that the package substrate (102) is electrically coupled to a circuit board (133, Fig. 1, para [0032]). The embodiment in Fig. 1 also discloses that the first die (114-1) is also electrically coupled to the circuit board (133). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to electrically couple a circuit board to the package substrate of the embodiment in Fig. 7 as shown in the embodiment of Fig. 1 of Elsherbini. The circuit board provides a physical platform for mounting and connecting electronic components, enabling electronic devices and packages to perform their specific functions like computing, communication, and data transfer.
Elsherbini does not disclose that the first die has a top surface below the second plateau and that the second die has a top surface below the third plateau. Elsherbini discloses that the first die (114-1, Fig. 7) has a top surface above the second plateau (“P2”, Fig. 7) and that the second die (114-6, Fig. 7) has a top surface above the third plateau (“P3”, Fig. 7).
However, Examiner notes that the relative position of the top surface of the die and the corresponding plateau is a design choice which is well-known in this field of art. For example, prior art Ho shows that the top surface of the first die (104, Fig. 3) can be approximately at the same level as the second plateau (top surface of 120, Fig. 3), and that the top surface of the second die (154, Fig. 3) can be approximately at the same level as the third plateau (top surface of 142, Fig. 3). Similarly, related art Sung teaches that the first die has a top surface below the second plateau (top surface of die 213 is below the 2nd plateau of 100, see Fig. 1) and the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1), as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to realize that there are only three predictable outcomes depending on the design choice of the device where the top surface of the die can be either above (as shown by Elsherbini), nearly at the same level (as shown by Ho), or below (as shown by Sung) the top surface of the corresponding plateau. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Additionally, the relative position of the top surface of the die and the corresponding plateau will not hinder the performance of the device, and the device will not perform any differently if the top surface of the die is either above (as shown by Elsherbini), nearly at the same level (as shown by Ho), or below (as shown by Sung) the top surface of the corresponding plateau. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04-IV-A).
Re Claim 16, Elsherbini modified by Ho and Sung teaches the electronic system of claim 12, wherein the third die (114-8, Elsherbini) is communicatively coupled (electrically coupled, Fig. 7) to the second die (114-6, Fig. 7, para [0062]), and wherein the second die (114-6) is communicatively coupled (electrically coupled, Fig. 7) to the first die (114-1, Fig. 7, para [0062]).
Re Claim 17, Elsherbini modified by Ho and Sung teaches the electronic system of claim 12, wherein a thickness of the second die (114-6, Elsherbini) is greater than one routing layer in the package substrate (thickness of one routing layer is marked “d1” in annotated Fig. 7 above, and the thickness of 114-6 is greater than “d1”).
Re Claim 23, Elsherbini teaches an electronic system, comprising:
an electronic package (100, Fig. 7, para [0062]), wherein the electronic package comprises:
a package substrate (102, Fig. 7, para [0062]) with a stepped top surface (see Fig. 7);
a first die (114-1, Fig. 7, para [0062]) on a first plateau of the stepped top surface (marked “P1” in annotated Fig. 7 above);
a second die (114-6, Fig. 7, para [0062]) on a second plateau of the stepped top surface (marked “P2” in annotated Fig. 7 above), wherein the second die (114-6) extends over the first die (114-1, see Fig. 7), and wherein the first die (114-1) is partially outside of a footprint of the second die (114-6, see Fig. 7); and
a third die (114-8, Fig. 7, para [0062]) on a third plateau of the stepped top surface (marked “P3” in annotated Fig. 7 above), wherein the third die (114-8) extends over the second die (114-6, see Fig. 7), and wherein the second die (114-6) is partially outside of a footprint of the third die (114-8, see Fig. 7).
Elsherbini does not disclose a board coupled to the package substrate in Fig. 7. However, in another embodiment in Fig. 1, Elsherbini discloses that the package substrate (102) is electrically coupled to a circuit board (133, Fig. 1, para [0032]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to electrically couple a circuit board to the package substrate of the embodiment in Fig. 7 as shown in the embodiment of Fig. 1 of Elsherbini. The circuit board provides a physical platform for mounting and connecting electronic components, enabling electronic devices and packages to perform their specific functions like computing, communication, and data transfer.
Elsherbini does not disclose that the first die has a top surface below the second plateau and that the second die has a top surface below the third plateau. Elsherbini discloses that the first die (114-1, Fig. 7) has a top surface above the second plateau (“P2”, Fig. 7) and that the second die (114-6, Fig. 7) has a top surface above the third plateau (“P3”, Fig. 7).
However, Examiner notes that the relative position of the top surface of the die and the corresponding plateau is a design choice which is well-known in this field of art. For example, prior art Ho shows that the top surface of the first die (104, Fig. 3) can be approximately at the same level as the second plateau (top surface of 120, Fig. 3), and that the top surface of the second die (154, Fig. 3) can be approximately at the same level as the third plateau (top surface of 142, Fig. 3). Similarly, related art Sung teaches that the first die has a top surface below the second plateau (top surface of die 213 is below the 2nd plateau of 100, see Fig. 1) and the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1), as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to realize that there are only three predictable outcomes depending on the design choice of the device where the top surface of the die can be either above (as shown by Elsherbini), nearly at the same level (as shown by Ho), or below (as shown by Sung) the top surface of the corresponding plateau. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Additionally, the relative position of the top surface of the die and the corresponding plateau will not hinder the performance of the device, and the device will not perform any differently if the top surface of the die is either above (as shown by Elsherbini), nearly at the same level (as shown by Ho), or below (as shown by Sung) the top surface of the corresponding plateau. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04-IV-A).
Re Claim 25, Elsherbini modified by Ho and Sung teaches the electronic system of claim 23, wherein a thickness of the second die (114-6, Elsherbini) is greater than one routing layer in the electronic package (thickness of one routing layer is marked “d1” in annotated Fig. 7 above, and the thickness of 114-6 is greater than “d1”).
Rejection 3:
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record), and further in view of Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited).
Re Claim 1, Chang Chien teaches an electronic package, comprising:
a package substrate (210+220+230, Fig. 1, para [0017]) with a stepped top surface (see Fig. 1);
a first die (130, Fig. 1, para [0016]) on a first plateau of the stepped top surface (230a, Fig. 1, para [0019]);
a second die (120, Fig. 1, para [0016]) on a second plateau of the stepped top surface (220a, Fig. 1, para [0019]), wherein the second die (120) extends over the first die (130, see Fig. 1); and wherein the first die (130) is partially outside of a footprint of the second die (120, see Fig. 1);
a third die (110, Fig. 1, para [0016]) on a third plateau of the stepped top surface (210a, Fig. 1, para [0019]), wherein the third die (110) extends over the second die (120, see Fig. 1), and wherein the second die (120) is partially outside of a footprint of the third die (110, see Fig. 1).
Chang Chien does not explicitly disclose that the first die has a top surface below the second plateau and that the second die has a top surface below the third plateau. Chang Chien discloses that the first die (130, Fig. 1) has a top surface that is approximately at the same level as the second plateau (220a, Fig. 1) and that the second die (120, Fig. 1) has a top surface that is approximately at the same level as the third plateau (210a, Fig. 1).
However, Examiner notes that the relative position of the top surface of the die and the corresponding plateau is a design choice which is well-known in this field of art. For example, prior art Elsherbini shows that the first die (114-1, Fig. 7) has a top surface above the second plateau (Fig. 7) and that the second die (114-6, Fig. 7) has a top surface above the third plateau (Fig. 7). Similarly, related art Sung teaches that the first die has a top surface below the second plateau (top surface of die 213 is below the 2nd plateau of 100, see Fig. 1) and the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1), as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to realize that there are only three predictable outcomes depending on the design choice of the device where the top surface of the die can be either above (as shown by Elsherbini), nearly at the same level (as shown by Chang Chien), or below (as shown by Sung) the top surface of the corresponding plateau. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Additionally, the relative position of the top surface of the die and the corresponding plateau will not hinder the performance of the device, and the device will not perform any differently if the top surface of the die is either above (as shown by Elsherbini), nearly at the same level (as shown by Chang Chien), or below (as shown by Sung) the corresponding plateau. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04-IV-A).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record), Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited), as applied to claim 1 above and further in view of Yu et al. (US 2019/0295912 A1, of record).
Re Claim 2, Chang Chien modified by Elsherbini and Sung teaches the electronic package of claim 1, wherein the first die (130, Fig. 1, Chang Chien) is a photonics integrated circuit, the second die (120) is an electrical integrated circuit (120 can be a CPU chip, para [0016]), and the third die (110) is a logic die (110 can be a logic chip, para [0016], Chang Chien).
Chang Chien does not explicitly disclose that the first die (130) is a photonics die but does disclose that various types of semiconductor chips may be implemented according to actual need (para [0016]), for example CPU or GPU chip, logic chip or memory chip (para [0016]).
Related art from Yu teaches that a semiconductor die (101, para [0015], Fig. 1) can be designed for a desired functionality, such as being a system-on-chip, a graphic die, a MEMS dies, a sensor die, a photonic die, a memory die, other logic dies, combinations of these, or the like (para [0015]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to have the chip 130 of Chang Chien to be a photonic chip as disclosed by Yu, as the semiconductor chip can be designed for a desired functionality (para [0015], Yu).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record), Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited), as applied to claim 1 above and further in view of Thacker et al. (US 2016/0216445 A1, of record).
Re Claim 10, Chang Chien modified by Elsherbini and Sung teaches the electronic package of claim 1, but does not disclose an optical fiber coupled to the first die (130. Fig. 1, Chang Chien).
However, in the related semiconductor field of art, Thacker teaches an optical fiber receptacle (134-1, Fig. 1, para [0036]) connected to the integrated circuit (126-1, Fig. 1, para [0036]) to create a packaged opto-electronic module (para [0036]) which will provide high band-width optical communication in conjunction with high-performance electrical circuits (para [0032]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to couple the optical fiber as disclosed by Thacker to the first die of Chang Chien, to create a packaged opto-electronic module (para [0036], Thacker) which will provide high band-width optical communication in conjunction with high-performance electrical circuits (para [0032], Thacker).
Claim 12, 14 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record) and further in view of Thacker et al. (US 2016/0216445 A1, of record), Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited).
Re Claim 12, Chang Chien teaches an electronic system (Fig. 1), comprising:
a package substrate (210+220+230, Fig. 1, para [0017]) comprises a bottom surface (200b, Fig. 1, para [0021]) and a stepped top surface (see Fig. 1);
a first die (130, Fig. 1, para [0016]) adjacent to the package substrate (210+220+230, see Fig. 1);
a second die (120, Fig. 1, para [0016]) on a first plateau of the stepped top surface of the package substrate (220a, Fig. 1, para [0019]), wherein the second die (120) extends over the first die (130, see Fig. 1), and wherein the first die (130) is partially outside of a footprint of the second die (120, see Fig. 1); and
a third die (110, Fig. 1, para [0016]) on a second plateau of the stepped top surface of the package substrate (210a, Fig. 1, para [0019]), wherein the third die (110) extends over the second die (120, see Fig. 1), and wherein the second die (120) is partially outside of a footprint of the third die (110, see Fig. 1).
Chang Chien does not disclose the following:
a board;
a package substrate (210+220+230) coupled to the board,
a first die (130) coupled to the board
However, Chang Chien does teach bumps 310a/310b/310c/310d/310e (Fig. 1, para [0028]), which will facilitate electrical connection to an external device like a PCB. Therefore, one of ordinary skill in the art would look into related arts to find how a PCB is connected to the electronic package of Chang Chien.
Related art Thacker teaches a PCB (142, Fig. 1, para [0040]) connected to a chip package, which may provide backplane with power, ground, control, monitoring (para [0040]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to add the PCB as disclosed by Thacker to the electronic package of Chang Chien, since the PCB may provide backplane with power, ground, control, monitoring (para [0040], Thacker).
Chang Chien modified by Thacker discloses:
a board (142, Thacker);
a package substrate (210+220+230, Chang Chien) coupled to the board (142, Thacker);
a first die (130, Chang Chien) coupled (see Fig. 1, para [0028], Chang Chien) to the board (142, Thacker).
Chang Chien also does not explicitly disclose that the first die has a top surface below the second plateau and that the second die has a top surface below the third plateau. Chang Chien discloses that the first die (130, Fig. 1) has a top surface that is approximately at the same level as the second plateau (220a, Fig. 1) and that the second die (120, Fig. 1) has a top surface that is approximately at the same level as the third plateau (210a, Fig. 1).
However, Examiner notes that the relative position of the top surface of the die and the corresponding plateau is a design choice which is well-known in this field of art. For example, prior art Elsherbini shows that the first die (114-1, Fig. 7) has a top surface above the second plateau (Fig. 7) and that the second die (114-6, Fig. 7) has a top surface above the third plateau (Fig. 7). Similarly, related art Sung teaches that the first die has a top surface below the second plateau (top surface of die 213 is below the 2nd plateau of 100, see Fig. 1) and the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1), as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to realize that there are only three predictable outcomes depending on the design choice of the device where the top surface of the die can be either above (as shown by Elsherbini), nearly at the same level (as shown by Chang Chien), or below (as shown by Sung) the top surface of the corresponding plateau. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Additionally, the relative position of the top surface of the die and the corresponding plateau will not hinder the performance of the device, and the device will not perform any differently if the top surface of the die is either above (as shown by Elsherbini), nearly at the same level (as shown by Chang Chien), or below (as shown by Sung) the corresponding plateau. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04-IV-A).
Re Claim 14, Chang Chien modified by Thacker, Elsherbini and Sung teaches the electronic system of claim 12, but does not disclose an optical fiber coupled to the first die (130, Fig. 1, Chang Chien).
However, Thacker also teaches an optical fiber receptacle (134-1, Fig. 1, para [0036]) connected to the integrated circuit (126-1, Fig. 1, para [0036]) to create a packaged opto-electronic module (para [0036]) which will provide high band-width optical communication in conjunction with high-performance electrical circuits (para [0032]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to couple the optical fiber as disclosed by Thacker to the first die of Chang Chien, to create a packaged opto-electronic module (para [0036], Thacker) which will provide high band-width optical communication in conjunction with high-performance electrical circuits (para [0032], Thacker).
Re Claim 23, Chang Chien teaches an electronic system, comprising:
an electronic package (Fig. 1) comprises:
a package substrate (210+220+230, Fig. 1, para [0017]) with a stepped top surface (see Fig. 1);
a first die (130, Fig. 1, para [0016]) on a first plateau of the stepped top surface (230a, Fig. 1, para [0019]);
a second die (120, Fig. 1, para [0016]) on a second plateau of the stepped top surface (220a, Fig. 1, para [0019]), wherein the second die (120) extends over the first die (130, see Fig. 1) and wherein the first die (130) is partially outside of a footprint of the second die (120, see Fig. 1); and
a third die (110, Fig. 1, para [0016]) on a third plateau of the stepped top surface (210a, Fig. 1, para [0019]), wherein the third die (110) extends over the second die (120, see Fig. 1), and wherein the second die (120) is partially outside of a footprint of the third die (110, see Fig. 1).
Chang Chien does not disclose the following:
a board; and
an electronic package coupled to the board.
However, Chang Chien does teach bumps 310a/310b/310c/310d/310e (Fig. 1, para [0028]), which will facilitate electrical connection to an external device like a PCB. Therefore, one of ordinary skill in the art would look into related arts to find how a PCB is connected to the electronic package of Chang Chien.
Related art Thacker teaches a PCB (142, Fig. 1, para [0040]) connected to a chip package, which may provide backplane with power, ground, control, monitoring (para [0040]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to couple the PCB as disclosed by Thacker to the electronic package of Chang Chien, since the PCB may provide backplane with power, ground, control or monitoring (para [0040], Thacker).
Chang Chien also does not explicitly disclose that the first die has a top surface below the second plateau and that the second die has a top surface below the third plateau. Chang Chien discloses that the first die (130, Fig. 1) has a top surface that is approximately at the same level as the second plateau (220a, Fig. 1) and that the second die (120, Fig. 1) has a top surface that is approximately at the same level as the third plateau (210a, Fig. 1).
However, Examiner notes that the relative position of the top surface of the die and the corresponding plateau is a design choice which is well-known in this field of art. For example, prior art Elsherbini shows that the first die (114-1, Fig. 7) has a top surface above the second plateau (Fig. 7) and that the second die (114-6, Fig. 7) has a top surface above the third plateau (Fig. 7). Similarly, related art Sung teaches that the first die has a top surface below the second plateau (top surface of die 213 is below the 2nd plateau of 100, see Fig. 1) and the second die has a top surface below the third plateau (top surface of 230 is below the 3rd plateau of 100, see Fig. 1), as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to realize that there are only three predictable outcomes depending on the design choice of the device where the top surface of the die can be either above (as shown by Elsherbini), nearly at the same level (as shown by Chang Chien), or below (as shown by Sung) the top surface of the corresponding plateau. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Additionally, the relative position of the top surface of the die and the corresponding plateau will not hinder the performance of the device, and the device will not perform any differently if the top surface of the die is either above (as shown by Elsherbini), nearly at the same level (as shown by Chang Chien), or below (as shown by Sung) the corresponding plateau. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04-IV-A).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record), Thacker et al. (US 2016/0216445 A1, of record), Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited), as applied to claim 12 above, and further in view of Yu et al. (US 2019/0295912 A1, of record).
Re Claim 13, Chang Chien modified by Thacker, Elsherbini and Sung teaches the electronic package of claim 12, wherein the first die (130, Chang Chien) is a photonics integrated circuit, the second die (120, Chang Chien) is an electrical integrated circuit (120 can be a CPU chip, para [0016], Chang Chien), and the third die (110, Chang Chien) is a logic die (110 can be a logic chip, para [0016], Chang Chien).
Chang Chien does not explicitly disclose that the first die (130) is a photonics die but does disclose that various types of semiconductor chips may be implemented according to actual need (para [0016]), for example CPU or GPU chip, logic chip or memory chip (para [0016]).
Related art from Yu teaches that a semiconductor die (101, para [0015], Fig. 1) can be designed for a desired functionality, such as being a system-on-chip, a graphic die, a MEMS dies, a sensor die, a photonic die, a memory die, other logic dies, combinations of these, or the like (para [0015]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to have the chip 130 of Chang Chien to be a photonic chip as disclosed by Yu, as the semiconductor chip can be designed for a desired functionality (para [0015], Yu).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record), Thacker et al. (US 2016/0216445 A1, of record), Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited), as applied to claim 12 above, and further in view of Canali et al. (US 2018/0045885 A1, of record) and Eid et al. (US 2020/0027812 A1, of record).
Re Claim 15, Chang Chien modified by Thacker, Elsherbini and Sung teaches the electronic system of claim 12, but does not disclose that the package substrate (210+220+230, Chang Chien) comprises a core.
However, in a related semiconductor field of art, Canali teaches a core (111, Fig. 3, para [0079]) within a substrate (10, Fig. 3, para [0079]). Additionally, Eid discloses that the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials (para [0018], Eid).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the package substrate of Chang Chien modified by Thacker, such that the package substrate comprises a core as taught by Canali, because the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core, and can serve as a platform for building up layers of conductors and dielectric materials (para [0018], Eid).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chang Chien et al. (US 2021/0265273 A1, of record), Thacker et al. (US 2016/0216445 A1, of record), Elsherbini et al. (US 2020/0219815 A1, of record) and Sung et al. (US 2015/0255427 A1, newly cited), as applied to claim 23 above and further in view of Yu et al. (US 2019/0295912 A1, of record).
Re Claim 24, Chang Chien modified by Thacker, Elsherbini and Sung teaches the electronic package of claim 23, wherein the first die (130, Chang Chien) is a photonics integrated circuit, the second die (120, Chang Chien) is an electrical integrated circuit (120 can be a CPU chip, para [0016], Chang Chien), and the third die (110, Chang Chien) is a logic die (110 can be a logic chip, para [0016], Chang Chien).
Chang Chien does not explicitly disclose that the first die (130) is a photonics die but does disclose that various types of semiconductor chips may be implemented according to actual need (para [0016]), for example CPU or GPU chip, logic chip or memory chip (para [0016]).
Related art from Yu teaches that a semiconductor die (101, para [0015], Fig. 1) can be designed for a desired functionality, such as being a system-on-chip, a graphic die, a MEMS dies, a sensor die, a photonic die, a memory die, other logic dies, combinations of these, or the like (para [0015]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to have the chip 130 of Chang Chien to be a photonic chip as disclosed by Yu, as the semiconductor chip can be designed for a desired functionality (para [0015], Yu).
Response to Arguments
Applicant’s arguments with respect to claims 1, 12 and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
With respect to applicant’s remarks regarding possible suggestions for claim amendments to make them allowable, the Examiner notes that if the Examiner had found any allowable subject matter, the Examiner would have notified it in the Office Action.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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