Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 18, 2025 has been entered.
Status of Claims
Examiner notes that in the instant application:
-Claims 26-50 are pending.
-Claims 1-25 are Cancelled.
-Claims 26 and 46 are Amended.
-Claims 36-45 are withdrawn.
Response to Arguments
Applicant's arguments filed November 18, 2025 have been fully considered but they are not persuasive.
Applicant’s argument that the amended limitation of “and wherein an entirety of the dielectric layer comprising oxygen is physically separated from the source and the drain” fails to be disclosed by Lilak et al. (U.S. Pub. 2020/0105891), hereinafter Lilak, seems to be specifically based off the embodiment disclosed by Lilak of Fig. 2E. However, as was brought to the Applicant’s attention in the Advisory Action dated November 10, 2025, this does not account for further embodiments provided by Lilak’s specification. As was previously noted, Lilak Paragraph [0079], discloses "In some embodiments, transistor device 200 may include the sidewall spacers 217 to surround (either partially or entirely) the first and second EPI layers 232 and 234..." Thus, even with the inclusion of “an entirety” in the claim limitation, Lilak still discloses the limitation, as the spacer would be between the dielectric layer comprising oxygen and the source/drain. A modified version of Lilak Fig. 2E which incorporates the teachings of Paragraphs [0057] (previously used in the rejections) and [0079] will be provided below for clarity.
New rejections based on the newly amended limitations are presented below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26-30, 32-34, and 46-49 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak. For clarity, a modified version of Lilak Fig. 2E, hereinafter Fig. M, which incorporates the teachings of Lilak Paragraphs [0057] and [0079] is provided below.
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Regarding Claim 26, Lilak teaches a semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) comprising:
-a gate all around (GAA) field effect transistor (FET) (‘transistor’ (270); Fig. M, Paragraph [0056]) that includes:
-a sub-channel (a portion of the substrate (202) located below (270); Fig.
M, Paragraph [0054]) in direct contact (Paragraph [0057]) with a source (‘EPI layer’ (232), e.g. the (232) on the left; Fig. M, Paragraph [0080]) and a drain ((232) on the right; Fig. 2E);
-a channel (consisting of an ‘interconnect’ (265) and a ‘transition layer’ (225)
above and below each interconnect (265) in the cross-sectional view of Fig. M; Fig. M, Paragraph [0079]) above the sub-channel (portion of (202)), the channel ((265) and (225)) coupled with the source (left (232)) and the drain (right (232)), wherein the channel includes a nanowire ((265); Paragraph [0034]); and
-a dielectric layer (bottom layer (230) as formed directly below (270) and not between (202) and (232); Fig. M, Paragraphs [0033], [0054], and [0057])
comprising oxygen (e.g. carbon-doped silicon oxide; Paragraph [0033]) on a side of the sub-channel (top surface of the portion of (202)) between the channel ((265) and (225)) and the sub-channel (portion of (202)), wherein the dielectric layer comprising oxygen (bottom (230)) includes a dopant (carbon), and wherein an entirety of the dielectric layer comprising oxygen (bottom (230)) is physically separated from (via the spacers (217), Paragraph [0079], Fig. M) the source (left (232)) and the drain (right (232))
Regarding Claim 27, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the dopant includes carbon atoms (‘carbon-doped’; Paragraph [0033]).
Regarding Claim 28, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the dopant (carbon) includes electrically active defects (adding carbon doping necessarily results in lowering the dielectric constant of silicon oxide, due to the presence of electrically active defects).
Regarding Claim 29, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the channel ((265) and (225)) includes a second dielectric layer ((225)) that does not include the dopant (e.g. silicon dioxide; Paragraph [0045]).
Regarding Claim 30, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 29, wherein:
- the channel ((265) and (225)) includes a first side (e.g. top side relative to the vertical; Fig. M) and a second side opposite the first side (e.g. bottom side relative to the vertical; Fig. 2M); and wherein the second dielectric layer (225) is on the first side (top, above (265)) and the second side (bottom, below (265)) of the channel.
Regarding Claim 32, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the channel ((265) and (225)) is a plurality of channels (e.g. the bottom, middle, and top groupings of (265) and (225)) above the sub-channel (portion of (202)).
Regarding Claim 33, Lilak teaches the apparatus (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the sub-channel (portion of (202)) includes silicon (e.g. silicon; Paragraph [0030])
Regarding Claim 34, Lilak teaches the apparatus (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the sub-channel (portion of (202)) is a portion of a substrate (totality of (202)).
Regarding Claim 46, Lilak teaches a (GAA) field effect transistor (FET) (‘transistor’ (270); Fig. M, Paragraph [0056]) comprising:
-a sub-channel (a portion of the substrate (202) located below (270); Fig. M, Paragraph [0054]);
-a plurality of channels (each consisting of an ‘interconnect’ (265); Fig. M, Paragraph
[0079]) above the sub-channel (portion of (202));
-a source (‘EPI layer’ (232), e.g. the (232) on the left; Fig. M, Paragraph [0080]) in direct contact (Paragraph [0057]) with the sub-channel (portion of (202)) and coupled with a portion, respectively, of the plurality of channels (each (265));
-a drain ((232) on the right; Fig. M) in direct contact (Paragraph [0057]) with the sub-channel (portion of (202)) and coupled with the plurality of channels (each (265));
-a first oxide layer (‘transition layers’ (225) of silicon dioxide; Fig. M, Paragraphs [0079] and [0045]) on each of the plurality of channels (each (265)); and
-a second oxide layer (carbon-doped silicon oxide layer (230) as formed directly below (270) and not between (202) and (232); Fig. M, Paragraph [0033], [0054], [0057]) on the sub-channel (portion of (202)), wherein the second oxide layer (230) includes a dopant (carbon), and wherein an entirety of the dielectric layer comprising oxygen (bottom (230)) is physically separated from (via the spacers (217), Paragraph [0079], Fig. M) the source (left (232)) and the drain (right (232)).
Regarding Claim 47, Lilak teaches the transistor (‘transistor’ (270); Fig. M, Paragraph [0056]) of Claim 46, wherein:
- the dopant includes carbon atoms (carbon-doped).
Regarding Claim 48, Lilak teaches the transistor (‘transistor’ (270); Fig. M, Paragraph [0056]) of Claim 46, wherein:
- the plurality of channels (each (265)) above the sub-channel (portion of (202)) are nanoribbons (Paragraph [0034]).
Regarding Claim 50, Lilak teaches the transistor (‘transistor’ (270); Fig. M, Paragraph [0056]) of Claim 46, wherein:
- the sub-channel (portion of (202)) is a portion of a silicon substrate (totality of (202), a silicon substrate; Paragraphs [0030] and [0031]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over by Lilak et al. (U.S. Pub. 2020/0105891), hereinafter Lilak, and in view of Hashemi et al. (U.S. Pub 2015/0236120), hereinafter Hashemi.
Regarding Claim 31, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, wherein:
-the nanowire (265) is a semiconductor (Paragraph [0026]).
Lilak does not explicitly teach:
-the nanowire is a silicon nanowire.
Hashemi teaches a semiconductor device comprising gate-all-around transistors wherein:
-the nanowire is a semiconductor silicon nanowire ((46); Fig. 5D, Paragraph [0029])
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teachings of Hashemi into the device of Lilak such that the nanowire is a silicon nanowire. This would be due to the predictable result of having a semiconductor (silicon) material based nanowire in the device.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over by Lilak et al. (U.S. Pub. 2020/0105891), hereinafter Lilak, and in view of Wang et al. (U.S. Pub 2015/0102287), hereinafter Wang.
Regarding Claim 35, Lilak teaches the semiconductor device (‘transistor device’ (200); Figs. 2A-2E and M, Paragraph [0054]) of Claim 26, upon which it depends, but does not teach:
-a portion of the sub-channel proximate to the dielectric layer comprising oxygen of the sub-channel includes the dopant.
Wang teaches application of materials in a gate-all-around (GAA) nanowire channel field-effect transistor wherein:
-an insulating layer of silicon includes a carbon dopant (Paragraph [0017])
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teachings of Wang into the device of Lilak such that a portion of the sub-channel proximate to the dielectric layer comprising oxygen of the sub-channel includes the dopant. This would be motivated by the fact doing so would increase the resistivity of the sub channel thereby improving electrical isolation between the source and drain via the sub channel and preventing current leakage, improving transistor efficiency (Wang, Paragraph [0017]).
Claim 49 is rejected under 35 U.S.C. 103 as being unpatentable over by Lilak et al. (U.S. Pub. 2020/0105891), hereinafter Lilak, and in view of Li et al. (U.S. Pub 2006/0267066), hereinafter Li.
Regarding Claim 49, Lilak teaches the transistor (‘transistor’ (270); Fig. M, Paragraph [0056]) of Claim 46, wherein:
-there is a first oxide layer (225) on each of the plurality of channels (each (265)), wherein the oxide layer is a high-k dielectric layer (Paragraph [0045])
Lilak does not explicitly teach the oxide layer:
-includes doping below a threshold level of 5E14 cm-2.
Li teaches a method of manufacturing high-k dielectric semiconductor materials wherein:
-a first oxide layer (oxide layer (40) e.g. hafnium oxide; Fig. 3, Paragraph [0026]) includes doping (e.g. nitrogen ions; Paragraph [0018]) below a threshold level of 5E14 cm-2 (e.g. 1011cm-2 ; Paragraph [0020])
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teachings of Li into the device of Lilak such that the oxide layer on each of the plurality of channels includes doping below a threshold level of 5E14 cm-2. This would be motivated by the fact doing so would provide for an improved high-k dielectric oxide to the device (Li, Paragraphs [0005] and [0008]).
Conclusion
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/D.M./ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812