DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 03/27/2026. Claims 1-20 are currently pending, of which claims 1-5, 9-14, 16-18 and 20 are currently rejected, and claims 6-8, 15, and 19 are currently objected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/27/2026 has been entered.
Information Disclosure Statement
The information disclosure statement filed 06/15/2026 fails to comply with 37 CFR 1.98(a)(3), which requires an English-language translation of a non-English-language document. Documents not considered are lined through.
Response to Arguments
Applicant’s arguments filed 03/27/2026 have been fully considered.
Drawing Objection: Applicant’s arguments regarding the drawing objections have been fully considered, but they are not persuasive.
Applicant argues at the bottom of page 7 and in page 8 that the features in the dependent claims don’t need to be shown in the drawings as they are not necessary for the understanding of the claimed invention. Applicant specifically argues “As stated in the Code of Federal Regulations, the drawings in a nonprovisional application must show every feature of the invention specified in the claims. See 37 C.F.R. § 1.83(a). Importantly, the Code of Federal Regulations further states that the applicant for a patent is required to furnish a drawing of the invention where necessary for the understanding of the subject matter sought to be patented. See 37 C.F.R. § 1.81(a). Applicant submits that a drawing of the "maximum circuit that is included in a floating point matrix multiplication datapath or a pipelined floating point matrix multiplication datapath" from claim 11 and "the plurality of input values comprises a plurality of exponents" from claim 19 are not necessary for the understanding of the subject matter of those claim limitations.”
Examiner respectfully disagrees. 37 C.F.R. 1.83 states “(a) The drawing in a nonprovisional application must show every feature of the invention specified in the claims. However, conventional features disclosed in the description and claims, where their detailed illustration is not essential for a proper understanding of the invention, should be illustrated in the drawing in the form of a graphical drawing symbol or a labeled representation (e.g., a labeled rectangular box). In addition, tables that are included in the specification and sequences that are included in sequence listings should not be duplicated in the drawings.” Hence, every claimed feature must be shown in the drawings even if the details are not essential for a proper understanding of the invention. See 37 C.F.R. 1.83.
35 U.S.C. 103: Applicant’s arguments regarding the 35 U.S.C. 103 rejection have been fully considered and are persuasive. However, see new reasons of rejection necessitated by amendments.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the maximum circuit that is “included in a floating point matrix multiplication datapath or a pipelined floating point matrix multiplication datapath” from claim 11, and “the plurality of input values comprises a plurality of exponents” from claim 19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 9, 10, 12, 14, 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over K. Pagiamtzis in NPL: “Content-addressable memory (CAM) circuits and architectures: a tutorial and survey” (https://ieeexplore.ieee.org/document/1599540), hereinafter “Pagiamtzis”, in view of Chuang et al. (U.S. Patent No.: US 4928260 A), hereinafter “Chuang”.
Regarding Claim 1, Pagiamtzis teaches:
A circuit comprising:
a first plurality of detection subcircuits, wherein:
each detection subcircuit receives a plurality of input values in parallel (Abstract, e.g., CAM outputs data within one clock cycle; Section I. Introduction, e.g., CAM is used to classify and forward Internet protocol (IP) packets in network routers; Fig. 1, e.g., stored words (detection subcircuits) receive search words (input value); Fig. 3, e.g., each search word contains a plurality of input bits (plurality of input values), which are inputted in parallel),
each detection subcircuit included in the first plurality of detection subcircuits computes a different detection result that is included in a first plurality of detection results (Section I. I Introduction, ¶4, e.g., Each stored word (detection subcircuit) has a matchline that indicates if a search word is identical to a stored word (detection result); Fig. 1, e.g., shows stored word 1 - w-1 (plurality of detection subcircuits) outputting detection results through matchlines), and each detection result indicates whether at least one input value included in the plurality of input values is equal to a different possible integer value included in a plurality of possible integer values (Section I. I Introduction, ¶4, e.g., Each stored word (detection subcircuit) has a matchline that indicates if a search word (first set of bits from a plurality of input values) is identical (at least one input value) to a stored word (second set of bits) from a plurality of stored words (plurality of possible integer values));
and a first encoder coupled to the first plurality of detection subcircuits that: determines a first active bit or a last active bit from first encoder input data (Fig. 1, e.g., encoder (first encoder) is attached to stored words through matchlines, which supply match signal (first encoder input data); Section I. Introduction, ¶4, e.g., A priority encoder is used instead of a simple encoder. Priority encoder outputs value with the highest priority. Lower address locations receive higher priority (last active bit)),
wherein each detection result included in the first plurality of detection results comprises a different bit of the first encoder input data (Fig. 1, e.g., encoder (first encoder) receives match signals through matchlines as separate inputs (different bit of the first encoder input data));
and encodes a bit position associated with the first active bit or the last active bit (Section I. Introduction, ¶4, e.g., A priority encoder is used instead of a simple encoder. Priority encoder outputs value with the highest priority. Lower address locations receive higher priority (last active bit)) …
Pagiamtzis does not teach:
… to generate a maximum value or a minimum value.
However, in the same field of endeavor, Chuang teaches how Content-addressable memories can be configured to locate the maximum or minimum in a set of stored numbers. Chuang explains “Content-addressable searching is sometimes performed without reference to an external search argument, for instance, when locating the maximum or minimum in a set of stored numbers.” See Chuang: Column 2 Lines 20-24. Additionally, Pagiamtzis suggests CAM applications can be used, where more than one match will occur. See Pagiamtzis ¶4.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Content-addressable memory searching instruction to locate the maximum or minimum value as taught by Chuang with the content-addressable memory as taught by Pagiamtzis. One would have been motivated to combine these references because both references disclose using an encoder to generate a bit value based on match signals, and Chaung enhances the model of Pagiamtzis by adding the feature of generating maximum or minimum values using the CAM without implementing extra circuitry. Pagiamtzis in view of Chuang teach claim 1 in its entirety.
Regarding Claim 3, Pagiamtzis in view of Chuang teach:
The circuit of claim 1, wherein the first encoder comprises a parallel priority encoder or a trailing one detector (Pagiamtzis: Section I. Introduction, ¶4, e.g., A priority encoder is used instead of a simple encoder; Fig. 1, e.g., encoder receives lines in parallel).
Regarding Claim 4, Pagiamtzis in view of Chuang teach:
The circuit of claim 1, wherein a first detection subcircuit included in the first plurality of detection subcircuits comprises:
a plurality of match detectors (Pagiamtzis: Section I. I Introduction, ¶4, e.g., Each stored word (detection subcircuit) has a matchline; Section II. Core Cells and Matchline Structure, A. NOR Cell, e.g., Each Cell compares each stored bit to search bit of corresponding words (plurality of match detectors)); and
an OR component coupled to the plurality of match detectors (Pagiamtzis: Section II. Core Cells and Matchline Structure, A. NOR Cell, e.g., Cells connected in parallel act as a NOR component (Negated OR component)).
Regarding Claim 5, Pagiamtzis in view of Chuang teach:
The circuit of claim 1, further comprising:
a plurality of pipelining flip-flops coupled to the first encoder that store the maximum value or the minimum value (Pagiamtzis: Fig. 17, e.g., shows plurality of pipeline flip-flops attached to CAM cells; Fig. 4, e.g., shows multiple CAM Cells coupled to encoder (first encoder)).
Regarding Claim 9, Pagiamtzis in view of Chuang teach:
The circuit of claim 1, wherein a least significant bit or a most significant bit of the first encoder input data comprises a binary value of one (Pagiamtzis: Section I. Introduction, ¶4, e.g., hit signal can be implemented to flag the case in which there is no matching in the CAM. Implementing this signal in the encoder would cause the hit signal to be the signal with the least priority (least significant bit)).
Regarding Claim 10, Pagiamtzis in view of Chuang teach:
The circuit of claim 1, wherein a number of detection subcircuits included in the first plurality of detection subcircuits is one less than two to the power of a number of bits in each input value included in the plurality of input values (Pagiamtzis: Section V. Power-Saving CAM Architectures, ¶5, e.g., a CAM with 72-bit words will have 272 possible entries (2n); Fig. 1, e.g., stored words (detection subcircuits) are w-1 (2n -1)).
Regarding claims 12, 14, and 17, they are method claims practiced by the apparatus of claim 1, 5, and 9, respectively. They are rejected for the same reasons as claims 1, 5, and 9.
Regarding Claim 16, Pagiamtzis in view of Chuang teach:
The method of claim 12, wherein the maximum value or the minimum value comprises a maximum or a minimum of the plurality of input values (Pagiamtzis: Section I. I Introduction, ¶4, e.g., priority encoder selects matchline with the highest priority; Fig. 1, e.g., search word is distributed through searchlines (plurality of input values); Chuang: Column 2 Lines 20-24, e.g., CAMs can be configured to indicate maximum or minimum value).
The motivation to combine provided with respect to claims 1 and 12 applies equally to claim 16.
Regarding Claim 18, Pagiamtzis in view of Chuang teach:
The method of claim 12, wherein the first plurality of detection results is associated with a range of integers that spans from one through one less than two to the power of a number of bits in each input value included in the plurality of input values (Pagiamtzis: Section V. Power-Saving CAM Architectures, ¶5, e.g., a CAM with 72-bit words will have 272 possible entries (2n); Fig. 1, e.g., stored words (detection subcircuits) are w-1 (2n -1)).
Regarding claim 20, it is a media claim practiced by the apparatus of claim 1. It is rejected for the same reasons as claim 1.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Pagiamtzis in view of Chuang, further in view of Lee (U.S. Patent No.: US 5867088 A), hereinafter “Lee”.
Regarding Claim 2, Pagiamtzis in view of Chuang teach:
The circuit of claim 1, wherein the first encoder generates the maximum value (Pagiamtzis: Section I. I Introduction, ¶4, e.g., priority encoder selects matchline with the highest priority; Fig. 1; Chuang: Column 2 Lines 20-24, e.g., CAMs can be configured to indicate maximum or minimum value);
Pagiamtzis in view of Chuang do not teach:
and further comprising:
a first plurality of inverters coupled to the first plurality of detection subcircuits that invert a plurality of sources to generate the plurality of input values;
and a second plurality of inverters coupled to the first encoder that invert the maximum value to generate the minimum value.
However, Lee teaches:
and further comprising:
a first plurality of inverters coupled to the first plurality of detection subcircuits that invert a plurality of sources to generate the plurality of input values (Fig. 4, e.g., Inverter with a mux are used for DTRs (detection circuit); Column 5, Lines 25-29, e.g., Inverters are used for each input to select minimum or maximum values);
and a second plurality of inverters coupled to the first encoder that invert the maximum value to generate the minimum value (Fig. 5, e.g., inverter is coupled to the NOR gate).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the inverter and mux at each input and each NOR gate as taught by Lee with the search word input and matchline outputs as taught by Pagiamtzis in view of Chuang, respectively. One would have been motivated to combine these references because both references disclose generating maximum or minimum values using NOR gates, and Lee enhances the model of Pagiamtzis in view of Chuang by allowing for dynamic selection of maximum or minimum determination.
Regarding claim 13, it is a method claim practiced by the apparatus of claim 2. It is rejected for the same reasons as claim 2.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Pagiamtzis in view of Chuang, further in view of Urbanski et al. (U.S. Patent No.: US 12254061 B2), hereinafter “Urbanski”.
Regarding Claim 11, Pagiamtzis in view of Chuang teach the circuit of claim 1. Pagiamtzis in view of Chuang do not teach:
further comprising a maximum circuit that is included in a floating point matrix multiplication datapath or a pipelined floating point matrix multiplication datapath.
However, Urbanski teaches:
further comprising a maximum circuit that is included in a floating point matrix multiplication datapath or a pipelined floating point matrix multiplication datapath (FIG. 9, e.g., illustrates a floating-point matrix multiplication circuit; Column 1, Lines 62-63; Fig. 10, e.g., shows Max exponent determiner 1040 (maximum circuit)).
Additionally, Urbanski teaches the Max exponent determiner 1040 being implemented in a computer. Urbanski explains “the circuit is part of a processor (e.g., computer) and improves the functionality of the processor (e.g., computer) itself.” See Urbanski: Column 8, lines 7-9. Pagiamtzis teaches a CAM being implemented for packet forwarding in a computer network. See Section I. Introduction, A. Packet Forwarding Using CAM.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the maximum exponent circuit in a computer as taught by Urbanski with the computer network using CAM as taught by Pagiamtzis in view of Chuang. One would have been motivated to combine these references because both references disclose maximum circuits implemented in a computer, and Urbanski enhances the model of Pagiamtzis in view of Chuang because it “improves the functionality of the processor” (Urbanski: Column 8 Line 8).
Allowable Subject Matter
Claims 6-8, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Pagiamtzis teaches a Content-addressable memory (CAM) that receives search words to match with stored words, and uses matchlines to determine if the input search words match the stored words in the CAM. Pagiamtzis further teaches using an encoder to generate a binary match location corresponding to the matchline. See Pagiamtzis: Fig. 1 and section 1. Pagiamtzis does not teach or suggest these search words input values being exponent values, nor does it teach or suggest using a mask subcircuit coupled to the first encoder and to a second plurality of detection subcircuits coupled to a second encoder. Instead, Pagiamtzis teaches using one plurality of stored words to match search words, and one encoder to output binary match locations, and is silent about using the CAM for exponents. Therefore, Pagiamtzis does not teach or suggest the combination of claims 6 and 19, including the limitations “a mask subcircuit coupled to the first encoder that generates a plurality of next values associated with a next bit position sequence based on the plurality of overall input values and the maximum value or the minimum value; a second plurality of detection subcircuits coupled to the mask subcircuit that computes a second plurality of detection results; and a second encoder coupled to the second plurality of detection subcircuits that determines a next maximum value or a next minimum value that is represented via the next bit position sequence of the overall maximum value or the overall minimum value”, nor “wherein the plurality of input values comprises a plurality of exponents.”
Chuang teaches a CAM array with a priority encoder. CAM array receives a bit coded word through bitlines, and outputs a match result though a plurality of match lines. Chaung further teaches how this CAM array can be used for locating maximum or minimum values of a set of numbers. See Chuang: Fig. 1 and Column 2 Line 5 – Column 4 Line 54. Chuang does not teach or suggest these search words input values being exponent values, nor does it teach or suggest using a mask subcircuit coupled to the first encoder and to a second plurality of detection subcircuits coupled to a second encoder. Instead, Chaung teaches using one plurality of stored words to match search words, and one encoder to output binary match locations, and is silent about using this CAM array for exponents. Therefore, Chuang does not teach or suggest the combination of claims 6 and 19, including the limitations “a mask subcircuit coupled to the first encoder that generates a plurality of next values associated with a next bit position sequence based on the plurality of overall input values and the maximum value or the minimum value; a second plurality of detection subcircuits coupled to the mask subcircuit that computes a second plurality of detection results; and a second encoder coupled to the second plurality of detection subcircuits that determines a next maximum value or a next minimum value that is represented via the next bit position sequence of the overall maximum value or the overall minimum value”, nor “wherein the plurality of input values comprises a plurality of exponents.”
Almy (U.S. Patent No.: US 4670858 A), hereinafter “Almy” teaches a CAM array that is coupled to a match/detect block, and an address encoder. CAM array stores a number of data words, and outputs a match signal for every word match in the CAM array. Match/detect block outputs a single match from the matches of the CAM array, acting as a prioritizing circuit. See Almy: Fig. 1 and Column 2 Line 20 – Column 3 Line 47. Almy does not teach or suggest these search words input values being exponent values, nor does it teach or suggest using a mask subcircuit coupled to the first encoder and to a second plurality of detection subcircuits coupled to a second encoder. Instead, Almy teaches using one plurality of stored words to match input words, and a match/detect block to prioritize one match signal, and is silent about using this CAM array for exponents. Therefore, Almy does not teach or suggest the combination of claims 6 and 19, including the limitations “a mask subcircuit coupled to the first encoder that generates a plurality of next values associated with a next bit position sequence based on the plurality of overall input values and the maximum value or the minimum value; a second plurality of detection subcircuits coupled to the mask subcircuit that computes a second plurality of detection results; and a second encoder coupled to the second plurality of detection subcircuits that determines a next maximum value or a next minimum value that is represented via the next bit position sequence of the overall maximum value or the overall minimum value”, nor “wherein the plurality of input values comprises a plurality of exponents.”
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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