DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the Pre-Brief appeal conference decision filed on 12/01/25. Claims 1-24 are pending. Claims 9-12 are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 13-22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pindl et al. (US PGPub 2020/0249380, hereinafter referred to as “Pindl”).
Pindl discloses the semiconductor method as claimed. See figures 1-3 and corresponding text, where Pindl teaches, in claim 1, a manufacturing method, comprising:
forming a first dicing groove (DL1) and a second dicing groove (DL2) in a first surface of a cap wafer (260); (figures 2G and 3; [0087-0101])
aligning the cap wafer (260) and a device substrate (220) such that the first surface of the cap wafer (260) faces a second surface of the device substrate (220), wherein the device substrate comprises: (figure 3; [0096-0101])
a device on to the second surface of the device substrate (220), and a bond pad (230-2, 230-3) on the second surface of the device substrate and coupled to the device, the bond pad (230-2, 230-3) facing the first surface of the cap wafer (260) or at least one of the first or second dicing grooves; (figure 3; [0096-0101])
bonding the cap wafer (260) to the device substrate (220); (figure 3; [0096-0101]) and
partially dicing the cap wafer (260) at the first and second dicing grooves such that the bond pad (230-2, 230-3) is exposed (figures 2G and 3; [0087-0101]).
Pindl teaches, in claim 2, wherein aligning the cap wafer and the device substrate comprises aligning the first and second dicing grooves between the bond pad and a bonding area, wherein the bonding area comprises an area at which the cap wafer is bonded to the device substrate (figures 1 and 2E; [0026-0046], [0077-0081]).
Pindl teaches, in claim 3, wherein a width of the first and second dicing grooves is such that cap wafer dust formed during the partial dicing does not fall on the bond pad (figures 2G and 3; [0087-0101]).
Pindl teaches, in claim 4, wherein bonding the cap wafer to the device substrate comprises: bonding a first portion of the cap wafer and a first portion of the device substrate with a bonding polymer; (figures 1 and 2E; [0014-0046]) and
bonding a second portion of the cap wafer and a second portion of the device substrate with the bonding polymer, wherein the bonding polymer abuts the first surface of the cap wafer and the second surface of the device substrate, and the first and second portions of the device substrate are on opposite sides of the device (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 5, wherein the second portion of the device substrate is between the device and the bond pad (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 6, wherein aligning the cap wafer and the device substrate comprises aligning at least one of the first dicing groove and the second dicing groove between the second portion of the device substrate and the bond pad (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 7, wherein partially dicing the cap wafer at the first and second dicing grooves comprises sawing through the cap wafer to a depth of the first and second dicing grooves (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 8, wherein the device comprises one of an integrated circuit and a microelectromechanical system device ([0097]).
Pindl teaches, in claim 13, a method, comprising:
forming a plurality of dicing grooves (DL1, DL2) in an inner surface of a cap wafer (260); (figures 1 and 2E; [0026-0046], [0077-0081])
forming affixing a plurality of devices on a surface of a substrate (220); (figures 1 and 2E; [0026-0046], [0077-0081])
forming a plurality of bond pads (230-2, 230-3) on the surface of the substrate (220), wherein the plurality of bond pads (230-2, 230-3) is coupled to the plurality of devices; (figures 2G and 3; [0087-0101])
aligning the cap wafer (260) and the substrate (220) such that the inner surface of the cap wafer (260) faces the surface of the substrate (220) and the bond pads (230-2, 230-3); (figures 2G and 3; [0087-0101])
bonding the cap wafer (260) to the substrate (220); (figures 2G and 3; [0087-0101]) and
partially dicing an outer surface of the cap wafer (260) at portions of the outer surface corresponding to the plurality of dicing grooves (DL1, DL2) in the inner surface of the cap wafer (260) (figures 1 and 2E; [0026-0046], [0077-0081])
.
Pindl teaches, in claim 14, wherein aligning the cap wafer and the substrate comprises aligning the plurality of dicing grooves such that for each bond pad in the plurality of bond pads, a dicing groove in the plurality of dicing grooves is between the bond pad and a bonding area, wherein the bonding area comprises an area at which the cap wafer is bonded to the substrate (figures 1 and 2E; [0026-0046], [0077-0081])
.
Pindl teaches, in claim 15, wherein a width of the dicing groove is such that cap wafer dust formed during the partial dicing does not fall on the bond pad. (figures 1 and 2E; [0026-0046], [0077-0081])
Pindl teaches, in claim 16, wherein bonding the cap wafer to the substrate comprises, for each device in the plurality of devices:
bonding a first portion of the inner surface of the cap wafer and a first portion of the surface of the substrate with a bonding polymer; (figures 1 and 2E; [0014-0046]) and
bonding a second portion of the inner surface of the cap wafer and a second portion of the surface of the substrate with the bonding polymer, wherein the first and second portions of the surface of the substrate are on opposite sides of the device, in which the bonding polymer abuts the inner surface of the cap wafer and the surface of the substrate (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 17, wherein: the plurality of devices comprises a plurality of stress-sensitive devices(figures 1 and 2E; [0014-0046]);
the surface of the substrate further comprises a plurality of isolation trenches (14);
for each device in the plurality of devices, an isolation trench (235) in the plurality of isolation trenches surrounds the device; (figures 1 and 2E; [0014-0046]) and
forming the plurality of bond pads (34) on the surface of the substrate comprises forming, for each device in the plurality of devices, a corresponding bond pad being laterally between the corresponding isolation trench and a dicing groove of the plurality of dicing grooves (figures 1 and 2E; [0014-0046])
Pindl teaches, in claim 18, wherein the second portion of the surface of the substrate is between the corresponding isolation trench and the corresponding bond pad (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 19, wherein aligning the cap wafer and the substrate comprises aligning, for each device in the plurality of devices, a dicing groove in the plurality of dicing grooves between the second portion of the surface of the substrate and the corresponding bond pad (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 20, wherein partially dicing the outer surface of the cap wafer at portions of the outer surface corresponding to the plurality of dicing grooves comprises aligning at least one blade with the portions of the outer surface corresponding to the plurality of dicing grooves (figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 21, wherein partially dicing the outer surface of the cap wafer at portions of the outer surface corresponding to the plurality of dicing grooves further comprises sawing the at least one blade through the portions of the outer surface to a depth of the plurality of dicing grooves(figures 1 and 2E; [0014-0046]).
Pindl teaches, in claim 22, wherein the plurality of devices comprises at least one of an integrated circuit and a microelectromechanical system device ([0097]).
Pindl teaches, in claim 24, further comprising forming first and second trenches on the second surface of the device substrate adjacent to the device, in which the first trench is laterally between the device and the first dicing groove, and the second trench is laterally between the device and the second dicing groove (figures 1 and 2E; [0014-0046]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pindl et al. (US PGPub 2020/0249380, hereinafter referred to as “Pindl”) as applied to claim 1 above, and further in view of Ostrowicki et al. (US PGPub 2021/0296196, hereinafter referred to as “Ostrowicki”).
Re: Claim 23, Pindl discloses the semiconductor method substantially as claimed. See the rejection above.
However, Pindl fails to show, in claim 23, wherein the device is a bulk acoustic wave (BAW) resonator.
Ostrowicki teaches, in claim 23, similar semiconductor devices called “stress sensitive component” that include bulk acoustic wave (BAW) resonator ([00024]). In addition, Ostrowicki provides the advantages of improving heat conduction and reducing shrinkage ([0004-0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the device is a bulk acoustic wave (BAW) resonator, in the method of Pindl, according to the teachings of Ostrowicki, with the motivation of having a stress sensitive component where heat conduction and reduction of shrinkage is improved.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 and 13-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 March 8, 2026