DETAILED ACTION
In the response filed 18 November 2025, claims 1, 9, and 16 were amended. Claims 8 was cancelled. Claims 1-3, 5-7, 9-18, and 20-22 remain pending with claims 11-15 being withdrawn. New rejections of claims 1-3, 5-7, 9, 10, 16-18, and 20-22 are required due to amendment. See below.
Updated Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 16 objected to because of the following informalities:
Claim 1, line 10, “at least one of the array of CABs” does not seem to have proper antecedent basis. There is only one array of CABs currently claimed in the claim. At least a second array of CABs would be needed for there to be “at least one of the array of CABs”. Either a second array should be claimed or the “at least one of” should be removed.
Claim 16 is objected to for the same reason.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a superconducting material arranged to form a Josephson junction and configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation” as described in claims 1 and 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3, 5-7, 9, 10, 16-18, and 20-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification, drawing and claims only describe Josephson junctions four times. Paragraph [0016], “Quantum FPAAs achieve better performance compared to non-quantum FPAAs as they use approaches from quantum computing such as Josephson junctions, superconducting circuits, quantum entanglement, and quantum tunneling.” Paragraph [0034] “When using superconducting materials, the quantum FPAAs may include Josephson junctions.” Paragraph [0066] “The quantum FPAA of any of Clauses 1-9, wherein the quantum FPAA comprises one or more Josephson junctions.” Paragraph [0085] “The system of any of Clauses 20-28, wherein the quantum FPAA comprises one or more Josephson junctions.”
Accordingly, with regards to the added limitation to claims 1 and 16 of “a superconducting material arranged to form a Josephson junction and configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation”, nowhere in the written description describes or shows a Josephson junction that is configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation. Applicant points to paragraph [0018] to of the specification to provide support for this, but the examiner disagrees with applicants interpretation. The quoted portion states “quantum FPAAs described herein may be designed to take advantage of parallel approaches to solving algorithms to improve the quality of the approximation. The quantum FPAA described herein suffers from degradation in the quality of the solution. This degradation is solved by solving the equations multiple times. That is, the quality of the solution may be able to be increased by repeating the equation multiple times and by averaging out the results (assuming all noise is Gaussian, etc.). The averaging out can be done in parallel as we can configure multiple parts of the quantum FPAA in an identical way to fill-up the unused computational analog blocks (CABs) and wires.” As best understood by the examiner this is describing multiple arrays of CABs acting in parallel to repeat solving an equation multiple times at once and averaging the results. It is unclear how this would be done by an array of CABs and a Josephson junction in parallel. As such, it does not appear that at the time the application was filed, the joint inventors had possession of the claimed invention, specifically an array of CABs and a Josephson junction in parallel.
None of the dependent claims correct this issue and are rejected for the same reasons.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-7, 9, 10, 16-18, and 20-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to the added limitation to claims 1 and 16 of “a superconducting material arranged to form a Josephson junction and configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation”, nowhere in the written description describes or shows a Josephson junction that is configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation. As described above, applicant points to paragraph [0018] to of the specification to provide support for this, but the examiner disagrees with applications interpretation. The quoted portion states “quantum FPAAs described herein may be designed to takes advantage of parallel approaches to solving algorithms to improve the quality of the approximation. The quantum FPAA described herein suffers from degradation in the quality of the solution. This degradation is solved by solving the equations multiple times. That is, the quality of the solution may be able to be increased by repeating the equation multiple times and by averaging out the results (assuming all noise is Gaussian, etc.). The averaging out can be done in parallel as we can configure multiple parts of the quantum FPAA in an identical way to fill-up the unused computational analog blocks (CABs) and wires.” As best understood by the examiner this is describing multiple CABs acting in parallel to repeat solving an equation multiple times at once and averaging the results. It is clear that this would not be done by a CAB and a Josephson junction in parallel. Furthermore, there is no drawing or description that specifically shows at least one CAB and a Josephson junction in parallel. Accordingly, it would have been unclear for one of ordinary skill in that art how to build or use a superconducting material arranged to form a Josephson junction and configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation.
None of the dependent claims correct this issue and are rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-9, 16-18, and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Twigg et al., "Configurable Analog Signal Processing," in view of Schmeider, US Patent Application Publication No. 2009/0198759, Newrock, “What are Josephson junctions? How do they work?” and Johal et al., US Patent Application Publication No. 2016/0285433.
In reference to claim 1 Twigg teaches a field programmable analog array (Figure 2) comprising:
an array of computational analog blocks (CABs) configured to perform a mathematical operation (Figure 2, and Pages 907-909, Section 3 “Scaling to large reconfigurable devices” CABs); and
an interconnection network connecting the CABs, the interconnection network comprising communication paths and switches (Figure 2, global routing, local routing and Pages 907-909, Section 3 “Scaling to large reconfigurable devices”; routing networks of paths and switches connecting the CABs).
Twigg does not teach wherein the field programmable analog array is a quantum field programmable analog array. Schmeider teaches a quantum field programmable analog array (Paragraph 0599, array of CABs on a single chip such as the one from Twigg, which are compatible with nanoelectronic devices (paragraph 0596) which include quantum dots and superconducting quantum interference devices (paragraph 0603) and perform as Josephson Junctions (Paragraph 0198). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to modify the field programmable analog array as taught by Twigg into the quantum field programmable analog array as taught by Schmeider to have the quantum field programmable analog array because it would provide options for generating complex discontinuous functions (Schmeider, Paragraph 0603).
Twigg in view of Schmeider further teach parallelism to increase problem speed processing (Schmeider, Paragraph 0595), and SQUIDs for quantum analog processing (Schmeider, Paragraph 0603). They do not teach a superconducting material arranged to form a Josephson junction. Newrock teaches a superconducting material arranged to form a Josephson junction (Paragraph 7, Electronic circuits can be built from Josephson junctions, especially digital logic circuitry. Many researchers are working on building ultrafast computers using Josephson logic. Josephson junctions can also be fashioned into circuits called SQUIDs--an acronym for superconducting quantum interference device). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate a SQUID as taught by Newrock into the quantum analog array as taught by Twigg in view of Schmeider to be operate in parallel (Schmeider, Paragraph 0595) with the array of CABs to perform the mathematical operation (Twigg, Figure 2, and Pages 907-909, Section 3 “Scaling to large reconfigurable devices” CABs) because SQUIDs are extremely sensitive and very useful in constructing extremely sensitive voltmeters (Newrock, paragraph 7).
Twigg in view of Schmeider and Newrock do not teach wherein at least one of the CABs is a universal analog component configured to perform the mathematical operation depending on a configuration of transistor switches. Johal teaches a universal analog component configured to perform the mathematical operation depending on a configuration of transistor switches. Johal teaches a universal analog component (Figures 1A and 15, UAB) configured to perform the mathematical operation (Figure 9, gain, Figure 11, summing, Figure 12 integrator) depending on a configuration of transistor switches (Figures 1B, 1C, Paragraphs [0070-71] transistor switches). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the universal analog component as taught by Johal as one of the CABs as taught by Twigg in view of Schmeider and Newrock because it would allow a single CAB be used to perform many different mathematical functions such as the ones found in figures 9, 11, and 12 of Johal.
In reference to claim 2, Twigg in view of Schmeider, Newrock, and Johal teaches wherein the array is a multilayer array (Twigg, Figure 2(a)).
In reference to claim 3, Twigg in view of Schmeider, Newrock, and Johal teaches wherein at least one of the CABs is an analog circuit (Twigg, CABs are analog circuits on Pages 907-909, Section 3 “Scaling to large reconfigurable devices”).
In reference to claim 5, Twigg in view of Schmeider, Newrock, and Johal teaches claim 1 as described above. Furthermore Schmeider teaches that any mathematical operation can be performed using the device (Paragraph [0016]). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the set theory as taught by Schmeider into the quantum field programmable analog array of claim 1 such that the mathematical operation is selected from the group consisting of: gain, logarithmic, exponential, raising of a number to a power, integration, and differentiation because there are all mathematical operations that a user might want to solve.
In reference to claim 6, Twigg in view of Schmeider, Newrock, and Johal teaches wherein the communication paths are selected from the group consisting of: wires, laser light, and any combination thereof (Twigg, interconnections are wires on Page 912, Section 5.3).
In reference to claim 7, Twigg in view of Schmeider, Newrock, and Johal teaches wherein at least one of the CABs further comprises an operational amplifier, passive components, and transistor switches (Twigg, Figure 3).
In reference to claim 9, Twigg in view of Schmeider, Newrock, and Johal teaches claims 1 and 8 as rejected above. They does not teach wherein the superconducting material is selected from the group consisting of niobium-titanium alloys, germanium- niobium alloys, niobium nitride alloys, yttrium barium copper oxide, magnesium diboride, fluorine-doped LaOFeAs, fullerenes, carbon nanotubes, graphene, and any combination thereof. However niobium-titanium alloys, germanium- niobium alloys, niobium nitride alloys, yttrium barium copper oxide, magnesium diboride, fluorine-doped LaOFeAs, fullerenes, carbon nanotubes, and graphene are all well-known superconducting materials. Official Notice is Taken. Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to use one or more of the superconducting materials of niobium-titanium alloys, germanium- niobium alloys, niobium nitride alloys, yttrium barium copper oxide, magnesium diboride, fluorine-doped LaOFeAs, fullerenes, carbon nanotubes, graphene in the quantum configurable analog array as taught by Twigg in view of Schmeider and Johal because they are all well known in the art for superconducting.
In reference to claim 16 Twigg teaches a system comprising: a processor comprising a field programmable analog array (Figure 2) comprising: an array of computational analog blocks (CABs) configured to perform a mathematical operation (Figure 2, and Pages 907-909, Section 3 “Scaling to large reconfigurable devices” CABs); and an interconnection network connecting the CABs, the interconnection network comprising communication paths and switches (Figure 2, global routing, local routing and Pages 907-909, Section 3 “Scaling to large reconfigurable devices”; routing networks of paths and switches connecting the CABs) and a memory coupled to the processor (Figure 12, PCs have memory).
Twigg does not teach wherein the field programmable analog array is a quantum field programmable analog array. Schmeider teaches a quantum field programmable analog array (Paragraph 0599, array of CABs on a single chip such as the one from Twigg, which are compatible with nanoelectronic devices (paragraph 0596) which include quantum dots and superconducting quantum interference devices (paragraph 0603) and perform as Josephson Junctions (Paragraph 0198). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to modify the field programmable analog array as taught by Twigg into the quantum field programmable analog array as taught by Schmeider to have the quantum field programmable analog array because it would provide options for generating complex discontinuous functions (Schmeider, Paragraph 0603).
Twigg in view of Schmeider further teach parallelism to increase problem speed processing (Schmeider, Paragraph 0595), and SQUIDs for quantum analog processing (Schmeider, Paragraph 0603). They do not teach a superconducting material arranged to form a Josephson junction. Newrock teaches a superconducting material arranged to form a Josephson junction (Paragraph 7, Electronic circuits can be built from Josephson junctions, especially digital logic circuitry. Many researchers are working on building ultrafast computers using Josephson logic. Josephson junctions can also be fashioned into circuits called SQUIDs--an acronym for superconducting quantum interference device). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate a SQUID as taught by Newrock into the quantum analog array as taught by Twigg in view of Schmeider to be operate in parallel (Schmeider, Paragraph 0595) with the array of CABs to perform the mathematical operation (Twigg, Figure 2, and Pages 907-909, Section 3 “Scaling to large reconfigurable devices” CABs) because SQUIDs are extremely sensitive and very useful in constructing extremely sensitive voltmeters (Newrock, paragraph 7).
Twigg in view of Schmeider and Newrock do not teach wherein at least one of the CABs is a universal analog component configured to perform the mathematical operation depending on a configuration of transistor switches. Johal teaches a universal analog component configured to perform the mathematical operation depending on a configuration of transistor switches. Johal teaches a universal analog component (Figures 1A and 15, UAB) configured to perform the mathematical operation (Figure 9, gain, Figure 11, summing, Figure 12 integrator) depending on a configuration of transistor switches (Figures 1B, 1C, Paragraphs [0070-71] transistor switches). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the universal analog component as taught by Johal as one of the CABs as taught by Twigg in view of Schmeider and Newrock because it would allow a single CAB be used to perform many different mathematical functions such as the ones found in figures 9, 11, and 12 of Johal.
In reference to claim 17, Twigg in view of Schmeider, Newrock, and Johal teaches wherein the array is a multilayer array (Twigg, Figure 2(a)).
In reference to claim 18, Twigg in view of Schmeider, Newrock, and Johal teaches wherein at least one of the CABs is an analog circuit (Twigg, CABs are analog circuits on Pages 907-909, Section 3 “Scaling to large reconfigurable devices”).
In reference to claim 20, Twigg in view of Schmeider, Newrock, and Johal teaches claim 1 as described above. Furthermore Schmeider teaches that any mathematical operation can be performed using the device (Paragraph [0016]). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the set theory as taught by Schmeider into the quantum field programmable analog array of claim 1 such that the mathematical operation is selected from the group consisting of: gain, logarithmic, exponential, raising of a number to a power, integration, and differentiation because there are all mathematical operations that a user might want to solve.
In reference to claim 21, Twigg in view of Schmeider, Newrock, and Johal teaches claim 1 as described above. Furthermore, Johal teaches wherein the universal analog component is further configured to receive an input voltage (Figure 9, gain, Figure 11, summing, Figure 12 integrator, Vref0) and provide an output voltage(Figure 9, gain, Figure 11, summing, Figure 12 integrator, Vout0), wherein the input voltage and the output voltage are related by the mathematical operation and depend on the configuration of transistor switches (Figure 9, gain, Figure 11, summing, Figure 12 integrator, switches).
In reference to claim 22, Twigg in view of Schmeider, Newrock, and Johal teaches claim 1 as described above. Furthermore, Johal teaches wherein at least one of the CABs includes an operational amplifier configured to provide feedback and a variable capacitor configured to the mathematical operation based on the feedback, and wherein the mathematical operation comprises integration (Figure 12 and paragraph 0097, integrator).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Twigg et al., "Configurable Analog Signal Processing," in view of Schmeider, US Patent Application Publication No. 2009/0198759, Newrock, “What are Josephson junctions? How do they work?”, Johal et al., US Patent Application Publication No. 2016/0285433 and George et al., “A Programmable and Configurable Mixed-Mode FPAA SoC”
In reference to claim 10, Twigg in view of Schmeider, Newrock and Johal teaches claims 1 as rejected above. They do not teach an integrated chip comprising: a system-on-chip for controlling the computation; one or more analog to digital converters (ADCs) for reading the results of the computation; one or more digital to analog converters (DACs) for configuring the CABs of the quantum FPAA; a memory; and a field-programmable gate array in combination with the quantum configurable analog array of claim 1. George teaches an integrated chip comprising: an FPAA; a system-on-chip for controlling the computation; one or more analog to digital converters (ADCs) for reading the results of the computation; one or more digital to analog converters (DACs) for configuring the CABs of the FPAA; a memory; and a field-programmable gate array (Figures 1 and 2 showing the FPAA, SoC, ADCs, DACs, memory and FPGA). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to replace the FPAA in the integrated chip of George with the quantum field programmable analog array as taught by Twigg in view of Schmeider, Newrock and Johal to have the integrated chip of claim 10 because it could generate multi-peak functions representing a fairly high-order polynomial.
Response to Arguments
Applicant's arguments filed 18 November 2025 have been fully considered but they are not persuasive.
With regards to applicants arguments that the amendments are supported by the written description, the examiner disagrees. See the 35 USC 112 rejections above for further explanation.
Applicant’s arguments with respect to the references of the previous office action not teaching the new limitation of “a superconducting material arranged to form a Josephson junction and configured to operate in parallel with at least one of the array of CABs to perform the mathematical operation.” are considered moot because the new ground of rejection incorporates a new reference that teaches missing limitation when taken into consideration with the other references from the previous office action.
Conclusion
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/B.B/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851