DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/01/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1) and Lin et al. (US 2020/0279998 A1).
Regarding claim 1, Lung discloses a phase change memory semiconductor structure (Fig. 1) comprising:
a dielectric (130);
a heater (120) located in the dielectric;
a stack including at least one lateral conductive metal layer disposed on said stack (although not shown in Fig. 1, the text of Lung discloses that two additional undoped layers of phase change material may be located over the doped chalcogenide layer 114; the one farther from the doped chalcogenide layer constituting the lateral conductive metal layer; ¶ 0030); an inner undoped chalcogenide layer (112) outward of the dielectric, a doped chalcogenide layer (114) outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer (although not shown in Fig. 1, the text of Lung discloses that two additional undoped layers of phase change material may be located over the doped chalcogenide layer; the one closer to the doped chalcogenide layer constituting the outer undoped chalcogenide layer; ¶ 0030); and
a top electrode (140; ¶ 0030) outward of the outer undoped chalcogenide layer.
Lung does not disclose a landing pad located inside of a substrate.
However, it is well known in the art to form heater elements in phase change memory semiconductor structures on top of landing pads inside of substrates (landing pad 130 inside substrate 120 in Fig. 8 of Ok).
There is a benefit to such a configuration in that it allows for electricity to be applied to the heater.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the substrate of Lung to use a landing pad inside of the substrate as taught by Ok for this benefit.
Lung does not disclose a hard mask outward of said top electrode; a second dielectric disposed on sides of said stack and an upper surface of said hard mask; or a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode.
Lin, in the same field of endeavor, discloses a phase change memory structure with a hard mask (“hard mask 122” in Fig. 1A, ¶ 0015) outward of a top electrode (“top electrode 120”, ¶ 0015);
a second dielectric (“upper portion 106b of the dielectric structure”, ¶ 0016) disposed on sides of a stack and an upper surface of said hard mask; and
a top electrical contact (“via 126”, ¶ 0016) penetrating said hard mask and said second dielectric and connected to said top electrode. There was a benefit to forming the hard mask, the second dielectric, and the top electrical contact as it allows for an electrical pathway to the top electrode while protecting the remaining structures. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a hard mask outward of said top electrode of Lung; a second dielectric disposed on sides of said stack of Lung and an upper surface of said hard mask; and a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode for this benefit.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1) and Lin et al. (US 2020/0279998 A1) as applied to claim 1, above, and further in view of Redaelli et al. (EP 2,034,536 B1).
Regarding claim 2, Lung in view of Ok and Lin further discloses that the lateral conductive metal layer is located outward of said outer undoped chalcogenide layer (see discussion in the rejection of claim 1, above).
Lung in view of Ok does not disclose the inclusion of a projection liner as claimed.
However, it was known in the art to form projection liners between heaters and phase change materials in phase change memory semiconductor structures (projection liner 11 in Fig. 5 of Redaelli).
There is a benefit to including a projection liner in that is allows for easier detection of the difference in resistance between programmed states (¶ 0020 of Redaelli).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of the combination of Lung in view of Ok to include a projection liner located between the inner undoped chalcogenide layer and the heater element as taught by Redaelli for this benefit.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1) and Redaelli et al. (EP 2,034,536 B1) as applied to claim 2, above, and further in view of Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9).
Regarding claim 3, Lung in view of Ok and Redaelli does not disclose a second lateral conductive metal layer located between said inner undoped chalcogenide layer and said doped chalcogenide layer.
However, it is well known in the art to form a lateral conductive metal layer between chalcogenide layers in a phase change memory device (additional top electrode (ATE) in Fig. 2a of Kim).
There is a benefit to using lateral conductive metal layers between chalcogenide layers in a phase change memory device in that it results in better amorphization (second column of Page 1484 of Kim).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok and Redaelli to insert a lateral conductive metal layer into the stack as taught by Kim this benefit.
With regards to where to insert the lateral conductive metal layer of Kim, there is a benefit to putting it between chalcogenides of different dopant profiles in that it can be applied between the deposition steps of the different chalcogenide layers rather than pause the deposition process of a single chalcogenide layer, deposit the metal layer, and then resume the original chalcogenide deposition before moving on to depositing the remaining chalcogenide layers which adds an extra processing step.
With regards to between which two of the three chalcogenide layers the metal layer is inserted, there is a finite number of possibilities: between the inner undoped chalcogenide layer and the doped chalcogenide layer or between the doped chalcogenide layer and the outer undoped chalcogenide layer.
One having ordinary skill in the art could have inserted it between the inner undoped chalcogenide layer and the doped chalcogenide layer with a reasonable expectation of success and, as such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to form the lateral conductive metal layer between the inner undoped chalcogenide layer and the doped chalcogenide layer.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1), Redaelli et al. (EP 2,034,536 B1), and Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9) as applied to claim 3, above, and further in view of Lai et al. (US 9,537,093 B1).
Regarding claim 4, Lung in view of Ok, Lin, Redaelli, and Kim does not disclose a sidewall layer as claimed.
Lai discloses a sidewall layer (216A in Fig. 4B) disposed on sides of a stack, said sidewall layer providing a current path. There was a benefit to forming a sidewall layer as such in that it aids in providing stable resistance and stable operating efficiency (Col. 2, Lines 35-36 of Lai).
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a sidewall layer as taught by Lai along the entirety of the stack in the structure of the combination for this benefit. In the resulting configuration, the sidewall layer will extend outward from the dielectric and contact the top electrode.
Claim(s) 1, 5, 6, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9) and Lin et al. (US 2020/0279998 A1).
Regarding claim 1, Lung discloses a phase change memory semiconductor structure (Fig. 1) comprising:
a dielectric (130);
a heater (120) located in the dielectric;
a stack including an inner undoped chalcogenide layer (112) outward of the dielectric, a doped chalcogenide layer (114) outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer (although not shown in Fig. 1, the text of Lung discloses that an additional undoped layer of phase change material may be located over the doped chalcogenide layer; ¶ 0030); and
a top electrode (140) outward of the outer undoped chalcogenide layer.
Lung does not disclose a landing pad located inside of a substrate.
However, it is well known in the art to form heater elements in phase change memory semiconductor structures on top of landing pads inside of substrates (landing pad 130 inside substrate 120 in Fig. 8 of Ok).
There is a benefit to such a configuration in that it allows for electricity to be applied to the heater.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung to use a substrate with a landing pad inside of the substrate as taught by Ok for this benefit.
Lung in view of Ok does not disclose at least one lateral conductive metal layer disposed in this version of the stack.
However, it is well known in the art to form a lateral conductive metal layer between chalcogenide layers in a phase change memory device (additional top electrode (ATE) in Fig. 2a of Kim).
There is a benefit to using lateral conductive metal layers between chalcogenide layers in a phase change memory device in that it results in better amorphization (second column of Page 1484 of Kim).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok to insert a lateral conductive metal layer into the stack as taught by Kim for this benefit.
Lung does not disclose a hard mask outward of said top electrode; a second dielectric disposed on sides of said stack and an upper surface of said hard mask; or a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode.
Lin, in the same field of endeavor, discloses a phase change memory structure with a hard mask (“hard mask 122” in Fig. 1A, ¶ 0015) outward of a top electrode (“top electrode 120”, ¶ 0015);
a second dielectric (“upper portion 106b of the dielectric structure”, ¶ 0016) disposed on sides of a stack and an upper surface of said hard mask; and
a top electrical contact (“via 126”, ¶ 0016) penetrating said hard mask and said second dielectric and connected to said top electrode. There was a benefit to forming the hard mask, the second dielectric, and the top electrical contact as it allows for an electrical pathway to the top electrode while protecting the remaining structures. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a hard mask outward of said top electrode of Lung; a second dielectric disposed on sides of said stack of Lung and an upper surface of said hard mask; and a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode for this benefit.
Regarding claim 5, with regards to where to insert the lateral conductive metal layer of Kim, there is a benefit to putting it between chalcogenides of different dopant profiles in that it can be applied between the deposition steps of the different chalcogenide layers rather than pause the deposition process of a single chalcogenide layer, deposit the metal layer, and then resume the original chalcogenide deposition before moving on to depositing the remaining chalcogenide layers which adds an extra processing step.
With regards to between which two of the three chalcogenide layers the metal layer is inserted, there is a finite number of possibilities: between the inner undoped chalcogenide layer and the doped chalcogenide layer or between the doped chalcogenide layer and the outer undoped chalcogenide layer.
One having ordinary skill in the art could have inserted it between the inner undoped chalcogenide layer and the doped chalcogenide layer with a reasonable expectation of success and, as such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to form the lateral conductive metal layer between the inner undoped chalcogenide layer and the doped chalcogenide layer.
Regarding claim 6, Lung discloses a second lateral conductive metal layer (although not shown in Fig. 1, the text of Lung discloses that two additional undoped layers of phase change material may be located over the doped chalcogenide layer; the one farther from the doped chalcogenide layer constituting the lateral conductive metal layer; ¶ 0030) located outward of said outer undoped chalcogenide layer.
Regarding claim 17, Lung discloses a phase change memory semiconductor array (Fig. 10) comprising:
a plurality of word lines (¶ 0063);
a plurality of bit lines intersecting said plurality of word lines at a plurality of cell locations (¶ 0063);
a plurality of access devices, controlled by the word lines, at said plurality of cell locations (¶ 0051),
a plurality of phase change memory cells located at said plurality of cell locations, each of said phase change memory cells comprising:
a dielectric (130 in Fig. 1);
a heater (120) located in the dielectric;
a stack including an inner undoped chalcogenide layer (112) outward of the dielectric, a doped chalcogenide layer (114) outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer (although not shown in Fig. 1, the text of Lung discloses that an additional undoped layer of phase change material may be located over the doped chalcogenide layer; ¶ 0030).
Lung does not disclose a landing pad located inside of a substrate.
However, it is well known in the art to form heater elements in phase change memory semiconductor structures on top of landing pads inside of substrates (landing pad 130 inside substrate 120 in Fig. 8 of Ok).
There is a benefit to such a configuration in that it allows for electricity to be applied to the heater.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung to use a substrate with a landing pad inside of the substrate as taught by Ok for this benefit.
Other than the top electrode 140, Lung in view of Ok does not disclose at least one lateral conductive metal layer associated with the stack.
However, it is well known in the art to form a lateral conductive metal layer between chalcogenide layers in a phase change memory device (additional top electrode (ATE) in Fig. 2a of Kim).
There is a benefit to using lateral conductive metal layers between chalcogenide layers in a phase change memory device in that it results in better amorphization (second column of Page 1484 of Kim).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok to dispose a lateral conductive metal layer in the stack as taught by Kim for this benefit.
Lung does not disclose a hard mask outward of said top electrode; a second dielectric disposed on sides of said stack and an upper surface of said hard mask; or a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode.
Lin, in the same field of endeavor, discloses a phase change memory structure with a hard mask (“hard mask 122” in Fig. 1A, ¶ 0015) outward of a top electrode (“top electrode 120”, ¶ 0015);
a second dielectric (“upper portion 106b of the dielectric structure”, ¶ 0016) disposed on sides of a stack and an upper surface of said hard mask; and
a top electrical contact (“via 126”, ¶ 0016) penetrating said hard mask and said second dielectric and connected to said top electrode. There was a benefit to forming the hard mask, the second dielectric, and the top electrical contact as it allows for an electrical pathway to the top electrode while protecting the remaining structures. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a hard mask outward of said top electrode of Lung; a second dielectric disposed on sides of said stack of Lung and an upper surface of said hard mask; and a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode for this benefit.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1) and Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9) as applied to claim 6, above, and further in view of Redaelli et al. (EP 2,034,536 B1).
Regarding claim 7, Lung in view of Ok, Lin, and Kim does not disclose a sidewall layer as claimed.
However, it is well known in the art to provide sidewall layers in phase change memory semiconductor structures (sidewall layer 52 in Fig. 5 of Redaelli).
There is a benefit to sidewall layers in that they provide physical protection to the memory cell.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok and Kim to form a sidewall layer at least on sides of said stack as taught be Redaelli for this benefit.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1), and Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9) as applied to claim 1, above, and further in view of Redaelli et al. (EP 2,034,536 B1).
Regarding claim 8, Lung in view of Ok, Lin, and Kim disclose the method of claim 11, as discussed above. Kim further discloses that the at least one lateral conductive metal layer is formed between chalcogenide layers (Fig. 2a of Kim shows a lateral additional top electrode (ATE) metal layer between two chalcogenide layers (GST1 and GST2)). As such, in the method of the combination, the at least one lateral conductive material layer will be formed between the inner undoped chalcogenide layer and the doped chalcogenide layer.
Lung in view of Ok and Kim does not disclose the inclusion of an all-around projection liner as claimed.
However, it was known in the art to form all-around projection liners between heaters and phase change materials in phase change memory semiconductor structures (all-around projection liner 11 in Fig. 5 of Redaelli).
There is a benefit to including an all-around projection liner in that is allows for easier detection of the difference in resistance between programmed states (¶ 0020 of Redaelli).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok and Kim to form an all-around projection liner located between the inner undoped chalcogenide layer and the heater element as taught by Redaelli for this benefit.
Regarding claim 9, Lung in view of Ok, Lin, Kim, and Redealli further discloses a second lateral conductive metal layer (140 in Fig. 1 of Lung, ¶ 0030) located outward of said outer undoped chalcogenide layer.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1), Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9) and Redaelli et al. (EP 2,034,536 B1) as applied to claim 8, above, and further in view of Lai et al. (US 9,537,093 B1).
Regarding claim 10, Lung in view of Ok, Kim, and Redaelli does not disclose a sidewall layer as claimed.
Lai discloses a sidewall layer (216A in Fig. 4B) disposed on sides of a stack, said sidewall layer providing a current path. There was a benefit to forming a sidewall layer as such in that it aids in providing stable resistance and stable operating efficiency (Col. 2, Lines 35-36 of Lai).
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a sidewall layer as taught by Lai along the entirety of the stack in the structure of the combination for this benefit. In the resulting configuration, the sidewall layer will extend outward from the dielectric, exposed at least a portion of said hard mask, contact the all-around projection liner, the second lateral conductive metal layer, and the top electrode.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1), and Kim et al. (“One-Dimensional Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) Using a Pseudo 3-Terminal Device”, IEEE transactions on electron devices, 2011 Apr. 5; 58(5):1483-9) as applied to claim 17, above, and further in view of Kim et al. (US 10,381,074 B1; hereinafter ‘074).
Regarding claim 18, Lung in view of Ok, Lin and Kim does not disclose that the phase change memory semiconductor array comprises control circuitry coupled to said word lines and said bit lines and configured to cause weights of a neural network to be stored in the plurality of phase change memory cells.
However, it was known that phase-change memory cells may be used with control circuitry to store the weights of a neural network (Col. 4, Lines 18-37 and Col. 6, Line 41 of ‘074).
There is a benefit to using the phase change memory semiconductor array of the combination of Lung, Ok, Lin, and Kim to store the weights of a neural network as taught by ‘074 in that the memory cells will have a lower failure rate due to the lack of oxidation at electrodes (Abstract of Lung).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok and Kim to use the phase change memory semiconductor array with control circuitry coupled to said word lines and said bit lines and configured to cause weights of a neural network to be stored in the plurality of phase change memory cells as taught by ‘074 for this benefit.
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 19 further limits the structure of the device of claim 18 by requiring two adjacent cells of said plurality of phase change memory cells share their stacks to form a continuous unitary stack; each cell of said two adjacent cells further comprises an individual patterned projection liner located between said inner undoped chalcogenide layer and said heater element; and the continuous unitary stack further includes a sidewall layer left of a leftmost one of said cells and right of a rightmost one of said cells and exposing at least a portion of said sides of said stack, said sidewall layer extending outward from said dielectric portion, contacting said at least one lateral conductive metal layer and said top electrode, and providing a current path. These features, when combined with the features of claims 17 and 18, are neither taught by nor obvious over the prior art of record.
Response to Arguments
Applicant's arguments filed 9/8/2025 have been fully considered but they are not persuasive.
Applicant argues that the previously cited prior art does not disclose the limitations of a hard mask outward of said top electrode, a second dielectric disposed on sides of said stack and an upper surface of said hard mask; and a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode. This argument is not persuasive as these features are taught by newly cited prior art reference Lin, as discussed above.
Regarding claim 4, Applicant further argues that the conductive spacers 216A and 216B of Lai do not extend outward from the dielectric. This argument is not persuasive as the width of phase change layer 222 of Lai is not commensurate with the width of the stack. However, the phase change layer of Lung is a portion of the stack of Lung. As such, in the device of the combination, when the conductive spacers are formed along the sides of the stack, the conductive spacers will reach the dielectric layer and, therefore extend outward from the dielectric.
Further regarding claim 4, Applicant argues that the conductive spacers do not expose at least a portion of the sides of the stack, “For example, as illustrated in Fig. 9 of the present application, a portion of the hard mask 235 may be exposed”. This argument is not persuasive as Applicant’s hard mask is a distinct component from the claimed stack (see claim 1, from which claim 4 depends). As such, “exposing at least a portion of said sides of said stack” is interpreted to be consistent with Applicant’s disclosure in that it allows for the top side portion of the stack to be “exposed” in that they may be directly contacted by other components. As the top side portion of the stack in the device of the combination is exposed to allow direct contact by other components, the claim limitation is met.
Further regarding claims 1 and 17, Applicant argues that in the combination of Lung, Ok, and Kim, there is no hard mask component in the final form of the device. This argument is not persuasive as newly cited reference Lin discloses this feature.
Applicant’s arguments regarding claim 11 and claims dependent therefrom (claims 12-16) are moot as these claims are withdrawn pursuant to Applicant’s election filed 12/01/2025.
Further regarding claim 10, Applicant argues that the conductive spacers do not expose at least a portion of the sides of the stack, “For example, as illustrated in Fig. 9 of the present application, a portion of the hard mask 235 may be exposed”. This argument is not persuasive as Applicant’s hard mask is a distinct component from the claimed stack (see claim 1, from which claim 4 depends). As such, “exposing at least a portion of said sides of said stack” is interpreted to be consistent with Applicant’s disclosure in that it allows for the top side portion of the stack to be “exposed” in that they may be directly contacted by other components. As the top side portion of the stack in the device of the combination is exposed to allow direct contact by other components, the claim limitation is met.
Applicant’s arguments concerning claim 19 are persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.C/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815