Prosecution Insights
Last updated: July 17, 2026
Application No. 17/493,813

ARTIFICIAL INTELLIGENCE (AI) DEVICES WITH IMPROVED THERMAL STABILITY AND SCALING BEHAVIOR

Non-Final OA §103
Filed
Oct 04, 2021
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
5 (Non-Final)
42%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
49%
With Interview

Examiner Intelligence

Grants 42% of resolved cases
42%
Career Allowance Rate
144 granted / 341 resolved
-25.8% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
43 currently pending
Career history
416
Total Applications
across all art units

Statute-Specific Performance

§103
82.1%
+42.1% vs TC avg
§102
11.3%
-28.7% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 341 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/22/2026 has been entered. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1), Applicant’s admitted prior art (hereinafter AAPA) and Redaelli et al. (EP 2,034,536 B1). Regarding claim 1, Lung discloses a phase change memory semiconductor structure (Fig. 1) comprising: a dielectric (130); a heater (120) located in the dielectric; a stack including an inner undoped chalcogenide layer (112) outward of the dielectric, a doped chalcogenide layer (114) outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer (although not shown in Fig. 1, the text of Lung discloses that two additional undoped layers of phase change material may be located over the doped chalcogenide layer; the one closer to the doped chalcogenide layer constituting the outer undoped chalcogenide layer; ¶ 0030); and a second lateral conductive metal layer located outward of the outer undoped chalcogenide layer (although not shown in Fig. 1, the text of Lung discloses that two additional undoped layers of phase change material may be located over the doped chalcogenide layer 114; the one farther from the doped chalcogenide layer constituting the lateral conductive metal layer; ¶ 0030); and a top electrode (140; ¶ 0030) outward of the outer undoped chalcogenide layer. Lung does not disclose a landing pad located inside of a substrate. However, it is well known in the art to form heater elements in phase change memory semiconductor structures on top of landing pads inside of substrates (landing pad 130 inside substrate 120 in Fig. 8 of Ok). There is a benefit to such a configuration in that it allows for electricity to be applied to the heater. It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the substrate of Lung to use a landing pad inside of the substrate as taught by Ok for this benefit. Lung does not disclose a hard mask outward of said top electrode; a second dielectric disposed on sides of said stack and an upper surface of said hard mask; or a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode. Lin, in the same field of endeavor, discloses a phase change memory structure with a hard mask (“hard mask 122” in Fig. 1A, ¶ 0015) outward of a top electrode (“top electrode 120”, ¶ 0015); a second dielectric (“upper portion 106b of the dielectric structure”, ¶ 0016) disposed on sides of a stack and an upper surface of said hard mask; and a top electrical contact (“via 126”, ¶ 0016) penetrating said hard mask and said second dielectric and connected to said top electrode. There was a benefit to forming the hard mask, the second dielectric, and the top electrical contact as it allows for an electrical pathway to the top electrode while protecting the remaining structures. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a hard mask outward of said top electrode of Lung; a second dielectric disposed on sides of said stack of Lung and an upper surface of said hard mask; and a top electrical contact penetrating said hard mask and said second dielectric and connected to said top electrode for this benefit. Lung does not disclose a first lateral conductive metal layer located between the inner undoped chalcogenide layer and the doped chalcogenide layer. Forming a first lateral conductive metal layer as such was well-known in the art (component 109 in Fig. 1 of Applicant’s Drawing which are designated as prior art). There was a benefit to such a layer in that it spreads the heat (¶ 0006 of Applicant’s Specification). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to include a first lateral conductive metal layer located between the inner undoped chalcogenide layer and the doped chalcogenide layer of Lung for this benefit. Lung in view of Ok, Lin, and AAPA does not disclose the inclusion of an all-around projection liner as claimed. However, it was known in the art to form all-around projection liners between heaters and phase change materials in phase change memory semiconductor structures (11 in Fig. 5 of Redaelli). There is a benefit to including an all-around projection liner in that is allows for easier detection of the difference in resistance between programmed states (¶ 0020 of Redaelli). It would have been obvious to one having ordinary skill in the art before the effective filing date of the Application to modify the device of Lung in view of Ok, Lin, and AAPA to form an all-around projection liner located between the inner undoped chalcogenide layer and the heater element as taught by Redaelli for this benefit. Claim(s) 4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (US 2017/0263863 A1) in view of Ok et al. (US 10,741,756 B1), Lin et al. (US 2020/0279998 A1), Applicant’s admitted prior art (hereinafter AAPA) and Redaelli et al. (EP 2,034,536 B1) as applied to claim 1, above, and further in view of Lai et al. (US 9,537,093 B1). Regarding claim 4, Lung in view of Ok, Lin, AAPA, and Redaelli does not disclose a sidewall layer as claimed. Lai discloses a sidewall layer (216A in Fig. 4B) disposed on sides of a stack, said sidewall layer providing a current path. There was a benefit to forming a sidewall layer as such in that it aids in providing stable resistance and stable operating efficiency (Col. 2, Lines 35-36 of Lai). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a sidewall layer as taught by Lai along the entirety of the stack in the structure of the combination for this benefit. In the resulting configuration, the sidewall layer will extend outward from the dielectric and contact the top electrode. Regarding claim 10, Lung in view of Ok, Lin, AAPA, and Redaelli does not disclose a sidewall layer as claimed. Lai discloses a sidewall layer (216A in Fig. 4B) disposed on sides of a stack, said sidewall layer providing a current path. There was a benefit to forming a sidewall layer as such in that it aids in providing stable resistance and stable operating efficiency (Col. 2, Lines 35-36 of Lai). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a sidewall layer as taught by Lai along the entirety of the stack in the structure of the combination for this benefit. In the resulting configuration, the sidewall layer will extend outward from the dielectric, exposed at least a portion of said hard mask, contact the all-around projection liner, the second lateral conductive metal layer, and the top electrode. Allowable Subject Matter Claims 17 and 18 are allowed. The following is an examiner’s statement of reasons for allowance: claim 17 has been amended to include the limitations of previously presented claim 19 which was noted as allowable in the Final Rejection mailed 3/23/2026 and is allowed for the same reasons. Claim 18 depends from claim 17 and it, therefore, also allowed. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in view of the teachings of AAPA. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Show 9 earlier events
Jul 14, 2025
Applicant Interview (Telephonic)
Jul 14, 2025
Examiner Interview Summary
Sep 08, 2025
Response Filed
Mar 23, 2026
Final Rejection mailed — §103
May 22, 2026
Response after Non-Final Action
Jun 18, 2026
Request for Continued Examination
Jun 24, 2026
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
42%
Grant Probability
49%
With Interview (+6.8%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 341 resolved cases by this examiner. Grant probability derived from career allowance rate.

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