Detailed Action
This office action is in response to the amendment filed on June 25th, 2026. Claims 1-20 are pending. Claims 15-20 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed June 25th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 7-8, “Remarks”) that Yao fails to teach the limitations presented in amended Claim 1.
However, as seen below, Claim 1 is now rejected by the combination of Yao, Kuo, and Yang.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Objections
Claim 1 is objected to because of the following informalities:
The claim recites the limitation “each the plurality of interconnect lines” in line 3. The limitation will be interpreted as “each of the plurality of interconnect lines”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-7 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (10,847,417 B1; hereinafter Yao) in view of Kuo et al. (2015/0132948 A1; hereinafter Kuo) and Yang et al. (2013/0277853 A1; hereinafter Yang).
Regarding Claim 1, Yao (fig. 10) teaches an interconnect structure (Col. 9, Lines 38-51; 200) comprising:
a plurality of interconnect lines (Col. 9, Lines 52-60; plurality of 212) formed in a dielectric layer (Col. 9, Lines 52-60; 204) of a semiconductor device (Col. 9, Lines 31-51; 200 may correspond to an IC device 10), wherein
the dielectric layer separates each the plurality of interconnect lines from a substrate, wherein each of the plurality of interconnect lines includes a metal cap deposited on a top surface;
a first dielectric cap (Col. 12, Lines 16-36; 230) formed between each interconnect line of the plurality of interconnect lines (plurality of 212); and
a second dielectric cap (Col. 12, Lines 22-36; 242) formed on top of the plurality of interconnect lines (plurality of 212) and the first dielectric cap (230), wherein the second dielectric cap (242) formed on top of the first dielectric cap (230) forms a bi-layer dielectric cap (stack of 242 and 230) between the plurality of interconnect lines (plurality of 212).
Yao doesn’t teach the dielectric layer separates each the plurality of interconnect lines from a substrate.
However, Kuo (fig. 10) teaches the dielectric layer ([0021], 204) separates each the plurality of interconnect lines ([0023], 208 formed in 206) from a substrate ([0021], 202). Kuo also teaches that this provides an interconnect that fulfills the operation of a single layer interconnection.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the interconnect structure of Yao to include the dielectric layer and interconnect line spacing of Kuo to provide a single layer interconnection.
Yao doesn’t teach each of the plurality of interconnect lines includes a metal cap deposited on a top surface.
However, Yang (fig. 9) teaches each of the plurality of interconnect lines ([0023], 120) includes a metal cap ([0026], 124) deposited on a top surface (top surface of 120). Yang also teaches the capping layer improves electromigration characteristics of the conductive material ([0026]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the interconnect structure of Yao to include the metal cap of Yang to improve electromigration characteristics.
Regarding Claim 2, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the plurality of interconnect lines are formed of copper (Cu) (Col. 10, Lines 42-46; the plurality of 212 may be Cu).
Regarding Claim 3, Yao doesn’t teach the interconnect structure of claim 1, wherein the first dielectric cap has a high voltage breakdown (Vbd).
However, Yang (fig. 8) teaches the first dielectric cap ([0019], 110) has a high voltage breakdown (Vbd) ([0019], 110 may be SiCN) (Applicant’s specification defines SiCN as being a dielectric material with a high voltage breakdown). Yang also teaches that SiCN improves TDDB results by preventing material contamination and the high carbon content of the SiCN improves VBD results ([0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the interconnect structure of Yao to include the SiCN of Yang to further improve VBD and TDDB results.
Regarding Claim 4, Yang (fig. 8) teaches the interconnect structure of claim 3, wherein the first dielectric cap material is silicon carbonitride (SiCN) ([0019], 110 may be SiCN).
Regarding Claim 5, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the second dielectric cap has a high etch stop capability (Col. 12, Lines 22-36; 242 is defined to be an ESL, or etch stop layer).
Regarding Claim 6, Yao (fig. 10) teaches the interconnect structure of claim 5, wherein the second dielectric cap material is aluminum oxide (AlOx) (Col. 13, Lines 32-49; 242 may be aluminum oxide).
Regarding Claim 7, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the dielectric layer is a low-k dielectric constant material (Col. 10, Lines 15-38; 204 may be a low-k dielectric material).
Regarding Claim 11, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the bi-layer dielectric cap (stack of 242 and 230) between the plurality of interconnect lines (plurality of 212) prevents micro-trenching in case of a misalignment between a via and a line (Col. 16, Lines 14-37; the dielectric features mitigates misalignment).
Regarding Claim 12, Yao (fig. 10) teaches the interconnect structure of claim 11, wherein preventing micro-trenching exhibits improved Vbd performance due to increased space between the via and an adjacent line (Col. 16, Lines 14-37; the mitigation of misalignment improves device reliability with respect to VBD).
Regarding Claim 13, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the bi-layer dielectric cap (stack of 242 and 230) between the plurality of interconnect lines (plurality of 212) exhibits better Time-Dependent Dielectric Breakdown (TDDB) performance (Col. 16, Lines 14-37; the mitigation of misalignment improves device reliability with respect to TDDB).
Regarding Claim 14, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the second dielectric cap (242) forms a conventional blanket dielectric cap (Col. 13, Lines 32-49; 242 is deposited over 204, see fig. 7) on a top surface of the plurality of interconnect lines (plurality of 212).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yao, Kuo, and Yang as applied to Claim 1 above, and further in view of Ishizaka et al. (2013/0252417 A1; hereinafter Ishizaka).
Regarding Claim 8, Yao (fig. 10) teaches the interconnect structure of claim 1,
wherein the plurality of interconnect lines (plurality of 212) formed in the dielectric layer (204) of the semiconductor device comprises: a cut (Col. 10, Lines 42-51; openings where each of the plurality of 212 are formed in) etched in the dielectric layer (204) for each interconnect line of the plurality of interconnect lines (plurality of 212);
a barrier material deposited on a first exposed surfaces of the cut etched in the dielectric layer for each interconnect line; a liner material deposited on a second exposed surfaces of the barrier;
and the cut filled by depositing copper to fill the cut (Col. 10, Lines 42-51; openings are filled with suitable conductive material such as copper) etched in the dielectric layer (204) for each interconnect line of the plurality of interconnect lines (plurality of 212).
Yao doesn’t teach a barrier material deposited on a first exposed surfaces of the cut etched in the dielectric layer for each interconnect line; a liner material deposited on a second exposed surfaces of the barrier.
However, Ishizaka (figs. 1A-H) teaches a barrier material ([0032], 10) deposited on a first exposed surfaces of the cut ([0031], barrier 10 is formed inside recess 8, see fig. 1B) etched in the dielectric layer ([0027], 6) for each interconnect line ([0035], 16, see fig. 1H); a liner material ([0033], 12, see fig. 1C) deposited on a second exposed surfaces ([0033], liner 12 is formed on barrier 10) of the barrier (10). Ishizaka also teaches that barrier layers help prevent diffusion into the metal ([0004]) and that liner layers improve adhesivity with a filling metal ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the interconnect structure of Yao to include the barrier and liner layers of Ishizaka to prevent diffusion into the metal and improve adhesivity with the filling metal.
Regarding Claim 9, Ishizaka (figs. 1A-H) teaches the interconnect structure of claim 8, wherein the barrier material is Tantalum nitride (TaN) ([0004], barrier layers may be TaN).
Regarding Claim 10, Yao (fig. 10) teaches the interconnect structure of claim 8, wherein the liner material is Ruthenium (Ru) ([0005], liner layers may be ruthenium when copper is used as the filling metal).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liou et al. (2015/0021779 A1) teaches an interconnect structure spaced from a substrate with a metal cap.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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