Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on February 25th, 2026, is acknowledged.
Claims 15-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 25th, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 10th, 2021, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-7, and 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao et al. (10,847, 417 B1; hereinafter Yao).
Regarding Claim 1, Yao (fig. 10) teaches an interconnect structure (Col. 9, Lines 38-51; 200) comprising:
a plurality of interconnect lines (Col. 9, Lines 52-60; plurality of 212) formed in a dielectric layer (Col. 9, Lines 52-60; 204) of a semiconductor device (Col. 9, Lines 31-51; 200 may correspond to an IC device 10);
a first dielectric cap (Col. 12, Lines 16-36; 230) formed between each interconnect line of the plurality of interconnect lines (plurality of 212); and
a second dielectric cap (Col. 12, Lines 22-36; 242) formed on top of the plurality of interconnect lines (plurality of 212) and the first dielectric cap (230), wherein the second dielectric cap (242) formed on top of the first dielectric cap (230) forms a bi-layer dielectric cap (stack of 242 and 230) between the plurality of interconnect lines (plurality of 212).
Regarding Claim 2, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the plurality of interconnect lines are formed of copper (Cu) (Col. 10, Lines 42-46; the plurality of 212 may be Cu).
Regarding Claim 5, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the second dielectric cap has a high etch stop capability (Col. 12, Lines 22-36; 242 is defined to be an ESL, or etch stop layer).
Regarding Claim 6, Yao (fig. 10) teaches the interconnect structure of claim 5, wherein the second dielectric cap material is aluminum oxide (AlOx) (Col. 13, Lines 32-49; 242 may be aluminum oxide).
Regarding Claim 7, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the dielectric layer is a low-k dielectric constant material (Col. 10, Lines 15-38; 204 may be a low-k dielectric material).
Regarding Claim 11, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the bi-layer dielectric cap (stack of 242 and 230) between the plurality of interconnect lines (plurality of 212) prevents micro-trenching in case of a misalignment between a via and a line (Col. 16, Lines 14-37; the dielectric features mitigates misalignment).
Regarding Claim 12, Yao (fig. 10) teaches the interconnect structure of claim 11, wherein preventing micro-trenching exhibits improved Vbd performance due to increased space between the via and an adjacent line (Col. 16, Lines 14-37; the mitigation of misalignment improves device reliability with respect to VBD).
Regarding Claim 13, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the bi-layer dielectric cap (stack of 242 and 230) between the plurality of interconnect lines (plurality of 212) exhibits better Time-Dependent Dielectric Breakdown (TDDB) performance (Col. 16, Lines 14-37; the mitigation of misalignment improves device reliability with respect to TDDB).
Regarding Claim 14, Yao (fig. 10) teaches the interconnect structure of claim 1, wherein the second dielectric cap (242) forms a conventional blanket dielectric cap (Col. 13, Lines 32-49; 242 is deposited over 204, see fig. 7) on a top surface of the plurality of interconnect lines (plurality of 212).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yao as applied to Claim 1 above, and further in view of Yang et al. (2013/0277853 A1; hereinafter Yang)
Regarding Claim 3, Yao doesn’t teach the interconnect structure of claim 1, wherein the first dielectric cap has a high voltage breakdown (Vbd).
However, Yang (fig. 8) teaches the first dielectric cap ([0019], 110) has a high voltage breakdown (Vbd) ([0019], 110 may be SiCN) (Applicant’s specification defines SiCN as being a dielectric material with a high voltage breakdown). Yang also teaches that SiCN improves TDDB results by preventing material contamination and the high carbon content of the SiCN improves VBD results ([0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the interconnect structure of Yao to include the SiCN of Yang to further improve VBD and TDDB results.
Regarding Claim 4, Yang (fig. 8) teaches the interconnect structure of claim 3, wherein the first dielectric cap material is silicon carbonitride (SiCN) ([0019], 110 may be SiCN).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yao as applied to Claim 1 above, and further in view of Ishizaka et al. (2013/0252417 A1; hereinafter Ishizaka).
Regarding Claim 8, Yao (fig. 10) teaches the interconnect structure of claim 1,
wherein the plurality of interconnect lines (plurality of 212) formed in the dielectric layer (204) of the semiconductor device comprises: a cut (Col. 10, Lines 42-51; openings where each of the plurality of 212 are formed in) etched in the dielectric layer (204) for each interconnect line of the plurality of interconnect lines (plurality of 212);
a barrier material deposited on a first exposed surfaces of the cut etched in the dielectric layer for each interconnect line; a liner material deposited on a second exposed surfaces of the barrier;
and the cut filled by depositing copper to fill the cut (Col. 10, Lines 42-51; openings are filled with suitable conductive material such as copper) etched in the dielectric layer (204) for each interconnect line of the plurality of interconnect lines (plurality of 212).
Yao doesn’t teach a barrier material deposited on a first exposed surfaces of the cut etched in the dielectric layer for each interconnect line; a liner material deposited on a second exposed surfaces of the barrier.
However, Ishizaka (figs. 1A-H) teaches a barrier material ([0032], 10) deposited on a first exposed surfaces of the cut ([0031], barrier 10 is formed inside recess 8, see fig. 1B) etched in the dielectric layer ([0027], 6) for each interconnect line ([0035], 16, see fig. 1H); a liner material ([0033], 12, see fig. 1C) deposited on a second exposed surfaces ([0033], liner 12 is formed on barrier 10) of the barrier (10). Ishizaka also teaches that barrier layers help prevent diffusion into the metal ([0004]) and that liner layers improve adhesivity with a filling metal ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the interconnect structure of Yao to include the barrier and liner layers of Ishizaka to prevent diffusion into the metal and improve adhesivity with the filling metal.
Regarding Claim 9, Ishizaka (figs. 1A-H) teaches the interconnect structure of claim 8, wherein the barrier material is Tantalum nitride (TaN) ([0004], barrier layers may be TaN).
Regarding Claim 10, Yao (fig. 10) teaches the interconnect structure of claim 8, wherein the liner material is Ruthenium (Ru) ([0005], liner layers may be ruthenium when copper is used as the filling metal).
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 25, 2026
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