DETAILED ACTION
This Office action is in response to the Amendment filed on 08 September 2025. Claims 1-15 and 17-26 are pending in the application. Claims 1-9 and 18-26 are withdrawn from consideration. Claim 16 has been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable Krivokapic et al., US 6,512,273, in view of Lindsay et al., US 2009/0042359, both of record.
With respect to claim 10, Krivokapic et al. disclose a method for fabricating a semiconductor device, shown in Fig. 1 (“FIG. 1 is a flow chart describing process flow for the formation of the inventive structure.”), the method comprising:
forming an N-type source/drain region (steps 58 and 60) and a P-type source/drain region (step 54) in a substrate 2, as shown in Fig. 2B;
forming an interlayer insulating layer on the substrate 2 (step 50), see column 4, lines 53-56 (”In step 50, silicon nitride spacers 20 are formed for both n-channel and p-channel gate sidewalls, by depositing 500-700 Å nitride, then etching back to the top gate surfaces leaving nitride spacers.”);
forming contact holes respectively exposing the N-type source/drain region and the P- type source/drain region by etching the interlayer insulating layer (step 50), see column 4, lines 53-56 (”In step 50, silicon nitride spacers 20 are formed for both n-channel and p-channel gate sidewalls, by depositing 500-700 Å nitride, then etching back to the top gate surfaces leaving nitride spacers.” Since the deposited nitride covered the N-type source/drain region and the P- type source/drain region, the subsequent etching step exposes the N-type source/drain region and the P- type source/drain region. The claim does not preclude the N-type source/drain region and the P- type source/drain region from being covered by another layer. );
performing a pre-annealing process on exposed surfaces of the N-type and P-type source/drain regions (step 63, “In step 63, RTA anneal is performed for 5-10 seconds at 1030-1060 C.“);
forming an N-type additional doped region within the pre-annealing N-type source/drain region by doping an N-type additional dopant in the pre-annealed N-type source/drain region after the pre-annealing process (step 74, “In step 74, n-channel LDD extension implant 36 is performed using P at 3-5 keV energy, 1-10e14 cm-2 dose, and 0.degree. tilt. The order of steps 72 and 74 is interchangeable.”);
forming a P-type additional doped region within the pre-annealed P-type source/drain region by doping a P-type additional dopant in the pre- annealed P-type source/drain region after the pre-annealing process (step 84, “ In step 84, p-channel S/D implant 37 is performed using BF2 at 10-30 keV energy, 2-4 e15 cm-2 dose, and 0.degree. tilt. In step 86, p-channel junction implant 39 is performed using B at 20-30 keV energy, 5e13-5e14 cm-2 dose, and 0.degree. tilt. The order of steps 84 and 86 is interchangeable.”);
performing a post-annealing process on exposed surface of the N-type and P- type additional doped regions (step 90); and
forming a metal silicide on each of the post-annealed N-type and P-type additional doped regions, see column 5, lines 34-38 (“In step 92 200-300 Angstroms silicon dioxide is deposited, then etched back to form a thin oxide spacer layer 34 which prevents subsequent silicidation of the poly spacers 33. The structure resultant from the performing of inventive steps 40-92 is shown in FIG. 2d. The wafer may then continue with standard CMOS processing including silicidation and metallization. The intermediate structures during the inventive process are shown in FIGS. 2a-2d.”).
Claim 10 requires “the pre-annealing process is performed by a rapid thermal process, and the post-annealing process is performed by a milli-second annealing for less than 1 second”. In the known method of Krivokapic et al., the pre-annealing process (step 63) is a rapid thermal process, as shown in Fig. 1 (”In step 63, RTA anneal is performed for 5-10 seconds at 1030-1060 C, see column 4, line 67, bridging column 5 to line 1.). However, in the known method of Krivokapic et al., although the post-annealing process (step 90} is a milli-second annealing (2000 to 5000 milli-seconds, as shown in Fig. 1), Krivokapic et al. lack anticipation only of the milli-second annealing being for less than 1 second. In the same field of endeavor, Lindsay et al. disclose a source/drain annealing process which comprises a rapid thermal anneal (RTA) performed at a temperature between about 900.degree. C. and about 1200.degree. C., for a time between about 0.1 milli-seconds and about 1 s, as disclosed in paragraph [0052]. Since both the anneals of Krivokapic et al. and Lindsay et al. are source/drain RTA processes, it would have been obvious to one of ordinary skill in the art that the source/drain post-annealing process of Krivokapic et al. disclosed in step 90 could be performed for less than 1 second, since Lindsay et al. disclose this time is sufficient for activating the dopants and forming the active junctions in the source/drain regions of a field effect transistor.
With respect to claim 11, as shown in Fig. 1, in the method of Krivokapic et al., the pre-annealing (step 63) and the post-annealing (step 90) processes include rapid thermal annealing, and wherein the pre-annealing process (step 63) is performed at a higher temperature than the post-annealing process (step 90).
With respect to claim 12, in the method of Krivokapic et al., the pre-annealing process is performed at a temperature reactivating the N-type and P-type source/drain regions, see column 2, lines 14-38.
With respect to claim 15, in the method of Krivokapic et al., after the exposing of the N-type and P-type source/drain regions to the pre-annealing process, wherein the N-type and the P-type source/drain regions have a carbon-free and a fluorine-free surface, since there is no carbon- or fluorine-containing material in contact with the N-type and P-type source/drain regions.
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable Krivokapic et al., US 6,512,273, in view of Lindsay et al., US 2009/0042359, both of record, as applied to claim 10 above.
With respect to claim 13, in the method of Krivokapic et al., the pre-annealing process (step 63) is performed at a temperature above 950°C, see Fig. 1. Although Krivokapic et al. disclose performing the post-annealing process at a temperature less than the pre-annealing temperature, as shown in Fig. 1, Krivokapic et al. lack anticipation of the post-annealing process (step 90) being performed at a temperature of 950°C or lower. Krivokapic et al. teach to perform the pre-annealing process at a temperature of 1030-1060 degrees Celsius and to perform the post-annealing process at a temperature of 990-1010 degrees Celsius, as shown in Fig. 1 It has been well established that optimization within prior art conditions is not inventive. Since Krivokapic et al. teach the general conditions of the pre- and post-annealing processes, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, Krivokapic et al. disclose the purpose and criteria for these annealing steps in column 2, lines 39-62. Therefore, optimization of the post-annealing temperature would have been clearly ascertainable by the skilled artisan through routine experimentation. Based on both of these arguments, Applicant’s claimed post-annealing temperature range of 950 oC or lower would have been prima facie obvious and is not deemed to patentably distinguish Applicant’s claimed method from the prior art method of Krivokapic et al.
Furthermore, the newly-cited reference to Lindsay et al. discloses that a source/drain anneal which comprises a rapid thermal anneal (RTA) performed at a temperature between about 900.degree. C. and about 1200.degree. C., see paragraph [0052]. Therefore, in light of the newly-cited reference to Lindsay et al., it would have been obvious to one of ordinary skill in the art that the post-annealing process of Krivokapic et al. could have been performed at a temperature of less than 950 oC or lower, since Lindsay et al. disclose that this temperature is sufficient for activating the dopants and forming the active junctions in the source/drain regions of a field effect transistor.
With respect to claim 17, Krivokapic et al. disclose that the pre-annealing process (Step 63) and the post-annealing process (Step 90) are performed at a temperature above 950 C, and wherein the post-annealing process (Step 90) is performed for a shorter time than the pre-annealing process (Step 63), as shown in Fig. 1. However, Krivokapic et al. lack anticipation of the post-annealing process (Step 90) being performed at a higher temperature than the pre-annealing process (Step 63). Krivokapic et al. disclose the purpose and criteria for these annealing steps in column 2, lines 39-62. Therefore, optimization of the post-annealing temperature would have been clearly ascertainable by the skilled artisan through routine experimentation. Furthermore, the post-annealing process can be performed at a temperature either higher or lower than the temperature of the pre-annealing process. It has been well established that an obvious to try rationale is acceptable to support a conclusion of obviousness. Consequently, it would have been obvious to the skilled artisan to try performing the post-annealing process at a higher temperature than the pre-annealing process in the known method of Krivokapic et al., since one skilled in the art would be choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) For these reasons, it would have been obvious to the skilled artisan to try performing the post-annealing process at a higher temperature than the pre-annealing process in the known method of Krivokapic et al. This limitation is not deemed to patentably distinguish Applicant’s claimed method from the prior art method of Krivokapic et al.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable Krivokapic et al., US 6,512,273, in view of Lindsay et al., US 2009/0042359, as applied to claim 10 above, further in view of Pfiester et al., US 4,835,112, all of record.
Krivokapic et al. are applied as above. Krivokapic et al. fail to teach forming of the P-type additional doped region includes sequentially performing germanium doping and boron-containing material doping on the pre-annealed P-type source/drain region. Pfiester et al. disclose a CMOS silicide process in which germanium is implanted before silicide formation to retard the diffusion of boron, see Figs. 3-8, and the Abstract. Therefore, in order to retard the diffusion of the p-type additional dopant in the known method of Krivokapic et al., it would have been obvious to the skilled artisan to form the P-type additional doped region by sequentially performing germanium doping and boron-containing material doping on the pre-annealed P-type source/drain region.
Response to Arguments
Applicant's arguments filed 08 September 2025 have been fully considered but they are not persuasive. Independent claim 10 has been amended and claims, inter alia, "forming an N-type additional doped region within the pre-annealed N-type source/drain region by doping an N-type additional dopant in the pre-annealed N-type source/drain region after the pre-annealing process; forming a P-type additional doped region within the pre-annealed P-type source/drain region by doping a P-type additional dopant in the pre-annealed P-type source/drain region after the pre-annealing process". In the above rejection, Krivokapic's first annealing step (step 63) reads on Applicant’s pre-annealing step, since this RTA anneal is performed after the p-channel LDD extension implant 26 (step 54) and the n-channel junction implant 24 and the n-channel S/D implant 22 (steps 58 and 60). After the pre-annealing step 63 of Krivokapic, the n- channel LDD extension implant 36 and the p-channel S/D implant 37 are performed (steps 74 and 84, respectively, in Fig. 1 of Krivokapic). Therefore, since Fig. 1 is a flow chart describing process flow for the formation of the inventive structure of Krivokapic, Krivokapic clearly teaches "forming an N-type additional doped region within the pre-annealed N-type source/drain region by doping an N-type additional dopant in the pre-annealed N-type source/drain region after the pre-annealing process; forming a P-type additional doped region within the pre-annealed P-type source/drain region by doping a P-type additional dopant in the pre-annealed P-type source/drain region after the pre-annealing process".
Applicant has argued that “Krivokapic's n-channel junction implant 24 is NOT included in Krivokapic's n-channel S/D implant 22, as well as Krivokapic's n-channel LDD extension implant 36 is NOT included in Krivokapic's n-channel junction implant 24. This argument is not found persuasive, since independent claim 10 only requires doping in the source/drain regions. The source/drain regions in the known method of Krivokapic are adjacent to gate electrode10. Therefore, since the dopants for all implants in the known method of Krivokapic are implanted into regions of the substrate adjacent the gate electrode 10, the n-channel junction implant 24 and the n-channel S/D implant 22 (steps 58 and 60), the n-channel LDD extension implant 36, and the p-channel S/D implant 37 are all doping in the pre-annealed N-type and P-type source/drain regions.
For the above reasons, amended claim 10 is not deemed to patentably distinguish Applicant’s claimed method from the known method of Krivokapic et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The newly cited reference to Mineji, US 2006/0199345, discloses a method for fabricating a semiconductor device which includes a pre-annealing step S103 (that is, the first heat treatment), as shown in Fig. 4..
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898