DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
6. Claims 1, 6, 10, 15, 19, 24, 28 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. Publication 2015/0324441) (Zhou hereinafter)in view of Ringseth (U.S. Publication 2012/0089961) (Ringseth hereinafter).
7. As per claim 1, Zhou teaches one or more processors comprising: circuitry to select one or more algorithms to perform one or more software kernels based, at least in part, on a structure of threads in a group that are to perform the one or more software kernels, the structure to determine how the threads are to communicate with one another [“This intelligent kernel selection algorithm approach encodes a fixed-kernel selection policy into a set of rules such that, given d and k, the best kernels can be determined efficiently. As examples, a few kernel selection rules are described below:” ¶ 0119; “simple rules can effectively produce the optimal selection policy (for Fermi GPUs) of when to choose the global-memory kernels ({AGT, UGT}) instead of the 6 shared-memory limited kernels. For example, this rule would pick the AGT kernel if d≧16 and k=400, because when d≧16 and k=400, the shared memory consumption of a single thread block for kernel fε{AS, AST, ASU, ASUT} is dk≧16×400=6400 floats=25 KB>48 KB/2, which means kernel f cannot run two thread blocks at the same time on a SM with only 48 KB of shared memory. On the other hand, if d≦15 and k=400, dk≦6000 floats≦48 KB/2. Thus, for k=400, 15 is the maximum value of d that allows two thread blocks of a shared-memory limited assignment kernel to run simultaneously on a SM. For the update kernels, setting the minimum-resident-blocks-per-SM to 3 would favor the UGT kernel when d≧10 and k=400, since the shared memory consumption of the {US, UST} kernels is dk+k≧10×400+400=4400 floats=17.2 KB per thread block, which is greater than one third (⅓) of the 48 KB shared memory on a SM. Thus, for k=400, 9 is the maximum value of d that allows three thread blocks of either the US or the UST kernel to run simultaneously on a SM. It can be verified that this is the optimal selection strategy for picking the UGT kernel. On the other hand, if the minimum-resident-blocks-per-SM constraint is satisfied, a shared-memory limited kernel would be preferred over a global-memory kernel. In the present k-means, there are multiple shared-memory limited kernels to choose from: {AS, AST, ASU, ASUT} for assignment, and {US, UST} for update,” ¶ 0120; kernel selection based on shared-memory or global-memory as the means for thread communication of elected kernels; minimum-resident-blocks-per-SM constraint suggests a limiting structure].
Zhao does not explicitly disclose but Ringseth discloses cause performance of the one or more software kernels in accordance with the one or more algorithms to be synchronized according to the structure of the threads in the group [“Whenever one thread needs the results of another thread from its own thread group, a synchronization barrier is inserted:” ¶ 0042; “group_barrier( ) which blocks all threads in a thread group until all have reached the barrier,” ¶ 0043; execution is controlled by thread dependence structure within the thread group].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou and Ringseth available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou to include the capability of thread group synchronization as taught by Ringseth, thereby providing a mechanism to enhance system efficiency by controlling execution multiple threads within a parallel processing architecture based on dependencies.
8. As per claim 6, Zhou and Ringseth teach the processor of claim 1. Zhou further teaches wherein the one or more software kernels are performed based at least in part on available communication mechanisms between individual threads of the threads [“simple rules can effectively produce the optimal selection policy (for Fermi GPUs) of when to choose the global-memory kernels ({AGT, UGT}) instead of the 6 shared-memory limited kernels. For example, this rule would pick the AGT kernel if d≧16 and k=400, because when d≧16 and k=400, the shared memory consumption of a single thread block for kernel fε{AS, AST, ASU, ASUT} is dk≧16×400=6400 floats=25 KB>48 KB/2, which means kernel f cannot run two thread blocks at the same time on a SM with only 48 KB of shared memory. On the other hand, if d≦15 and k=400, dk≦6000 floats≦48 KB/2. Thus, for k=400, 15 is the maximum value of d that allows two thread blocks of a shared-memory limited assignment kernel to run simultaneously on a SM. For the update kernels, setting the minimum-resident-blocks-per-SM to 3 would favor the UGT kernel when d≧10 and k=400, since the shared memory consumption of the {US, UST} kernels is dk+k≧10×400+400=4400 floats=17.2 KB per thread block, which is greater than one third (⅓) of the 48 KB shared memory on a SM. Thus, for k=400, 9 is the maximum value of d that allows three thread blocks of either the US or the UST kernel to run simultaneously on a SM. It can be verified that this is the optimal selection strategy for picking the UGT kernel. On the other hand, if the minimum-resident-blocks-per-SM constraint is satisfied, a shared-memory limited kernel would be preferred over a global-memory kernel. In the present k-means, there are multiple shared-memory limited kernels to choose from: {AS, AST, ASU, ASUT} for assignment, and {US, UST} for update,” ¶ 0120; shared-memory or global-memory as the available means for thread communication of elected kernels].
9. As per claim 10, it is a method claim having similar limitations as cited in claim 1. Thus, claim 10 is also rejected under the same rationale as cited in the rejection of claim 1 above.
10. As per claim 15, it is a method claim having similar limitations as cited in claim 6. Thus, claim 15 is also rejected under the same rationale as cited in the rejection of claim 6 above.
11. As per claim 19, it is a system claim having similar limitations as cited in claim 1. Thus, claim 19 is also rejected under the same rationale as cited in the rejection of claim 1 above.
12. As per claim 24, it is a system claim having similar limitations as cited in claim 6. Thus, claim 24 is also rejected under the same rationale as cited in the rejection of claim 6 above.
13. As per claim 28, it is a media claim having similar limitations as cited in claim 1. Thus, claim 28 is also rejected under the same rationale as cited in the rejection of claim 1 above.
14. As per claim 33, it is a media claim having similar limitations as cited in claim 6. Thus, claim 33 is also rejected under the same rationale as cited in the rejection of claim 6 above.
18. Claims 2, 11, 20 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Ringseth in view of Laine et al. (U.S. Publication 2009/0089542) (Laine hereinafter).
19. As per claim 2, Zhou and Ringseth teach the one or more processors of claim 1. Zhou and Ringseth do not explicitly disclose but Laine discloses wherein the one or more software kernels perform a scan operation on a series of numbers [“During the traversal of the array elements, a scan operation may be performed. In the context of the present description, the scan operation may refer to any operation that involves a current element and at least one previous element of the array (if available). In one embodiment, the scan operation may include an all-prefix-sums operation. More information regarding an exemplary all-prefix-sums operation will be set forth during the description of a different embodiment illustrated in FIG. 2.” ¶ 0016].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Laine available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou and Ringseth to include the capability of performing a scan operation as taught by Laine, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a parallel processing architecture.
20. As per claim 11, it is a method claim having similar limitations as cited in claim 2. Thus, claim 11 is also rejected under the same rationale as cited in the rejection of claim 2 above.
21. As per claim 20, it is a system claim having similar limitations as cited in claim 2. Thus, claim 20 is also rejected under the same rationale as cited in the rejection of claim 2 above.
22. As per claim 29, it is a media claim having similar limitations as cited in claim 2. Thus, claim 29 is also rejected under the same rationale as cited in the rejection of claim 2 above.
23. Claims 3, 4, 9, 12, 13, 18, 21, 22, 27, 30, 31 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Ringseth in view of Edwards (U.S. Publication 2021/0279837) (Edwards hereinafter) (Identified by Applicant in IDS).
24. As per claim 3, Zhou and Ringseth teach the one or more processors of claim 1. Zhou and Ringseth do not explicitly disclose but Edwards discloses wherein the one or more software kernels are performed based at least in part on whether the threads are assigned to a single core and are identified with contiguous identifiers [“a cooperative group (CG) 104, 106, 108 is a logical collection of interdependent threads, further described herein. In at least one embodiment, a CG 104, 106, 108 contains all threads 110 being executed on a single computational unit of a PPU, such as a GPU, or other processing units described herein,” ¶ 0053; “FIG . 2 is a block diagram illustrating a dynamic radix tree 200 for performing memory operations, according to at least one embodiment. In at least one embodiment, a dynamic radix tree 200 is an organizational data structure in memory, such as memory described herein. In at least one embodiment, a dynamic radix tree 200 is fully contained within a contiguous region of memory, such as scratch memory.” ¶ 0057].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Edwards available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou and Ringseth to include the capability of performing a scan operation as taught by Edwards, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a parallel processing architecture to reduce significant performance bottlenecks [Edwards ¶ 0002].
25. As per claim 4, Zhou and Ringseth teach the one or more processors of claim 1. Zhou does not explicitly disclose but Edwards discloses wherein the one or more software kernels are performed based at least in part on whether the threads are assigned to multiple cores and are identified with contiguous identifiers [“In at least one embodiment, one or more CGs 104, 106, 108 are executed in parallel on individual computational units, described below, of a PPU, such as a GPU, or other processing units described below. In at least one embodiment, one or more CGs 104, 106, 108 being executed in parallel perform memory operations 112, 114, 116 on a single scratch memory 102.” ¶ 0053; “FIG . 2 is a block diagram illustrating a dynamic radix tree 200 for performing memory operations, according to at least one embodiment. In at least one embodiment, a dynamic radix tree 200 is an organizational data structure in memory, such as memory described herein. In at least one embodiment, a dynamic radix tree 200 is fully contained within a contiguous region of memory, such as scratch memory.” ¶ 0057].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Edwards available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou and Ringseth to include the capability of performing a scan operation as taught by Edwards, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a parallel processing architecture to reduce significant performance bottlenecks [Edwards ¶ 0002].
26. As per claim 9, Zhou and Ringseth teach the one or more processors of claim 1. Zhou and Ringseth do not explicitly disclose but Edwards discloses wherein each kernel of the one or more software kernels corresponds to one or more different software algorithms that performs a scan operation [“In at least one embodiment, CUDA source code 3510 organizes thread blocks associated with a given kernel into a one-dimensional, a two-dimensional, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and a grid includes, without limitation, any number of thread blocks.” ¶ 0324].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Edwards available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou and Ringseth to include the capability of performing a scan operation as taught by Edwards, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a parallel processing architecture to reduce significant performance bottlenecks [Edwards ¶ 0002].
27. As per claim 12, it is a method claim having similar limitations as cited in claim 3. Thus, claim 12 is also rejected under the same rationale as cited in the rejection of claim 3 above.
28. As per claim 13, it is a method claim having similar limitations as cited in claim 4. Thus, claim 13 is also rejected under the same rationale as cited in the rejection of claim 4 above.
29. As per claim 18, it is a method claim having similar limitations as cited in claim 9. Thus, claim 18 is also rejected under the same rationale as cited in the rejection of claim 9 above.
30. As per claim 21, it is a system claim having similar limitations as cited in claim 3. Thus, claim 21 is also rejected under the same rationale as cited in the rejection of claim 3 above.
31. As per claim 22, it is a system claim having similar limitations as cited in claim 4. Thus, claim 22 is also rejected under the same rationale as cited in the rejection of claim 4 above.
32. As per claim 27, it is a system claim having similar limitations as cited in claim 9. Thus, claim 27 is also rejected under the same rationale as cited in the rejection of claim 9 above.
33. As per claim 30, it is a media claim having similar limitations as cited in claim 3. Thus, claim 30 is also rejected under the same rationale as cited in the rejection of claim 3 above.
34. As per claim 31, it is a media claim having similar limitations as cited in claim 4. Thus, claim 31 is also rejected under the same rationale as cited in the rejection of claim 4 above.
35. As per claim 36, it is a media claim having similar limitations as cited in claim 9. Thus, claim 38 is also rejected under the same rationale as cited in the rejection of claim 9 above.
36. Claims 5, 14, 23 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Ringseth in view of Mathiske et al. (U.S. Publication 2002/0194525) (Mathiske hereinafter).
37. As per claim 5, Zhou and Ringseth teach the one or more processors of claim 1. Zhou and Ringseth do not explicitly disclose but Mathiske discloses wherein the one or more software kernels are performed based at least in part on whether the threads are identified with non-contiguous identifiers [“FIG. 4 is a flow chart illustrating the actions of the modified program during recovery of a multi-threaded process in accordance with an embodiment of the present invention. The system first creates threads for all specified thread identifiers. This can be accomplished by creating threads for successive identifiers until a thread for a highest extracted identifier is reached (step 402). Next, the system disposes of threads that do not match any of the extracted identifiers (step 404). The above-described thread creation process can be used in operating systems for which creating a set of threads with non-contiguous identifiers is cumbersome. Furthermore, note that if threads cannot be explicitly disposed of through a system call, the system can simply cause newly created threads to execute a procedure that terminates quickly,” ¶ 0038].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Mathiske available before the effective filing date of the claimed invention, to modify the capability of parallel memory allocation as disclosed by Zhou and Ringseth to include the capability of allocating threads with non-contiguous identifiers as taught by Mathiske, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a variety of operating system environments.
38. As per claim 14, it is a method claim having similar limitations as cited in claim 5. Thus, claim 14 is also rejected under the same rationale as cited in the rejection of claim 5 above.
39. As per claim 23, it is a system claim having similar limitations as cited in claim 5. Thus, claim 23 is also rejected under the same rationale as cited in the rejection of claim 5 above.
40. As per claim 32, it is a media claim having similar limitations as cited in claim 5. Thus, claim 32 is also rejected under the same rationale as cited in the rejection of claim 5 above.
41. Claims 7, 16, 25 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Ringseth in view of Viitanen et al. (U.S. Publication 2021/0366177) (Viitanen hereinafter).
42. As per claim 7, Zhou and Ringseth teach the one or more processors of claim 1. Zhou and Ringseth do not explicitly disclose but Viitanen discloses wherein the circuitry is to receive, via an application programming interface, a request to perform a scan operation with a group of threads [“the compaction manager 116 may be configured to compact one or more of the compressed spans or groups of elements in the memory to recover storage from one or more gaps which may form in the memory—such as gap 132 in the memory 130. At compression time, a bitmask may be allocated that marks each output block, the number of set bits may be computed from the bitmask, and a prefix sum may be computed over the set bit counts. At compaction time, when copying a block to a new buffer, the compaction manager 116 (e.g., each worker thread or group of worker threads) may use the prefix sum and the bitmask values may be used to find a new position for a block. This may drop unused memory that is not needed to store the compressed elements. In some embodiments, compaction may be performed (e.g., after 312 in FIG. 3) based at least on an indicator and/or request from a user, such as in an API call used to build or refit the data structure. While compaction is described, this approach may be used for copy operations in general that involve one or more of the blocks.” ¶ 0062; prefix sum mapped to scan operation].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Viitanen available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou and Ringseth to include the capability of performing a scan operation via API call as taught by Viitanen, thereby providing a mechanism to enhance system maintainability by utilizing a construct frequently applied in the art to simply coding complexity and duplication.
43. As per claim 16, it is a method claim having similar limitations as cited in claim 7. Thus, claim 16 is also rejected under the same rationale as cited in the rejection of claim 7 above.
44. As per claim 25, it is a system claim having similar limitations as cited in claim 7. Thus, claim 25 is also rejected under the same rationale as cited in the rejection of claim 7 above.
45. As per claim 34, it is a media claim having similar limitations as cited in claim 7. Thus, claim 34 is also rejected under the same rationale as cited in the rejection of claim 7 above.
46. Claims 8, 17, 26 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou, Ringseth and Edwards in further view of Cartwright et al. (U.S. Publication 2021/0133761) (Cartwright hereinafter).
47. As per claim 8, Zhou and Ringseth teach the one or more processors of claim 1. Zhou and Ringseth do not explicitly disclose but Edwards discloses comprising a GPU with a plurality of cores [Fig. 37 depicts GPU 3592 with multiple programmable processing units 3720; multiple programming processing units mapped to cores]; wherein: each core of the plurality of cores supports a maximum number of threads [“FIG. 38 illustrates how threads of an exemplary CUDA grid 3820 are mapped to different compute units 3740 of FIG. 37, in accordance with at least one embodiment. In at least one embodiment and for explanatory purposes only, grid 3820 has a GridSize of BX by 1 and a BlockSize of TX by TY by 1. In at least one embodiment, grid 3820 therefore includes, without limitation, (BX * BY) thread blocks 3830 and each thread block 3830 includes, without limitation, (TX * TY) threads 3840.” ¶ 0337].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth and Edwards available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou and Ringseth to include the capability of performing a scan operation as taught by Edwards, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a parallel processing architecture to reduce significant performance bottlenecks [Edwards ¶ 0002].
Zhou, Ringseth and Edwards do not explicitly disclose but Cartwright discloses the one or more software kernels are performed based at least in part on whether a number of threads is greater than the maximum number of threads [“In a circumstance where the executed process thread count for the selected action process instance does not satisfy the maximum executed process thread count for the selected action process instance (for example, by the executed process thread count exceeding or equal to the maximum executed process thread count for the selected action process instance), the scaling service 702 may select another executed action process instance to attempt to execute a new process thread. In a circumstance where each executed action process instance is associated with an executed process thread count that matches each respective maximum executed process thread count, the scaling service 702 may then attempt to initiate and/or otherwise execute a new action process instance, as described above depending on the maximum process instance relationship.” ¶ 0363; action process instance mapped to software algorithm].
It would have been obvious to one of ordinary skill in the art, having the teachings of Zhou, Ringseth, Edwards and Cartwright available before the effective filing date of the claimed invention, to modify the capability of managing kernel selection as disclosed by Zhou, Ringseth and Edwards to include the capability of managing and synchronizing independent computing resources as taught by Cartwright, thereby providing a mechanism to enhance system efficiency by utilizing multiple threads within a parallel processing architecture in a custom manner based on the application to be executed.
48. As per claim 17, it is a method claim having similar limitations as cited in claim 8. Thus, claim 17 is also rejected under the same rationale as cited in the rejection of claim 8 above.
49. As per claim 26, it is a system claim having similar limitations as cited in claim 8. Thus, claim 26 is also rejected under the same rationale as cited in the rejection of claim 8 above.
50. As per claim 35, it is a media claim having similar limitations as cited in claim 8. Thus, claim 35 is also rejected under the same rationale as cited in the rejection of claim 8 above.
Response to Arguments
Claim Rejections - 35 USC § 101
51. Applicant’s arguments, have been fully considered and are persuasive. The rejections have been withdrawn.
Claim Rejections - 35 USC § 102/103
52. Zhao discloses the first amended limitation “select one or more algorithms …” as recited above.
53. Applicant’s remaining arguments with respect to the newly-added limitation “cause performance …” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
54. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C WOOD whose telephone number is (571)272-5285. The examiner can normally be reached Monday - Friday, 8:00 am - 4:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat C Do can be reached at 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM C WOOD/Examiner, Art Unit 2193
/Chat C Do/Supervisory Patent Examiner, Art Unit 2193
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