DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/2/2025 has been entered.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sumino (US 2012/0091423 A1).
Regarding claim 1, Sumino discloses a phase-change memory (PCM) cell (Fig. 2A), comprising:
a phase-change layer (“the information storage layer 60 is formed of a resistance change layer”, ¶ 0051) with a positive Seebeck coefficient, wherein the phase change layer comprises germanium antimony tellurium (“forming the resistance change layer with a chalcogenide material, the chalcogenide material may be a metal such as GeSbTe”, ¶ 0036; although Sumino is silent as to the specific Seebeck coefficient of the material, the phase-change layer of Subino will have a positive Seebeck coefficient as applicant states that GeSbTe has a positive Seebeck coefficient, see MPEP 2112(III));
a thermoelectric semiconductor layer (“first material layer 53”, ¶ 0048, which is a thermoelectric material, ¶ 0023) directly coupled to the phase-change layer, without an intervening layer between the thermoelectric semiconductor layer and the phase-change layer, wherein the thermoelectric semiconductor layer has a negative Seebeck coefficient (although Sumino is silent as to the specific Seebeck coefficient of the material, the phase-change layer of Subino will have a negative Seebeck coefficient as applicant states that bismuth telluride has a negative Seebeck coefficient, see MPEP 2112(III)) and wherein the thermoelectric semiconductor layer is thinner than the phase-change layer (see Fig. 2A), wherein the thermoelectric semiconductor layer comprises bismuth telluride (¶ 0041); and
a first electrode (“first electrode 51”, ¶ 0048) directly coupled to the thermoelectric semiconductor layer (see Fig. 2A), wherein the thermoelectric semiconductor layer facilities thermoelectric heating at an interface with the phase-change layer when a current is applied through the first electrode to change a state of the phase-change layer (¶ 0009).
Regarding claim 2, Sumino further discloses an insulating layer (“upper insulating layer 30” in Fig. 1, ¶ 0095) coupled to the thermoelectric semiconductor layer (See Fig. 1).
Regarding claim 3, Sumino further discloses wherein the first electrode is disposed through the insulating layer (see Fig. 1).
Regarding claim 4, Sumino further discloses wherein the insulating layer at least partially surrounds the thermoelectric semiconductor layer.
Regarding claim 5, Sumino further discloses a second electrode (52) coupled to the phase-change layer opposite the interface, wherein the current flows through the first electrode and the second electrode.
Regarding claim 7, Sumino is silent as to wherein a difference in Seebeck coefficients between the thermoelectric semiconductor layer and the phase-change layer induces thermoelectric heating of the phase-change layer when the current is applied through the first electrode. However, as the materials of the thermoelectric semiconductor layer and the phase-change layer are identical to those claimed (see rejection of claim 1, above), this property will inherently be satisfied (see MPEP 2112(III)).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 14-18 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumino (US 2012/0091423 A1).
Regarding claim 14, Sumino discloses a phase-change memory (PCM) cell (Fig. 2A), comprising:
a phase-change layer (“the information storage layer 60 is formed of a resistance change layer”, ¶ 0051) with a positive Seebeck coefficient, wherein the phase change layer comprises germanium antimony tellurium (“forming the resistance change layer with a chalcogenide material, the chalcogenide material may be a metal such as GeSbTe”, ¶ 0036; although Sumino is silent as to the specific Seebeck coefficient of the material, the phase-change layer of Subino will have a positive Seebeck coefficient as applicant states that GeSbTe has a positive Seebeck coefficient, see MPEP 2112(III));
a thermoelectric semiconductor layer (“first material layer 53”, ¶ 0048, which is a thermoelectric material, ¶ 0023) directly coupled to the phase-change layer, without an intervening layer between the thermoelectric semiconductor layer and the phase-change layer, wherein the thermoelectric semiconductor layer has a negative Seebeck coefficient (although Sumino is silent as to the specific Seebeck coefficient of the material, the phase-change layer of Subino will have a negative Seebeck coefficient as applicant states that bismuth telluride has a negative Seebeck coefficient, see MPEP 2112(III)), wherein the thermoelectric semiconductor layer is thinner than the phase-change layer (see Fig. 2A), and wherein the thermoelectric semiconductor is configured to facilitate thermal heating at an interface with the phase-change layer when a set current is supplied to the PCM cell via a first electrode directly coupled to the thermoelectric semiconductor layer (¶ 0009). wherein the thermoelectric semiconductor layer comprises bismuth telluride (¶ 0041).
Sumino does not explicitly disclose that this PCM cell is one of a plurality of PCM cells in a PCM device.
However, Sumino discloses that it was known in the art to form memory devices comprising a plurality of cells (“a semiconductor device having nonvolatile memory cells”, ¶ 0002). There was a benefit to forming a device comprising a plurality of memory cells in that it allows for larger amounts of data to be stored in a single device. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a device comprising a plurality of PCM cells as disclosed by Sumino for this benefit.
Regarding claim 15, Sumino further discloses a selector device (“selection transistor”, ¶ 0043) coupled to the PCM cell and configured to selectively provide the set current to one of the PCM cells (¶ 0043).
Regarding claim 16, Sumino further discloses wherein the selector device is further configured to selectively provide a reset signal to one of the PCM cells (¶ 0076 and 0100).
Regarding claim 17, Sumino further discloses a common substrate (10 in Fig. 1) on which the PCM cells are disposed.
Regarding claim 18, Sumino further discloses an insulating layer (23 in Fig. 1) disposed between the common semiconductor substrate and the thermoelectric semiconductor layer of each of the plurality of PCM cells.
Regarding claim 23, Sumino does not disclose the thicknesses of the thermoelectric semiconductor layer or the phase-change layer to determine if it falls within the claimed range. However the thickness of the thermoelectric semiconductor layer is a result effective variable as too thick of a layer would result in too large a voltage drop across the cell such that the memory material cannot be reliably switched and too thin a layer would not effectively facilitate heating. Further, the thickness of the phase-change layer is a result effective variable as too thick a layer would result in too large a voltage drop across the cell such that the memory material cannot be reliably switched and too thin a layer would be switched by minor, unintentional currents. As such, both thickness are result effective variables to be optimized and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. (See MPEP § 2144.05 (II) (A) and (B)).
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumino (US 2012/0091423 A1) as applied to claim 1, above.
Regarding claim 21, Sumino does not disclose the thickness of the thermoelectric semiconductor layer to determine if it falls within the claimed range. However the thickness of the thermoelectric semiconductor layer is a result effective variable as too thick of a layer would result in too large a voltage drop across the cell such that the memory material cannot be reliably switched and too thin a layer would not effectively facilitate heating. As such, the thickness is a result effective variable to be optimized and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. (See MPEP § 2144.05 (II) (A) and (B)).
Regarding claim 22, Sumino does not disclose the thickness of the phase-change layer to determine if it falls within the claimed range. However, the thickness of the phase-change layer is a result effective variable as too thick a layer would result in too large a voltage drop across the cell such that the memory material cannot be reliably switched and too thin a layer would be switched by minor, unintentional currents. As such, the thickness is a result effective variable to be optimized and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. (See MPEP § 2144.05 (II) (A) and (B)).
Response to Arguments
Applicant's arguments filed 10/2/2025 have been fully considered but they are not persuasive.
Applicant states that “it is not the information storage layer 60 in general which comprises the GeSbTe but rather the ionic layer 62 of the information storage layer 60”. As the phase change layer 60 comprises layer 62 and layer 62 is GST, phase change layer 60 of Sumino comprises GST. As phase change layer 60 is directly coupled to the thermoelectric semiconductor layer, the claim limitations are satisfied.
Conclusion
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/CHRISTOPHER A CULBERT/Examiner, Art Unit 2815