DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Drawings 3
IV. Claim Rejections - 35 USC § 112 3
A. Claim 21 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 3
V. Claim Rejections - 35 USC § 103 4
A. Claims 4, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0050514 (“Chen”) in view of US 2009/0280649 (“Mayer”). 4
B. Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0022545 (“Lee”) in view of Mayer and US 2019/0051600 (“Oh”). 10
C. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Mayer and Oh, as applied to claim 8 above, and further in view of Chen. 15
VI. Response to Arguments 16
VII. Pertinent Prior Art 16
Conclusion 17
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 04/17/2026 has been entered.
III. Drawings
The drawings were received on 04/17/2026. These drawings are acceptable.
IV. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claim 21 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 21 reads,
21. (New) The semiconductor structure of claim 8, wherein the refractory metal liner coats the metal via.
There is not support for a refractory metal liner coating the metal via 806 protruding from the metal line 802, as shown in Figs. 8 and 23. In fact, the Instant Application teaches away from including any liner or barrier between the metal via 806 and the surrounding low-k dielectric layer 808, as shown in each of Figs. 8 and 23, stating in this regard,
Note there is no barrier or liner between the vias 806 and the dielectric 808.
(¶ 42 of US 2023/0116440, which is the pre-grant publication of the Instant Application; emphasis added)
Additionally, the low-k dielectric 808 advantageously contacts bare sides of the vias 806, without any intervening liner.
(¶ 44 of US 2023/0116440; emphasis added)
V. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 4, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0050514 (“Chen”) in view of US 2009/0280649 (“Mayer”).
Claim 1 reads,
1. (Currently Amended) A semiconductor structure comprising:
[1] a substrate defining a first trench;
[2] a first refractory metal liner coating the first trench;
[3] a heavy metal liner coating the first refractory metal liner;
[4] a copper structure filling the first trench over a bottom portion of the heavy metal liner;
[5a] a generally planar capping dielectric layer on top of the substrate and the copper structure,
[5b] wherein the generally planar capping dielectric layer is in direct physical contact with an uppermost surface of the first refractory metal liner;
[6] a low-k dielectric layer on top of the generally planar capping dielectric layer; and
[7] a titanium nitride (TiN) layer on top of the low-k dielectric layer.
With regard to claim 1, Chen discloses, Figs. 1, 4, and 5,
1. (Currently Amended) A semiconductor structure comprising:
[1] a substrate 114 defining a first trench [in which “conductive feature 112”, e.g. “contacts 66” or “conductive lines 108B” in Fig. 1 is formed (¶¶ 16-17; Figs. 1, 2)];
[2]-[3] … [not taught] …
[4] a … [conductive] … structure 112 [¶ 17] filling the first trench …;
[5a] a generally planar capping dielectric layer 202 [¶ 17] on top of the substrate 114 and the …[conductive]… structure 112;
[5b] wherein the generally planar capping dielectric layer 202 is in direct physical contact with an uppermost surface of the …[the conductive structure 112] …
[6] a low-k dielectric layer 206 [¶ 19] on top of the generally planar capping dielectric layer 202; and
[7] a titanium nitride (TiN) layer 230 on top of the low-k dielectric layer 206 [¶ 23: “The mask layer 230 is formed of a titanium-containing mask material, such as titanium nitride …”].
With regard to features [2]-[4] of claim 1, Chen states,
[0017] FIG. 2 illustrates the formation of an etch stop layer (ESL) 202 and a dielectric layer 206. The ESL 202 and the dielectric layer 206 are formed over a dielectric layer 114 and conductive features 112. The dielectric layer 114 may be the IMD of an underlying interconnect level (e.g., the IMD 110B in FIG. 1) or may be an underlying ILD (e.g., the ILD(s) 64 in FIG. 1). The conductive features 112 may be a conductive line of an underlying interconnect level (e.g., the conductive lines 108B in FIG. 1) or may be an electrically conductive feature in an underlying ILD (e.g., the contacts 66 in FIG. 1).
(Chen: ¶ 17; emphasis added)
Chen does not teach the details of the conductive features 112 and does not therefore teach all of the limitations of features [2]-[4b].
Mayer teaches a process for making copper structures (abstract) for BEOL interconnect (¶ 35) including features [2]-[4]:
[2] a first refractory metal liner 132(317) coating the first trench 110, 112 [¶¶ 138, 170; Figs. 2, 21; “Barrier layer 132 typically comprises a conductive metal or metal nitride, such as tantalum, titanium, or tungsten, and/or nitrides of these metals.” (¶ 138)];
[3] a heavy metal liner 142(318) coating the first refractory metal liner 132 [¶¶ 140, 170; Figs. 3, 21; “metal seed layer 142 comprises non-cuprous metal, such as ruthenium, osmium, rhenium, rhodium, platinum, platinum, nickel, cobalt, nickel alloy and cobalt alloy.” (¶ 140)];
[4] a copper structure 262(316), 264(316) [¶¶ 7, 34, 138, 157, 166, 168, 170; Figs. 6-18, 21] filling the first trench 110, 112 over a bottom portion of the heavy metal liner 142(318);
Mayer further teaches forming a heavy metal capping layer 294(315) of, e.g. cobalt, which may be the same as the seed layer 142, i.e. cobalt (¶¶ 140, 168). The capping layer 294(315) is recessed and substantially coplanar with the top surfaces of the adjacent barrier layer 132(317) and the surface of the dielectric layer 106 (¶ 168) Thus, like the Instant Application, the copper metal structure 316 may be surrounded by a heavy metal liner 315, 318 made of cobalt that is substantially coplanar with each of the first liner layer 317 and the adjacent dielectric. Mayer teaches that the cobalt capping layer improves electromigration resistance and also functions as an additional barrier to copper diffusion, stating “Another useful application for PFSM, as mentioned above, is selective electrolytic plating and initiation of electroless plating by electrolytic plating (e.g., of a barrier and metal capping film, such as cobalt, nickel, CoW, NiW, CoNiW) over the lines of in-laid and exposed damascene copper for the purposes of improving electromigration properties and acting as a diffusion barrier.” (¶ 295: emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the conductive structure 112 in Chen from the material layers taught in Mayer including each of the refractory barrier 317, the heavy metal liner 318 or 318/315, and the copper fill 316 because Chen does not provide the details of the conductive features 112 such that one having ordinary skill in the art would use well known conductive structures for multilevel metallization, such as those taught in Mayer to be suitable for the same purpose. Moreover, Mayer teaches that the capping layer 315 helps prevent electromigration of the copper (¶ 295), which is a known benefit of the heavy metal liner and capping layer. As such, Mayer may be seen as an improvement to Chen in this aspect. (See MPEP 2143.)
Further with regard to features [5a]-[5b] of claim 1, inasmuch as Mayer shows that the top surfaces of each of the heavy metal capping layer 315 the barrier layer 317 and the surrounding dielectric 106 are generally coplanar, the capping dielectric layer 202 of Chen with remain generally planar, as required by feature [5a]. In addition, because the top surface of the barrier layer 317 is exposed, the capping dielectric layer 202 of Chen will directly contact the barrier layer, as required by feature [5b].
This is all of the limitations of claim 1.
With regard to claims 2-4, Chen further discloses,
2. (Original) The semiconductor structure of claim 1, further comprising: an etch stop layer 210 and/or 220 [¶¶ 20-22] between the low-k dielectric layer 206 and the TiN layer 230 [Fig. 4].
3. (Original) The semiconductor structure of claim 1, further comprising:
[1] a hard mask 240 [¶ 24] on the TiN layer 230; and
[2] a photoresist 250 [¶ 25] on the hard mask 240.
4. (Original) The semiconductor structure of claim 3, wherein the photoresist 250 and the hard mask 240 define a trench template 242 [Figs. 4-5].
With regard to the “trench template” the photoresist 250 and the hard mask 240 defining a trench template, Chen states,
[0026] In FIG. 5, the photosensitive mask 250 is used as an etching mask to etch and pattern the mask layers 240, 230, and 220, thus forming masks having openings 242 that will be used in subsequent etching processes to form trenches for conductive lines in the dielectric layer 206. The openings 242 are formed through the mask layers 240, 230, and 220. In some embodiments, the openings 242 extend into (but not through) the mask layers 210. One or more layers of the photosensitive mask 250 may be consumed in the etching process, or may be removed after the etching process. …
(Chen: ¶ 26; emphasis added)
With regard to claim 5, Chen modified according to Mayer to have the conductive features 112 of Chen to have the materials and structure in Mayer, as explained under claim 1, further teaches,
5. (Currently Amended) The semiconductor structure of claim 4, wherein a second trench 204/208 [of Chen] extends through the TiN layer 230 [of Chen], the low-k dielectric layer 206[of Chen], and the generally planar capping dielectric layer 202 [of Chen] to the copper structure 112 [of Chen/Mayer] [Figs. 5-8 of Chen—especially Fig. 8].
With regard to claim 6, Chen further discloses,
6. (Previously Presented) The semiconductor structure of claim 5, further comprising: alternative metal 290(104N-1/108N-1) filling the second trench 204/208 [¶ 38; Figs. 9 and 10].
Bearing in mind the rejection under 35 USC 112(a), above, consistent with the Instant Application, in Chen there is also no hard mask 240 or photoresist 250 present once the alternative metal 290 is deposited into and overflowing the trench 204/208 (Chen: Fig. 9) until a CMP is performed (Chen: Fig. 10). (Compare to Figs. 13-14 of the Instant Application.)
Claim 7 reads,
7. (Original) The semiconductor structure of claim 6, further comprising:
[1] a hard mask located atop the alternative metal; and
[2] photoresist located atop the hard mask.
After the CMP shown in Fig. 10, Chen states,
[0040] Additional interconnect levels may be formed after the process described for FIGS. 2-10. FIG. 11 illustrates an interconnect level 100N which is formed on the intermediate interconnect level 100N-1. The interconnect level 100N comprises a conductive via 104N and a conductive line 108N in an IMD 110N. The IMD 110N is formed from, e.g., a dielectric layer 306. The interconnect level 100N may be formed of similar materials and by similar methods as described above for the interconnect level 100N-1 (see above, FIGS. 2-10).
(Chen: ¶ 40)
Fig. 11 shows additional hard mask layers 302 over the alternative metal fill 104N/108N, which is patterned using photoresist consistent with Figs. 2-10; therefore, all of the features of claim 7 are taught, as follows:
7. (Original) The semiconductor structure of claim 6, further comprising:
[1] a hard mask 302 located atop the alternative metal 290(104N-1/108N-1); and
[2] photoresist [not shown in Fig. 11] located atop the hard mask 302 [as shown in Figs. 2-10 as needed to pattern the opening in 302 as explained in ¶ 40 of Chen, supra].
This is all of the limitations of claim 7.
B. Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0022545 (“Lee”) in view of Mayer and US 2019/0051600 (“Oh”).
Claim 8 reads,
8. (Currently Amended) A semiconductor structure comprising:
[1] a substrate defining a first trench;
[2] a first refractory metal liner coating the first trench;
[3] a heavy metal liner coating the first refractory metal liner;
[4] a copper structure filling the first trench over a bottom portion of the heavy metal liner,
[5a] a generally planar capping dielectric layer on top of the substrate and the copper structure,
[5b] wherein the generally planar capping dielectric layer is in direct physical contact with an uppermost surface of the first refractory metal liner;
[6] a first low-k dielectric layer on top of the generally planar capping dielectric layer, wherein the first low-k dielectric layer defines a second trench;
[7] a second refractory metal liner coating the second trench;
[8] a metal line filling the second refractory metal liner; and
[9a] a metal via protruding from the metal line,
[9b] the metal via having sides directly contacting a second low-k dielectric layer.
With regard to claim 8, Lee discloses, generally in Figs. 1-4 and 10,
8. (Currently Amended) A semiconductor structure comprising:
[1] a substrate 100/FL/ML/ILD1 [¶¶ 22-26] defining a first trench [where interconnection lines ML_IL are formed (Fig. 1; ¶ 26)];
[2] a first refractory metal liner [i.e. “barrier layer” e.g. TaN, TiN of ML_IL (¶ 51); BM of M1_IL in Figs. 14A-14B or BM of M1_PIL1 in Figs. 14C-14D (¶ 148)] coating the first trench [¶ 51];
[3] … [not taught] …
[4] a copper structure [of M1_IL] filling the first trench … [¶ 51: “Each of the M1 interconnection lines M1_IL may be formed of or include at least one of copper (Cu) …”],
[5a] a … capping dielectric layer ESL on top of the substrate 100/FL/ML/ILD1 and the copper structure [of M1_IL],
[5b] wherein … capping dielectric layer ESL is in direct physical contact with an uppermost surface of the first refractory metal liner [i.e. “barrier layer” e.g. TaN, TiN of ML_IL (¶ 51); BM of M1_IL in Figs. 14A-14B or BM of M1_PIL1 in Figs. 14C-14D (¶ 148)];
[6] a first low-k dielectric layer ILD_L [¶ 34: SiOCH] on top of the … capping dielectric layer ESL, wherein the first low-k dielectric layer defines ILD_L a second trench [in which MTL is formed (Figs. 2-4)];
[7] a second refractory metal liner BAP [¶ 94] coating the second trench [Fig. 10];
[8] a metal line [IL_L/IL in Figs. 3 and 10] filling the second refractory metal liner BAP [Fig. 10]; and
[9a] a metal via UVI protruding from the metal line IL_L/IL [¶¶ 42-43; Fig. 4],
[9b] the metal via UVI having sides directly contacting a second low-k dielectric layer ILD_U [as shown in Figs. 6 and 7A; ¶¶ 45-46, 71].
With regard to features [2] and [5a] of claim 8, Figs. 1-4 and 10 of Lee do not show the barrier layer made of, e.g. TiN or TaN (¶ 51), coating the trench where interconnection lines ML_IL are formed. However, as noted above each of Figs. 14A-14D show the barrier layer BM of, e.g. TiN or TaN (¶ 148), lining the trench in which the M1_IL is formed.
It would have been at least obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to line/coat the trench in ILD1 with the TiN or TaN barrier layer in Figs. 1-4 and 10 of Lee before forming the copper fill, (1) in order to prevent copper diffusion into ILD1, as is exceedingly well known in the art, and (2) because Lee shows that the barrier layer BM should line the trench.
So modified, the “capping dielectric layer ESL is in direct physical contact with an uppermost surface of the first refractory metal liner BM”, as shown in each of Figs. 14A-14D of Lee and as required by feature [5b] of claim 8.
With regard to features [3] and [4] of claim 8,
[3] a heavy metal liner coating the first refractory metal liner;
[4] a copper structure filling the first trench over a bottom portion of the heavy metal liner,
Lee does not teach the heavy metal liner on the barrier liner and does not therefore teach all of the limitations of features [3] and [4].
As explained above, Mayer teaches a process for making copper structures (abstract) for BEOL interconnect (¶ 35) including features [2]-[4] of claim 8:
[2] a first refractory metal liner 132(317) coating the first trench 110, 112 [¶¶ 138, 170; Figs. 2, 21; “Barrier layer 132 typically comprises a conductive metal or metal nitride, such as tantalum, titanium, or tungsten, and/or nitrides of these metals.” (¶ 138)];
[3] a heavy metal liner 142(318) coating the first refractory metal liner 132 [¶¶ 140, 170; Figs. 3, 21; “metal seed layer 142 comprises non-cuprous metal, such as ruthenium, osmium, rhenium, rhodium, platinum, platinum, nickel, cobalt, nickel alloy and cobalt alloy.” (¶ 140)];
[4] a copper structure 262(316), 264(316) [¶¶ 7, 34, 138, 157, 166, 168, 170; Figs. 6-18, 21] filling the first trench 110, 112 over a bottom portion of the heavy metal liner 142(318);
Mayer further teaches forming a heavy metal capping layer 294(315) of, e.g. cobalt, which may be the same as the seed layer 142, i.e. cobalt (¶¶ 140, 168). The capping layer 294(315) is recessed and substantially coplanar with the top surfaces of the adjacent barrier layer 132(317) and the surface of the dielectric layer 106 (¶ 168) Thus, like the Instant Application, the copper metal structure 316 may be surrounded by a heavy metal liner 315, 318 made of cobalt that is substantially coplanar with each of the first liner layer 317 and the adjacent dielectric. Mayer teaches that the cobalt capping layer improves electromigration resistance and also functions as an additional barrier to copper diffusion, stating “Another useful application for PFSM, as mentioned above, is selective electrolytic plating and initiation of electroless plating by electrolytic plating (e.g., of a barrier and metal capping film, such as cobalt, nickel, CoW, NiW, CoNiW) over the lines of in-laid and exposed damascene copper for the purposes of improving electromigration properties and acting as a diffusion barrier.” (¶ 295: emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a heavy metal liner 318 or 318/315 of, e.g. Co, and associated capping layer, e.g. Co, surrounding the copper fill of M1-IL of Lee, in order to improve the electromigration resistance of the copper fill and to prevent diffusion of the copper fill, as taught in Mayer (¶ 295, supra). As such, Mayer may be seen as an improvement to Lee in this aspect. (See MPEP 2143.)
With regard to feature [5a] and [6] of claim 8, Lee does not teach that the dielectric capping layer ESL is substantially planar.
Oh, like Lee, is drawn to making a multilevel metallization. Also like Lee, Oh teaches a three-layered etch stop layer (ESL), i.e. the claimed “capping dielectric layer”. However, Oh teaches that the ESL 55 is made planar by proper selection of the thickness of the middle layer of the three layered structure 55(=51/52/53) (Oh: Fig. 16).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the ESL of Lee because Oh teaches that planarity of the upper surface of the ESL 55 is a suitable configuration for a three-layered ESL used in making a multi-level metallization. Moreover, one having ordinary skill in the art would recognize the benefit of the planar upper surface of the dielectric capping layer in preventing concatenation of the non-planarity in subsequently deposited layers, thereby improving photolithographic patterning accuracy in multilayer metallization. As such, Oh may be seen as an improvement to Lee in this aspect. (See MPEP 2143.)
With regard to features [6] and [9b] of claim 8, first, Lee states that each of the lower ILD_L and upper ILD_U interlayer dielectric layers can be made from the same material (Lee: ¶ 71: “The lower and upper interlayer insulating layers ILD_L and ILD_U may be formed of or include the same insulating material …”).
Lee does not state that ILD_L is “low-k”. Lee does however state,
For example, the lower interlayer insulating layer ILD_L may include a silicon oxide layer containing silicon (Si) and oxygen (O). The lower interlayer insulating layer ILD_L may further contain carbon (C) and hydrogen (H).
(Lee: ¶ 34)
An ILD containing SiOC or SiOCH are inherently low-k. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Nonetheless, Oh teaches that all of the interlayer insulating layers 33, 43, 57, can be made from silicon oxide—like Lee—or low-k dielectric materials (Oh: ¶¶ 56, 57, 62).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make both of ILD_L and ILD_U of Lee from low-k dielectrics, in order to reduce RC delay as is exceedingly well known in the art and because Lee and Oh teach overlapping materials for the ILDs, i.e. silicon oxide, thereby making is obvious material choice (See MPEP 2144.07).
Finally, it is noted that feature [9b] of claim 8 has been treated consistent with the limitations shown in Fig. 23 of the Instant Application, which is not currently claimed, as explained above in the rejection of claim 8 under 35 USC 112(a) for lack of written descriptive support.
This is all of the features of claim 8.
With regard to claim 9, Lee further discloses,
9. (Original) The semiconductor structure of claim 8, further comprising: a hard mask VMP [¶ 42; Fig. 4] atop the metal via.
Note that the term “hard” is a relative term of degree; therefore, the mask VMP which is the result of the second etching of the mask material used to make the mask LMP shown in Fig. 3 (Lee: ¶¶ 42-43) is taken to be “hard” within the meaning of the Instant Application.
C. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Mayer and Oh, as applied to claim 8 above, and further in view of Chen.
Claim 10 reads,
10. (Original) The semiconductor structure of claim 8, further comprising: an etch stop layer atop the low-k dielectric layer.
The prior art of Lee in view of Mayer and Oh, as explained above, teaches each of the features of claim 8.
As explained above, Chen teaches an ESL 202, 302 between each of the ILD layers 114, 206, 306 of the multi-level metallization structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an ESL on the low-k dielectric layer ILD_L of Lee in order to prevent etching of the low-k dielectric layer ILD_L during two patterning steps of the metal layer MTL (Lee: Fig. 2) first into metal lines IL (Lee: Fig. 3) and then into the vias UVI on metal lines IL (Lee: Fig. 4). As such, Chen may be seen as an improvement to Lee in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 10.
VI. Response to Arguments
Applicant’s arguments filed 04/17/2026 have been fully considered but are moot because the new grounds of rejection do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
VII. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 2023/0369041 (“Ni”) is cited for teaching a copper interconnect 15 including a refractory metal liner 13 of, e.g., Ti, TiN, Ta, and TaN, and a heavy metal liner 14 of, e.g., Ru or Co, and a heavy metal capping layer 12 of, e.g., Ru or Co (Ni: ¶¶ 36, 37, 58, 59—especially TABLE 3).
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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