DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the RCE filed 2/2/2026 in which claims 1 and 22 were amended and claims 14, 25, and 26 were cancelled.
Claims 1, 4-10, 12, 13, 15-20, and 22 remain pending and are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 7, 16, 17, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishiguchi (US 2018/0308943 and Nishiguchi hereinafter).
As to claims 1, 6, and 7: Nishiguchi discloses [claim 1] a transistor device (Figs 1, 2, and 7A; [0099]), comprising: a plurality of trenches (Figs. 1 and 7A; T; [0073]) in a semiconductor layer (Fig. 2; 22; [0032]) over a semiconductor substrate (21; [0032]), the plurality of trenches (T) including a first trench (Fig. 1; middle T in which middle 50 is formed; [0027]) and a second trench (rightmost T in which rightmost 50 is formed; [0027]); a gate dielectric layer (Fig. 2; comprising 41 and 42; [0035] and [0037]) on first (left sidewall of T) and second sidewalls (right sidewall of T) of the first trench (middle T), and a gate electrode (30; [0035]) between the first (left sidewall of T) and second (right sidewall of T) sidewalls; a dielectric liner (Fig. 2; comprising 43a, 43b, and 43c; [0042]) on the first (left sidewall of T) and second (right sidewall of T) sidewalls of the first trench (middle T), the dielectric liner (comprising 43a, 43b, and 43c) having a first portion (43b) at a bottom of the first trench (middle T) with a first thickness (Tb; [0043]), a second portion (43c) between the first portion (43b) and the gate dielectric layer (comprising 41 and 42) with a second thickness (Tc) less than the first thickness ([0043]), and a third portion (43a) between the second portion (43c) and the gate dielectric layer (comprising 41 and 42) with a third thickness (Ta) less than the second thickness ([0043]); and a conductive field plate (Fig. 2; 50; [0027]) in the first trench (middle T), the conductive field plate (50) having a bottom portion (50b; [0039]) with a first width and a first height (as shown in the Figure; [0041]), a middle portion (50c; [0039]) between the bottom portion (50b) and the gate electrode (30) with a second width greater than the first width (as shown in the Figure; [0041]) and a second height smaller than the first height (the height of 50c measured between the top of 50b and the bottom of 50a is relatively smaller than the height of 50b, measured between the top of 50b to the bottom of 50b, in the Figure), and a top portion (50a; [0039]) between the middle portion (50c) and the gate electrode (30) with a third width greater than the second width (as shown in the Figure; [0041]) and a third height smaller than the second height (the height of 50a measured between the top of 50a and the bottom of 50a is relatively smaller than the height of 50c in the Figure), wherein the top portion (50a) has a uniform width (as shown in the Figure), the top portion (50a) and the middle portion (50c) are in direct contact (as shown in the Figure), and the top portion (50a) and the gate dielectric layer (comprising 41 and 42) are in direct contact (as shown in the Figure); [claim 6] wherein the semiconductor substrate (21) is n-type doped (n+ doped; [0032]); [claim 7] further comprising a body region (Fig. 2; 23; [0030]) between the first (Fig. 1; middle T in which middle 50 is formed) and second (rightmost T in which rightmost 50 is formed) trenches and a first doped region (Fig. 2; 24; [0030]) within the body region (23), the first doped region (24) providing a source ([0030]) of a trench gate MOSFET ([0099]) and the semiconductor substrate (21) providing a drain ([0032]) of the trench gate MOSFET.
As to claims 22, 16, and 17: Nishiguchi discloses [claim 22] a trench gate metal oxide semiconductor field effect transistor (MOSFET) device (Figs. 1, 2, and 7A; [0099]), comprising: a substrate (Fig. 2; 21; [0032]) having a semiconductor surface layer (22; [0032]) doped with a first conductivity type (n-type; [0032]); and at least one trench gate MOSFET (Fig. 2; [0073] and [0099]) in the semiconductor surface layer (22), including: a body region (Fig. 2; 23; [0032]) in the semiconductor surface layer (22) doped with a second conductivity type (p-type; [0032]); a source region (Fig. 2; 24; 0032]) on top of the body region (23) doped with the first conductivity type (n-type; [0032]); a trench (Figs. 2 and 7A; T; [0073]) extending down from a top side (top surface) of the semiconductor surface layer (22), the trench (T) abutting the body region (23) and being lined with a dielectric material (comprising 43a, 43b, and 43c; [0042]); a field plate (Fig. 2; 50; [0037]) comprising polysilicon (polycrystalline silicon; [0085]) in the trench (T); a gate electrode (30; [0027]) over the field plate (50); and a gate dielectric layer (Fig. 2; comprising 41 and 42; [0027] and [0037]) between the gate electrode (30) and the field plate (50), wherein the field plate (50) has a bottom portion (50b; [0039]) with a first width and a first height (as shown in the Figure; [0041]), a middle portion (50c; [0039]) with a second width (as shown in the Figure; [0041]) and a second height (measured between the top of 50c and the bottom of 50c) between the bottom portion (50b) and the gate electrode (30), and a top portion (50a; [0039]) with a third width (as shown in the Figure; [0041]) and a third height (measured between the top of 50a and the bottom of 50a) between the middle portion (50c) and the gate electrode (30), the second width greater than the first width (as shown in the Figure; [0041]), the third width greater than the second width (as shown in the Figure; [0041]), the third height smaller than the second height (the height of 50a is relatively smaller than the height of 50c in the Figure), and the second height smaller than the first height (the height of 50c is relatively smaller than the height of 50b in the Figure), and wherein the top portion (50a) has a uniform width (as shown in the Figure), the top portion (50a) and the middle portion (50c) are in direct contact (as shown in the Figure), and the top portion (50a) and the gate dielectric layer (comprising 41 and 42) are in direct contact (as shown in the Figure); [claim 16] wherein the first conductivity type is n-type (n-type; [0032]); [claim 17] wherein the at least one trench gate MOSFET (Fig. 1; [0099]) is one of a plurality of trench gate MOSFETs (as shown in the Figure) and the gate electrode (30) is one of a corresponding plurality of gate electrodes (as shown in the Figure), and the source region (24) is one of a corresponding plurality of source regions (as shown in the Figure) each located between an adjacent pair of gate electrodes (30), the plurality of source regions (24) providing a combined source region (through 12 in Fig. 2; [0036]) for the plurality of trench gate MOSFETs (as shown in the Figure) and the substrate (21) providing a drain ([0032]) for the plurality of trench gate MOSFETs (as shown in the Figure).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi in view of Kobayashi et al (US 2016/0093719 and Kobayashi hereinafter).
Although the structure disclosed by Nishiguchi shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
wherein the gate dielectric layer has a thickness in a range from 100 Å to 10,000 Å.
Kobayashi discloses wherein the gate dielectric layer (Fig. 1A; 52; [0024]) has a thickness in a range from 100 Å to 10,000 Å (52 can be 45 nm to 55 nm, which is 450 Å to 550 Å).
Kobayashi discloses a range of gate dielectric layer thickness that overlaps the claimed range and it was well-known in the art before the effective filing date of the claimed invention that the gate dielectric layer thickness is a result effective variable as it affects the isolation between the gate electrode and the channel region and the voltage requirement to operate the transistor.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose a gate dielectric thickness within the claimed range, such as a value disclosed by Kobayashi, as the thickness would affect the operating voltage of the device. See MPEP 2144.05(I).
Claims 5, 8, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi in view of Hsieh (US 2021/0126124 and Hsieh hereinafter).
As to claims 5 and 15: Although the structure disclosed by Nishiguchi shows substantial features of the claimed invention (discussed in paragraphs 7 and 8 above), it fails to expressly disclose:
[claims 5 and 15] wherein the gate electrode includes a recess.
Hsieh discloses [claims 5 and 15] wherein the gate electrode (Fig. 8; 806’; [0029]) includes a recess (recess in 806’ is filled with 816; [0029]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to form a recess in the gate electrode and fill with a contact material in order to provide a means to control the gate electrode.
As to claim 8: Nishiguchi discloses further comprising a pre-metal dielectric (PMD) layer (Fig. 2; 45; [0035]) over the first and second trenches (Figs. 1 and 7A; middle and right T; [0019]) and contact (Fig. 2; 12; [0028]) through the PMD layer (45), including a first contact (12) to the body region (23).
Nishiguchi fails to expressly disclose that there are multiple contacts through the PMD and the contacts include a second contact to the gate electrode.
Hsieh discloses that there are multiple contacts (Fig. 8; left and right 816; [0029]) through the PMD (814; [0029]) and the contacts include a second contact (right 816) to the gate electrode (806’; [0029]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within his or her ordinary capabilities to form a contact to the gate electrode as well as one to the body in order to provide a means to control the gate electrode.
As to claim 18: Nishiguchi discloses further comprising a pre-metal dielectric (PMD) layer (Fig. 2; 45; [0035]) over the plurality of trench gate MOSFETs (Figs. 1 and 7A; middle and right T; [0019] and [0099]) and contacts (Fig. 2; 12; [0028]) through the PMD layer (45), a first subset of contacts (12) reaching a plurality of body regions (23; [0030]) under the combined source region (12), wherein each of the first subset of the contacts electrically connects to a corresponding one of the plurality of source regions (24) and a corresponding one of the plurality of body regions (23).
Nishiguchi fails to expressly disclose a second subset of the contacts reaching the plurality of gate electrodes.
Hsieh discloses a second subset of the contacts (Fig. 8; left and right 816; [0029]) through the PMD (814; [0029]) reaching the plurality of gate electrodes (806’; [0029]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within his or her ordinary capabilities to form a contact to the gate electrode as well as one to the body in order to provide a means to control the gate electrode.
Claims 9, 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi in view of Kim et al (US 2020/0212219 and Kim hereinafter).
As to claims 9 and 12: Although the structure disclosed by Nishiguchi shows substantial features of the claimed invention (discussed in paragraphs 7 and 8 above), it fails to expressly disclose:
[claim 9] wherein the plurality of trenches are features of a discrete MOSFET device; [claim 12] wherein the trench gate MOSFET device is a discrete device.
Kim discloses wherein the plurality of trenches are features of a discrete MOSFET device (Abstract; MOSFET cell); [claim 12] wherein the trench gate MOSFET device is a discrete device (Abstract; MOSFET cell).
The claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention as one of ordinary skill could have combined the claimed elements, namely individual MOSFET cells combined into an integrated circuit, to provide a chip with multiple functions that comprises MOSFET cells that have a low on-state resistance and high withstand voltage ([0019] of Nishiguchi).
As to claims 10 and 13: Although the structure disclosed by Nishiguchi shows substantial features of the claimed invention (discussed in paragraphs 7 and 8 above), it fails to expressly disclose:
[claim 10] wherein the plurality of trenches are features of a MOSFET device in an integrated circuit; [claim 13] wherein the trench gate MOSFET device is connected within an integrated circuit.
Kim discloses wherein the plurality of trenches are features of a MOSFET device in an integrated circuit (Abstract; integrated circuit); [claim 13] wherein the trench gate MOSFET device is connected within an integrated circuit (Abstract; integrated circuit).
The claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention as one of ordinary skill could have combined the claimed elements, namely individual MOSFET cells combined into an integrated circuit, to provide a chip with multiple functions that comprises MOSFET cells that have a low on-state resistance and high withstand voltage ([0019] of Nishiguchi).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi in view of Shibib et al (US 2020/0243656 and Shibib hereinafter).
As to claims 19 and 20: Although the structure disclosed by Nishiguchi shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
[claim 19] wherein the field plate comprises doped polysilicon; [claim 20] wherein the field plate comprises undoped polysilicon.
Shibib discloses in [0073] that the material for the field plate can be doped or undoped polysilicon.
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within his or her ordinary capabilities to form the polysilicon field plate of Nishiguchi of doped or undoped polysilicon in order to provide a field plate with a desired level of conductivity.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-10, 12, 13, 15-20, and 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
2/21/2026