DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
In regard to 35 USC 103 rejection, applicant’s arguments with respect to claims 1-30 have been considered. However, Shen has been remapped in combination with references Bleiweiss and Xu to teach the amended features. Examiner respectfully directs Applicant to the detailed rejection for an explanation of how the references disclose the argued limitations. Shen explains input shapes and their dimensions. Then describes a typing constraint being used while representing them in code.
Specifically:
apply one or more constraints represented in code for one or more neural networks as one or more symbolic expressions at runtime to determine tensor shape information for one or more dynamically configurable dimensions of one or more sets of data; and (Shen, pg. 4, Col. 2, paragraph 1, “First, operators with dynamic output shapes depending on the input data, such as arange2 and unique3, will use Any to describe those shapes. Second, when input shapes contain Any dimension, the type relation needs to propagate [tensor shape information] Any correctly to the output types and relax typing constraints that hold in the static cases when necessary [apply one or more constraints represented in code]. For example, the rules for broadcast4 type relation between two dimensions with Any are defined as follows:
broadcast rel(Any; 1) ! Any
broadcast rel(Any; d) ! d (d > 1)
broadcast rel(Any; Any) ! Any
Note that due to the presence of dynamic shapes, these type relation rules can no longer rule out all type errors at compile-time. For example, for the second rule shown above, when Any is neither 1 nor d at runtime [one or more symbolic expressions at runtime], it then violates the broadcast type constraints.”)
In regard to 35 USC 101 rejection, applicant’s arguments, see pg. 9, filed 11/12/2025, with respect to Claims 1-30 have been fully considered and are persuasive. The 101 rejection of 08/12/2025 has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-6, 9-10, 12-13, 15-16, 19-22, 25-28, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (NIMBLE: EFFICIENTLY COMPILING DYNAMIC NEURAL NETWORKS FOR MODEL INFERENCE, "Shen") [Mar. 12, 2021] and in view of Bleiweiss et al (US Published Patent Application No. 20190205736, "Blieweiss") [July, 4th 2019] .
In regard to claim 1 and analogous claims 19 and 25, Shen teaches apply one or more constraints represented in code for one or more neural networks as one or more symbolic expressions at runtime to determine tensor shape information for one or more dynamically configurable dimensions of one or more sets of data; and (Shen, pg. 4, Col. 2, paragraph 1, “First, operators with dynamic output shapes depending on the input data, such as arange2 and unique3, will use Any to describe those shapes. Second, when input shapes contain Any dimension, the type relation needs to propagate [tensor shape information] Any correctly to the output types and relax typing constraints that hold in the static cases when necessary [apply one or more constraints represented in code]. For example, the rules for broadcast4 type relation between two dimensions with Any are defined as follows:
broadcast rel(Any; 1) ! Any
broadcast rel(Any; d) ! d (d > 1)
broadcast rel(Any; Any) ! Any
Note that due to the presence of dynamic shapes, these type relation rules can no longer rule out all type errors at compile-time. For example, for the second rule shown above, when Any is neither 1 nor d at runtime [one or more symbolic expressions at runtime], it then violates the broadcast type constraints.”)
infer information from one or more sets of data based, at least in part, on one or more dynamically configurable dimensions of the one or more sets of data according to the determined tensor shape information. (Shen, pg. 3, Col. 2, paragraph 2, “Second, shape functions are attached to operators to compute the output shapes dynamically and perform type checking at runtime [dynamically configurable dimensions] (Section 3.2). Third, a memory planning optimization is employed to reduce the amount of memory consumed (Section 3.3).” and pg. 4, Col. 1, 3.1 Typing, paragraph 1, “Deep learning compilers use type systems to represent, check and infer the data types and shapes of tensors [information]. In some frameworks and compilers this is separated into two steps, shape inference and data type inference.”, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”))).
Shen teaches shape inference for input tensors during compilation using inference algorithms but does not expressly disclose using one or more circuits to use one or more neural networks to for this task. However, Blieweiss , paragraph 0017, “FIG. llB illustrates a cross-section side view of an integrated circuit package assembly according to some embodiments [one or more circuits].” and paragraph 0164, “A machine learning application 1502 can be configured to train a neural network using a training dataset [use one or more neural networks to infer information] or to use a trained deep neural network to implement machine intelligence. The machine learning application 1502 can include training and inference functionality for a neural network and/or specialized software that can be used to train a neural network before deployment. The machine learning application 1502 can implement any type of machine intelligence including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation [from one or more sets of data based, at least in part…of the one or more sets of data.].”).
Shen and Blieweiss are related to the same field of endeavor (i.e. optimizing machine learning). In view of the teachings of Shen, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Blieweiss to Shen before the effective filing date of the claimed invention in order to use neural networks to infer certain information/instructions such as shape inference. (Blieweiss, paragraph 0159, “In one embodiment the inferencing configuration of the GPGPU 1430 can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks”)
In regard to claim 2 and analogous claims 20 and 26, Shen and Blieweiss teaches the processor of claim 1.
Shen teaches wherein the information includes one or more constraints of the one or more dynamically configurable dimensions of the one or more sets of data (Shen, pg. 4, Col. 1 (“In order to support dynamic data shapes, Nimble introduces a special dimension called Any to represent statically unknown dimensions. For example, we can represent a tensor type as Tensor[(1, 10, Any), float32],where the size of the third dimension in this tensor is unknown while the other two dimensions have concrete values.”)).
In regard to claim 3 and analogous claims 21 and 28, Shen and Blieweiss teach the processor of claim 1.
Shen further teaches generate a kernel that takes one or more input values corresponding to the one or more dynamically configurable dimensions of the one or more sets of data (Shen, pg. 3, Col. 2, paragraph 2, “Second, shape functions are attached to operators to compute the output shapes dynamically and perform type checking at runtime [dynamically configurable dimensions] (Section 3.2). Third, a memory planning optimization is employed to reduce the amount of memory consumed (Section 3.3).” pg. 4, Col. 1, 3.1 Typing, paragraph 1, “Deep learning compilers use type systems to represent, check and infer the data types and shapes of tensors. In some frameworks and compilers this is separated into two steps, shape inference and data type inference,” and pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)).
Blieweiss teaches wherein the one or more circuits are. (Blieweiss, paragraph 0139, “When the OpenGL API is in use, shader instructions 1012 in the GLSL high-level language are passed to a user mode graphics driver 1026 for compilation. In some embodiments, user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029. In some embodiments, kernel mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions. “)
Blieweiss and Shen are combinable for the same rationale as set forth above with respect to
claim 1.
In regard to claim 5, Shen and Blieweiss teaches the processor of claim 1.
Blieweiss further teaches wherein the one or more circuits are to generate a set of instructions that implement the one or more neural networks (Blieweiss, paragraph 0049, “In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a specific instruction set 109.”)
Shen further teaches and symbolically represent the one or more dynamically configurable dimensions of the one or more sets of data (Shen, pg. 4, Col. 1 (“In order to support dynamic data shapes, Nimble introduces a special dimension called Any to represent statically unknown dimensions. For example, we can represent a tensor type as Tensor[(1, 10, Any), float32],where the size of the third dimension in this tensor is unknown while the other two dimensions have concrete values.”)).
In regard to claim 6 and analogous claim 27, Shen and Blieweiss teaches the processor of claim 1.
Shen further teaches and the one or more circuits are to generate a set of instructions that takes one or more input values corresponding to the one or more dynamically configurable dimensions, (Shen, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)). Shen further teaches wherein the information includes one or more constraints of the one or more dynamically configurable dimensions, wherein the input values are to be generated based, at least in part, on the one or more constraints (Shen, pg. 4, Col. 1 (“In order to support dynamic data shapes, Nimble introduces a special dimension called Any to represent statically unknown dimensions. For example, we can represent a tensor type as Tensor[(1, 10, Any), float32],where the size of the third dimension in this tensor is unknown while the other two dimensions have concrete values.”)).
In regard to claim 9, Shen and Blieweiss teaches the processor of claim 1.
Blieweiss further teaches, wherein the one or more neural networks are to perform a task in an autonomous vehicle. (Blieweiss, paragraph 0194, “Parallel processor accelerated machine learning has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control.”)
Blieweiss and Shen are combinable for the same rationale as set forth above with respect to
claim 1.
In regard to claim 10, Shen and Blieweiss teaches the processor of claim 1.
Shen further teaches wherein the one or more circuits are further to perform one or more compilers, wherein the one or more compilers are to use one or more static constraints of one or more dimensions of the one or more sets of data to enable the one or more dimensions of the one or more sets of data to be dynamically configured for inferencing using a neural network of the one or more neural networks. (Shen, pg. 4, Col. 2, paragraph 2, “Note that due to the presence of dynamic shapes, these type relation rules can no longer rule out all type errors at compile-time. For example, for the second rule shown above, when Any is neither 1 nor d at runtime, it then violates the broadcast type constraints.”)
In regard to claim 12, Shen and Blieweiss teaches the processor of claim 10.
Blieweiss further teaches wherein the one or more compilers are to generate a kernel that takes one or more input values corresponding to the one or more dimensions. (Shen, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)).
In regard to claim 13, Shen and Blieweiss teaches the processor of claim 1.
Shen further teaches wherein the input values are to be generated based, at least in part, on the one or more static constraints and one or more sets of data. (Shen, pg. 4, Col. 1 (“In order to support dynamic data shapes, Nimble introduces a special dimension called Any to represent statically unknown dimensions. For example, we can represent a tensor type as Tensor[(1, 10, Any), float32],where the size of the third dimension in this tensor is unknown while the other two dimensions have concrete values.”)).
wherein the one or more compilers are to generate a set of instructions that takes one or more input values corresponding to the one or more dimensions, (Shen, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)).
In regard to claim 15, Shen and Blieweiss teaches the processor of claim 10.
Shen further teaches wherein the one or more compilers are to generate a kernel to be performed on a parallel processing unit that takes one or more input values corresponding to the one or more dimensions. (Shen, pg. 8, Col. 2 (“We observe that latency on Nvidia GPU is higher than Intel CPU with Nimble. This is because the size of LSTM model is relative small so that it cannot fully utilize the massive parallelism in the GPU. The significant performance improvement of Nimble comes from two aspects: (a) utilizing the deep learning compiler for better kernel fusion and implementation, (b) encoding the control flow into platform-independent instructions with minimal overhead.”)).
In regard to claim 16, Shen and Blieweiss teaches the processor of claim 10.
Shen further teaches wherein the one or more compilers are to generate a kernel that takes one or more input values corresponding to the one or more dimensions, and are to store the kernel, to be launched based, at least in part, on input values to be generated based, at least in part, on the one or more static constraints (Shen, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)).
In regard to claim 22, Shen and Blieweiss teaches the system of claim 19.
However, Shen and Blieweiss do not explicitly teach wherein the one or more processors are to generate code based, at least in part, on the one or more neural networks, and are to calculate input parameter values for the code based, at least in part, on the information (Shen, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)).
In regard to claim 30, Shen and Blieweiss teach the method of claim 25.
Shen further teaches generating a kernel that takes one or more input values corresponding to the one or more dynamically configurable dimensions, (Shen, pg. 4, Col. 1 (“A Tensor Type is designated by an n-dimensional shape (defined as a tuple of integers describing the tensor’s dimensions) and a data type (e.g. float32 or int64).”), pg. 8, Col. 2 (“We observe that latency on Nvidia GPU is higher than Intel CPU with Nimble. This is because the size of LSTM model is relative small so that it cannot fully utilize the massive parallelism in the GPU. The significant performance improvement of Nimble comes from two aspects: (a) utilizing the deep learning compiler for better kernel fusion and implementation, (b) encoding the control flow into platform-independent instructions with minimal overhead.”))
wherein the one or more input values are to be generated based, at least in part, on the information and one or more sets of input data at a launch of the kernel (Shen, pg. 2, Col. 1 (“Specifically, in order to compile and execute the dynamic models, a system requires an intermediate representation (IR) which can statically represent dynamic constructs, a code generator which can generate kernels for dynamically varying data shapes, and a runtime to handle the dynamic execution and kernel dispatch accordingly.”)).
Claims 4, 7-8, 11, 14, 17-18, 23-24 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (NIMBLE: EFFICIENTLY COMPILING DYNAMIC NEURAL NETWORKS FOR MODEL INFERENCE, "Shen") [Mar. 12, 2021] in view of, Bleiweiss et al (US Published Patent Application No. 20190205736, "Blieweiss") [July, 4th 2019], and in further view of Xu et al (GSPMD: General and Scalable Parallelization for ML Computation Graphs, "Xu") [May, 10, 2021].
In regard to claim 4 and analogous claim 14, Shen and Blieweiss teaches the processor of claim 1.
However, Shen and Blieweiss do not explicitly teach wherein the one or more sets of data are one or more tensors in a graph representation of the one or more neural networks.
Xu teaches wherein the one or more sets of data are one or more tensors in a graph representation of the one or more neural networks. (Xu, pg. 2, 2.2 Our Approach, paragraph 1, “Multiple front-end frameworks including TensorFlow [5], JAX [7], PyTorch [27] and Julia [6] already have lowering logic to transform their graph representation to XLA HLO graph, which can then be compiled into target executables if the accelerator has a compiler backend for XLA [one or more sets of data are one or more tensors in a graph representation]. XLA has a much smaller set of operators than front-end frameworks like TensorFlow. This reduces the burden of implementing a partitioner without harming generality, because the existing lowering from frontends performs the heavy-lifting to make it expressive.”)
Shen, Bieweiss and Xu are related to the same field of endeavor (i.e. optimizing machine learning). In view of the teachings of Xu, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Xu to Shen and Blieweiss before the effective filing date of the claimed invention in order to have highly efficient kernels. (Xu, pg. 6, Col. 2, paragraph 1, “In practice, the XLA compiler supports only limited degree of dynamism in tensor shapes, in order to ease the development of highly efficient operator kernels.”)
In regard to claim 7 and analogous claim 23, Shen and Blieweiss teaches the processor of claim 1.
Shen further teaches wherein the one or more dynamically configurable dimensions are one or more dimensions of tensor shapes, and the one or more circuits are to generate a kernel that takes one or more input values corresponding to the one or more dynamically configurable dimensions (Shen, pg. 4, Col. 1 (“A Tensor Type is designated by an n-dimensional shape (defined as a tuple of integers describing the tensor’s dimensions) and a data type (e.g. float32 or int64).”), pg. 8, Col. 2 (“We observe that latency on Nvidia GPU is higher than Intel CPU with Nimble. This is because the size of LSTM model is relative small so that it cannot fully utilize the massive parallelism in the GPU. The significant performance improvement of Nimble comes from two aspects: (a) utilizing the deep learning compiler for better kernel fusion and implementation, (b) encoding the control flow into platform-independent instructions with minimal overhead.”)).
However, Shen and Blieweiss do not explicitly teach wherein the one or more dynamically configurable dimensions are one or more dimensions of tensor shapes,
Xu teaches wherein the one or more dynamically configurable dimensions are one or more dimensions of tensor shapes, (Xu, pg. 6, Col. 2, paragraph 1, “…dynamism in tensor shapes, in order to ease the development of highly efficient operator kernels.”)
Blieweiss, Shen and Xu are combinable for the same rationale as set forth above with respect to
claim 4.
In regard to claim 8 and analogous claims 24 and 29, Shen and Blieweiss teaches the processor of claim 1.
Shen further teaches the information includes one or more constraints, and the one or more circuits are to generate a set of instructions that symbolically represent the one or more dynamically configurable dimensions and (Shen, pg. 4, Col. 1 (“In order to support dynamic data shapes, Nimble introduces a special dimension called Any to represent statically unknown dimensions. For example, we can represent a tensor type as Tensor[(1, 10, Any), float32],where the size of the third dimension in this tensor is unknown while the other two dimensions have concrete values.”)).
Blieweiss further teaches store the information in association with the set of instructions. (Blieweiss, paragraph 0049, “In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a specific instruction set 109.”)
However, Shen and Blieweiss do not explicitly teach wherein the one or more sets of data are one or more tensors in a graph representation of the one or more neural networks,
Xu teaches wherein the one or more sets of data are one or more tensors in a graph representation of the one or more neural networks, (Xu, pg. 2, 2.2 Our Approach, paragraph 1, “Multiple front-end frameworks including TensorFlow [5], JAX [7], PyTorch [27] and Julia [6] already have lowering logic to transform their graph representation to XLA HLO graph, which can then be compiled into target executables if the accelerator has a compiler backend for XLA [one or more sets of data are one or more tensors in a graph representation]. XLA has a much smaller set of operators than front-end frameworks like TensorFlow. This reduces the burden of implementing a partitioner without harming generality, because the existing lowering from frontends performs the heavy-lifting to make it expressive.”)
Blieweiss, Shen and Xu are combinable for the same rationale as set forth above with respect to
claim 4.
In regard to claim 11, Shen and Blieweiss teaches the processor of claim 10.
However, Shen and Blieweiss do not explicitly teach wherein the one or more compilers are to identify the one or more static constraints based, at least in part, on a set of rules associated with operations in a graph.
Xu teaches wherein the one or more compilers are to identify the one or more static constraints based, at least in part, on a set of rules associated with operations in a graph. (Xu, pg. 2, Col. 2, 2.2, paragraph 2, “Multiple front-end frameworks including TensorFlow [5], JAX [7], PyTorch [27] and Julia [6] already have lowering logic to transform their graph representation to XLA HLO graph, which can then be compiled into target executables if the accelerator has a compiler backend for XLA.” And pg. 6, Static Constraints, “ML accelerators get their performance edge via specialized hardware, such as vector and matrix units. In practice, the XLA compiler [wherein the one or more compilers] supports only limited degree of dynamism in tensor shapes, in order to ease the development of highly efficient operator kernels.
GSPMD is designed to work even with full static shape constraints [identify the one or more static constraints], but static shapes create a challenge for SPMD partitioning. When a computation is partitioned, it’s not always the case that all partitions have the same input/output shapes, because dimensions may not be evenly divisible by the number of partitions. In those cases, GSPMD rounds up the size of the shape to a multiple of partition count [based, at least in part, on a set of rules associated with operations in a graph.], and the data in that padded region can be arbitrary.”)
Blieweiss, Shen and Xu are combinable for the same rationale as set forth above with respect to
claim 4.
In regard to claim 17, Shen and Blieweiss teaches the processor of claim 10.
However, Shen and Blieweiss do not explicitly teach wherein the one or more sets of data are tensors in a graph, the one or more compilers are to identify the one or more static constraints based, at least in part, on a set of rules associated with operations in the graph, and are to generate a set of instructions that takes one or more input values corresponding to the one or more dimensions, wherein the one or more input values are to be generated based, at least in part, on the one or more static constraints
Xu teaches wherein the one or more sets of data are tensors in a graph, the one or more compilers are to identify the one or more static constraints based, at least in part, on a set of rules associated with operations in the graph, and are to generate a set of instructions that takes one or more input values corresponding to the one or more dimensions, wherein the one or more input values are to be generated based, at least in part, on the one or more static constraints (Xu, pg. 2, Col. 2, 2.2, paragraph 2, “Multiple front-end frameworks including TensorFlow [5], JAX [7], PyTorch [27] and Julia [6] already have lowering logic to transform their graph representation to XLA HLO graph, which can then be compiled into target executables if the accelerator has a compiler backend for XLA.” And pg. 6, Static Constraints, “ML accelerators get their performance edge via specialized hardware, such as vector and matrix units. In practice, the XLA compiler [wherein the one or more compilers] supports only limited degree of dynamism in tensor shapes, in order to ease the development of highly efficient operator kernels.
GSPMD is designed to work even with full static shape constraints [identify the one or more static constraints], but static shapes create a challenge for SPMD partitioning. When a computation is partitioned, it’s not always the case that all partitions have the same input/output shapes, because dimensions may not be evenly divisible by the number of partitions. In those cases, GSPMD rounds up the size of the shape to a multiple of partition count [based, at least in part, on a set of rules associated with operations in a graph.], and the data in that padded region can be arbitrary.”)
Blieweiss, Shen and Xu are combinable for the same rationale as set forth above with respect to
claim 4.
In regard to claim 18, Shen and Blieweiss teaches the processor of claim 10.
Blieweiss further teaches the neural network is to perform a task in an autonomous vehicle. (Blieweiss, paragraph 0194, “Parallel processor accelerated machine learning has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define the appropriate responses to specific training input. The parallel processors described herein can enable rapid training of the increasingly complex neural networks used for autonomous driving solutions…”)
However, Shen and Blieweiss do not explicitly teach wherein the one or more sets of data are tensors in a graph representation of the neural network of the one or more neural networks and
Xu teaches wherein the one or more sets of data are tensors in a graph representation of the neural network of the one or more neural networks and (Xu, pg. 2, 2.2 Our Approach, paragraph 1, “Multiple front-end frameworks including TensorFlow [5], JAX [7], PyTorch [27] and Julia [6] already have lowering logic to transform their graph representation to XLA HLO graph, which can then be compiled into target executables if the accelerator has a compiler backend for XLA [one or more sets of data are one or more tensors ibn a graph representation]. XLA has a much smaller set of operators than front-end frameworks like TensorFlow. This reduces the burden of implementing a partitioner without harming generality, because the existing lowering from frontends performs the heavy-lifting to make it expressive.”)
Shen, Bleiweiss, and Xu are combinable for the same rationale as set forth above with respect to
claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nicol et al (US Published Patent Application No. 20190279086, “Nicol”) teaches about data flow within graphs for machine learning.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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