Prosecution Insights
Last updated: April 19, 2026
Application No. 17/503,229

OPTOELECTRONIC PACKAGE STRUCTURE INCLUDING A THERMAL CONDUCTIVE ELEMENT FOR HEAT DISSIPATION

Non-Final OA §101§103§112
Filed
Oct 15, 2021
Examiner
GOLUB-MILLER, MARCIA A
Art Unit
2828
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
3 (Non-Final)
51%
Grant Probability
Moderate
3-4
OA Rounds
3y 11m
To Grant
78%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allow Rate
153 granted / 299 resolved
-16.8% vs TC avg
Strong +27% interview lift
Without
With
+26.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
22 currently pending
Career history
321
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
42.9%
+2.9% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
30.0%
-10.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 299 resolved cases

Office Action

§101 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 16, 19, 36-40 are rejected under 35 U.S.C. 101 because the claimed invention is not supported by either a credible asserted utility or a well-established utility. Claim 16 discloses limitations: “the through via is configured to transmit a signal between the heat source and the plurality of optoelectronic components”, and also discloses that “a plurality of optoelectronic components are laterally spaced apart from each other to define a space … the space is configured to accommodate the thermal conductive element”. However, it is a standard fact in the art of semiconductor circuits design that a through via is equivalent in its function to a single wire and is designed to connect two components to each other in a vertical direction in place of a wire. It is not physically possible for a single through via to connect to a plurality of spaced apart components and to connect all of the spaced apart elements to the heat source. Claims 16, 19, 36-40 are also rejected under 35 U.S.C. 112(a). Specifically, because the claimed invention is not supported by either a credible asserted utility or a well-established utility for the reasons set forth above, one skilled in the art clearly would not know how to use the claimed invention. The remainder of the claims are rejected for their dependence on claim 16. For the purpose of examination, the limitations as presented have been searched and considered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 8, 11, 12, 14, 15, 29, 33-35 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. Claim 8 discloses a limitation “a vertical extension line of a lateral surface of the heat source passes through the optoelectronic component”. There is no support for this limitation in the specification, a vertical extension line is not disclosed or described. The remainder of the claims are rejected for their dependence on claim 8. For the purpose of examination, the limitations as presented have been searched and considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 8, 11, 12, 14, 15, 29, 33-35, 37 and 39 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Claim 8 discloses a limitation “a vertical extension line of a lateral surface of the heat source”, this limitation is not explained in the specification. Claims 33 and 39 recite a limitation “non-overlap”, this is not a proper word and it does not appear in the specification. Where applicant acts as his or her own lexicographer to specifically define a term of a claim, the written description must clearly define the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so define that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The meaning of the term “non-overlap” in claims 33 and 39 cannot be ascertained. The meaning of the term “a vertical extension line” in claim 8 cannot be ascertained. The terms are indefinite because the specification does not clearly define the terms. Claim 37 recites limitations “a width of the first RDL” and “a width of heat source”. It is not clear from the claim in which direction the width is measured in relation to the rest of the structure and it is not clear if the direction for the first width measurement is the same as the direction for the second width measurement. The remainder of the claims are rejected for their dependence on claim 8. For the purpose of examination, the limitations as presented have been searched and considered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 24, 31, 32 are rejected under 35 U.S.C. 103 as being unpatentable over Doany et al. (2019/0214280), hereinafter ‘280, and further in view of Erickson et al. (2022/0113480) hereinafter ‘480 and Ketterson et al. (2020/0176416) hereinafter ‘416. Regarding claim 1, Fig 4 of ‘280 discloses an optoelectronic package structure, comprising: 1. “a heat source [108] having a first surface [center top] and a second surface [bottom] opposite to the first surface; a thermal conductive element [402] disposed over the first surface [center top] of the heat source, wherein the thermal conductive element defines a thermal conduction path [vertical] by which heat is transferred from the heat source [108] to the thermal conductive element [402]; and a first optoelectronic component [106 right side] over the first surface [top] of the heat source and a second optoelectronic component [106 on left side] over the first surface [top] the heat source, wherein the first optoelectronic component [106 right side] and the second optoelectronic component [106 left side] are arranged along an axis [horizontal] different from the thermal conduction path [vertical], wherein the first surface [center top] of the heat source [108] is electrically isolated (it is connected to a heat sink),” ‘280 does not disclose electrical connections on the bottom of the device 108: “and the second surface [bottom] of the heat source [108] is configured for signal transmission.” However, paragraph 0041 of ‘280 discloses that “it should also be understood that the ground, power, or an electrical signal can be internal or external to the carrier die”. Additionally, carrier dies that have electrical connections on the bottom surface are well known in the art as evidenced by Fig 2A of ‘480 which discloses a carrier die (heat source) 214 that has electrical connections to electronic components 102 and 206 on its bottom surface, so as to enable signal transmission from these components to the photonic die 116 on top of the carrier die 214. It would have been obvious to one of ordinary skill in the art to incorporate the teachings of ‘480 into the device of ‘280 by providing electrical connections for signal transmission on the bottom surface of carrier die 108, since the combination would yield the predictable result of enabling signal transmission to the electronic components while minimizing the footprint of the overall device. Thus, the claimed invention would have been obvious before the effective filing date of the claimed invention because “all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395. Regarding claims 24, 31 and 32, ‘280 discloses an optoelectronic package as described above, but does not disclose that the device further includes a redistribution layer. However, redistribution layers disposed between the heat source and the first optoelectronic component, wherein the redistribution layer extends from the first optoelectronic component to the second optoelectronic component are well known elements in the art of semiconductor micro-electronics and are used for electrically interconnecting separate components, as evidenced by APA. One of ordinary skill in the art would be well aware of how to use them for their standard purposes, without needing any inventive steps and would not have any difficulty arranging them as needed in any desired shape and configuration for the purpose of carrying out the circuit design interconnect layout. In addition, Fig 6B of ‘416 discloses an RDL 70 that has a top side without electrical connections (insulating) in the center and with electrical connections 80 (conducting) on the right and left sides of the RDL. It would have been obvious to one of ordinary skill in the art to incorporate the RDL 70 of ‘416 into the device of ‘280 by inserting it between the carrier die 108 and the optoelectronic components 106. Thus, the claimed invention would have been obvious before the effective filing date of the claimed invention because “all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395. Combination of ‘280, ‘480 and ‘416 discloses: 24. “further comprising a redistribution layer (RDL) [70 of ‘416] disposed over the first surface [top] of the heat source [108], wherein the RDL [70 of ‘416] includes a first region [center] connected to the thermal conductive element [402] and a second region [right side] electrically connected to the first optoelectronic component [106 on right side].” 31. “wherein the first region [center] of the RDL [70 of ‘416] is configured to insulate electrical conductivity and to transfer heat from the heat source [108] to the thermal conductive element [402], and wherein the second region [right side] of the RDL [70 of ‘416] is configured to transmit a signal between the heat source [108] and the first optoelectronic component [106 on right side].” 32. “wherein the second region [right side] of the RDL [70 of ‘416] extends beyond a lateral surface of the heat source [60 of ‘416] and has a lateral surface substantially aligned with a lateral surface of the first optoelectronic component [106].” The precise shape and alignment of the RDL is a matter of design choice that does not have an effect on the performance of the device, and which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed RDL is significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) Admitted Prior Art The rejection of claims 14, 22, 24, 26 and 27 (redistribution layers, conductive pillars and encapsulants) based on the well-known in the art statement is taken to be admitted prior art (hereinafter APA) because applicant either failed to traverse the examiner’s assertion of official notice or that the traverse was inadequate, see MPEP 2144.03. Response to Arguments Applicant’s arguments with respect to claims 1, 8 and 16 filed on 01/02/26 have been considered but they are moot in view of the new grounds of rejection. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant’s attention is drawn to the references cited on form PTO-892 in the previous office action, which lists other references with similar features as the invention. Contact Info Any inquiry concerning this communication or earlier communications from the examiner should be directed to M. A. GOLUB-MILLER whose telephone number is (571)272-8602. The examiner can normally be reached on M-F 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached on (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /M. A. Golub-Miller/Primary Examiner, Art Unit 2828
Read full office action

Prosecution Timeline

Oct 15, 2021
Application Filed
May 16, 2025
Non-Final Rejection — §101, §103, §112
Aug 21, 2025
Response Filed
Oct 01, 2025
Final Rejection — §101, §103, §112
Dec 02, 2025
Interview Requested
Jan 02, 2026
Request for Continued Examination
Jan 08, 2026
Response after Non-Final Action
Feb 03, 2026
Non-Final Rejection — §101, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
51%
Grant Probability
78%
With Interview (+26.7%)
3y 11m
Median Time to Grant
High
PTA Risk
Based on 299 resolved cases by this examiner. Grant probability derived from career allow rate.

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