Attorney’s Docket Number: T100616US01
Filing Date: 10/18/2021
Applicant: Dadvand
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 1/7/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 12, mailed on 10/7/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/7/2026 has been entered.
Amendment Status
The RCE submission filed on 1/7/2026 as an amendment in reply to the final rejection in paper no. 12 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3 and 5-21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-17 are rejected under 35 U.S.C. 103 as being unpatentable over Arvin (US 2016/0079193) in view of Beck (US 2015/0279797).
Regarding claim 1, Arvin (see, e.g., fig. 1-6) shows most aspects of the instant invention including a method comprising:
Providing an array of electronic devices 100 on a wafer, and
Electrolytically depositing tin on exposed sidewalls of a copper seed layer and a copper bump (see, e.g., pars. 0060-0061/ll.1-4)
wherein:
Each device includes a diffusion barrier layer 108 on the wafer, the seed layer 110 on the barrier layer, and the copper bump 114 on the seed layer, and
Sidewalls of the barrier layer 108 are free of tin
Arvin, however, fails to teach the steps of immersing the devices in a tin electrolyte to chemically dissolve an exposed portion of the seed layer in the electrolyte and simultaneously form a layer of tin on the sidewalls of the bump. Beck (see, e.g., par. 0066) teaches that tin layers deposited by immersing the devices in a tin electrolyte are less sensitive to whisker growth, which would reduce undesired circuit shorts between copper bumps. The electrolyte chemically dissolves exposed surfaces of the metal layers and chemically displaces electrons from sidewalls of the bump. The displaced electrons combine with tin ions in the electrolyte to form a layer of tin on sidewalls of the bump. See, e.g., Beck: par. 0036 and 0057.
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the step of immersing the devices in the method of Arvin, as suggested by Beck, to reduce undesired circuit shorts between the copper bumps.
Regarding claim 2, Beck (see, e.g., par.0076) teaches immersion times of no more than 10 minutes.
Regarding claim 3, Beck teaches rising the devices with water (see, e.g., par. 0032).
Regarding claim 5, Arvin shows the method further comprising depositing a photoresist (PR) layer on the seed layer via spin coating (see, e.g., par. 0051/ll.1-4).
Regarding claim 6, Arvin shows the method further comprising etching to form openings in the PR layer (see, e.g., par. 0051/ll.4-6).
Regarding claim 7, Arvin shows the method further comprising depositing copper in the openings and on the seed layer 110 to form a copper bump bond 114 (see, e.g., par. 0051/ll.7-8 and fig. 2).
Regarding claim 8, Beck (see, e.g., par. 0029) suggests forming a Ni layer in the openings and on the Cu bump.
Regarding claim 9, Arvin (see, e.g., fig. 2) teaches forming a solder cap 116 in the openings and on the bump 114; and Beck (see, e.g., par. 0029) suggests forming a Ni layer in the openings and on the bump. They, however, fail to teach forming a Pd layer in the openings and on the Ni layer. In a similar embodiment, Beck teaches that a Pd layer would provide good wettability to the solder cap (see, e.g., par. 0071).
Accordingly, it would have been obvious at the time of the invention to include the steps of forming a Pd layer in the method of Arvin/Beck to provide good wettability for the solder cap.
Regarding claims 10 and 11, Arvin shows that the PR and an exposed portion of the diffusion barrier are removed via an etching process (see, e.g., pars. 0058 and 0067).
Regarding claim 12, Arvin (see, e.g., figs. 1-6) shows most aspects of the instant invention including a method comprising:
Providing an array of electronic devices 100 comprising a silicon wafer, and
Electrolytically depositing tin on exposed sidewalls of a copper seed layer 110 and a copper bump 114 (see, e.g., pars. 0060-0061/ll.1-4)
wherein:
Each device includes a TiW diffusion barrier layer 108 on the wafer, the seed layer 110 on the barrier layer, and the bump 114 on the seed layer, and
Sidewalls of the barrier layer 108 are free of tin
Arvin, however, fails to teach the steps of immersing the devices for less than 10 minutes in a tin electrolyte, and rising the devices with water. See also the comments stated above in paragraphs 7-8 and 10 with respect to claims 1 and 3, which are considered repeated here.
Regarding claims 13 and 14, see the comments stated above in paragraphs 11-13 with respect to claims 5-7, which are considered to be repeated here.
Regarding claims 15-17, see the comments stated above in paragraphs 14-17 with respect to claims 8-11, which are considered to be repeated here.
Response to Arguments
The applicant argues:
Arvin/Beck fail to disclose immersing the devices in a tin electrolyte to chemically dissolve an exposed portion of the copper seed layer in the electrolyte and simultaneously form a tin layer on sidewalls of the cupper bump.
The examiner responds:
Although Arvin does fail to teach the step of immersing the devices, Beck (see, e.g., par. 0066) teaches that tin layers deposited by immersing the devices in a tin electrolyte are less sensitive to whisker growth, which would reduce undesired circuit shorts between copper bumps. Accordingly, Beck suggests including the step of immersing the devices in the method of Arvin to reduce undesired circuit shorts between the copper bumps. The electrolyte chemically dissolves exposed surfaces of the metal layers and chemically displaces electrons from sidewalls of the bump. The displaced electrons combine with tin ions in the electrolyte to form a layer of tin on sidewalls of the bump. See, e.g., Beck: par. 0036 and 0057.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
March 2, 2026