DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
Response to Arguments
Applicant's arguments filed with the Remarks dated 2/6/25, 2/10/25, 2/21/25, with the appeal brief filed 2/10/25, and with the supplemental appeal brief filed 11/5/25 have been fully considered.
The following grounds of rejection have been withdrawn by the examiner.
The rejection of claims 21, 26 and 28 under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 5,424,249 (Ishibashi) in view of Stecher is withdrawn.
The rejection of claims 22, 23 and 29 under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 5,424,249 (Ishibashi) in view of Stecher as applied to claim 21, and further in view of Uchida is withdrawn.
The rejection of claims of 24, 25 and 27 under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 5,424,249 (Ishibashi) in view of Stecher as applied to claim 21, and further in view of Nagaraj is withdrawn.
The arguments regarding the other rejections are not persuasive.
On pages 12-13 of the Appeal Brief, Appellant argued no portion of UV LED chip 205 (corresponding to the recited die) is configured to be exposed to an environment of the packaged UV LED 200 / 300 (corresponding to the package in Figures 2 / 3 of Toita) as recited in claim 1. Therefore, Examiner agrees with Appellant on page 13 of the Appeal Brief that this argument concerns features Toita is recited as disclosing.
In response, this phrase is functional and not part of a non-obvious technical application. First, "configured to be" often implies "capable of" (functional language) which can be scrutinized for prior art, as it is commonly used to describe functional structure. Second, simply exposing an IC to an environment is not enough on its own a patentable limitation that is be part of a new, non-obvious package structure. The language would be considered and given patentable weight if the claim included specific structural details of how it is exposed (e.g., "a pressure / temperature sensor disposed on a die surface, the die surface encapsulated within a package, the pressure / temperature sensor exposed to an environment outside the package through a port / hole in the encapsulant".) The die 205 in Toita is capable of such a configuration.
Therefore, even if this specific phrasing is common in patent claims, the surrounding technical details are not robust and specific enough to overcome "obviousness" or "mere capability" rejection.
The motivation to combine the references is providing a metal wall having two regions with different widths in Toita would be obvious to provide a vertical interlocking structure which can be produced at low cost that clamps part of the wall to the molding as taught by Stecher ([0059]). This combination does not represent “improper hindsight” as argued by Appellant on page 18 of the Appeal Brief.
Rather, because providing a metal wall on the surface of a die is well-known in the package art, it would have been obvious to substitute the wall 10 in Stecher for the wall 305 in Toita as combined.
On pages 18-20 of the Appeal Brief, Appellant argued it is not possible that the width of one region of the metal wall is wider than the width of another region of the metal wall in Stecher. Therefore, this argument concerns features Stecher is recited as teaching.
In response, as stated above, Stecher teaches a metal wall 10 including a top region or projection 41 having a wider width than and stacked on a bottom region.
Therefore, the features in Stecher read on the recited metal wall.
The motivation to combine the references is providing a metal wall having two regions with different widths in Toita would be obvious to provide a vertical interlocking structure which can be produced at low cost that clamps part of the wall to the molding as taught by Stecher ([0059]). This combination does not represent “improper hindsight” as argued by Appellant on page 20 of the Appeal Brief.
Rather, because providing a metal wall on the surface of a die are both well known in the package art, it would have been obvious to substitute the wall 10 in Stecher for the wall 305 in Toita as combined.
Accordingly, Stecher properly modifies Toita and it would have been obvious to combine the two references.
On page 21 of the Appeal Brief, Appellant did not provide arguments as to why dependent claim 2 distinguishes over the combination of references.
On pages 21-22 of the Appeal Brief, Appellant argued Toita shows that wall 225 is the same height as molding 220 in Figure 2 and wall 305 is at a height above molding 220 in Figure 3.
Whereas claim 3 recites the molding extends to a height that is about equal to a heigh of the first region of the metal wall. Whereas claim 4 recites the molding extends to a height that is greater than a height of the first region of the metal wall.
As discussed above, Toita shows a metal wall 305 and Stecher shows a metal wall 10 having two regions. Providing a height of the first region of the metal wall about the same height as the molding does not contribute to its intended purpose which is to prevent the molding from flowing over the metal wall. In fact, this object is achieved not only by the metal wall 305 in Toita and is well known in the art (e.g., U.S. Patent Application Publication No. 2005/0046044 to Theuss was listed as a pertinent reference on PTO-892 along with the Final Rejected dated September 25, 2024). In Theuss a metal wall 45 is provided on, circumscribes and extends from an active surface 47 of a die 4 which prevents molding 101 from flowing over the metal wall.
The metal walls of Toita and Stecher, like the metal wall shown in Figure 1 of the instant invention, prevents the molding from flowing over the metal wall. Also, in Stecher, the shape of the second region of the metal wall, like the metal wall shown in Figure 1 of the instant invention, provides a locking feature the prevents the wall from disconnecting from the molding.
Accordingly, neither the shape of the metal nor the height of the metal wall are essential for preventing the molding from flowing over the metal wall in general. The shape merely provides locking to the molding and the height is a feature that can be optimized.
Therefore, the limitations of claims 3 and 4 do not overcome the combination of Toita and Stecher because the height of the molding can be controlled during processing.
On pages 22-23 of the Appeal Brief, Appellant argued Stecher does not show second region 41 of the metal wall 10 overhangs a portion of the interface region of the die.
Whereas claim 5 recites a portion of the second region of the metal wall overhangs the interface region of the die.
In response, an interface region on a die can refer to several different physical and functional boundaries, depending on the context of the device architecture. The die 205 in Stecher has at least a semiconductor dielectric interface region (includes semiconductor base surface 1, passivation P, oxide O, and remaining chip RC) and a die attach interface region (includes Met, W/Ti, Cu-S, and remaining chip RC).
As discussed on page 8 of the Final Rejection mailed 9/25/2024, Stecher shows a metal wall 10 having a second region 41 that overhangs the interface region including Met. The combination does not represent “improper hindsight” as argued by Appellant on page 23 of the Appeal Brief.
Rather, because providing a metal wall overhanging an interface region is well-known in the package art, it would have been obvious to substitute the wall 10 in Stecher for the wall 305 in Toita as combined.
The rejection of claims 1-5 as unpatentable over Toita in view of Stecher is modified below.
On pages 25-26 of the Appeal Brief, Appellant argued Nagaraj shows almost a triangular shaped mold lock.
Whereas claim 6 recites the second region of the metal wall has a semicircle cross section.
Under MPEP § 2144.04, changing a shape (e.g., from one surface to a semicircular one) may be considered obvious because it is merely a change in relative dimension or a known, predictable modification. Appellant has not presented any arguments that the semicircular shape provides a new or unexpected function (e.g., improved structural integrity, better locking, or reinforces wall).
Further, the cross section of the second region (top) of the wall 21 in Nagaraj appears to be just as semicircular as the second regions 218 and 840 of the walls shown in Figures 2 and 16, respectively of the instant application.
Therefore, the semicircular cross section is considered obvious.
On page 26 of the Appeal Brief, Appellant did not provide arguments as to why dependent claim 7 distinguishes over the combination of references.
Accordingly, the rejection of claims 6, 7 as being unpatentable over Toita in view of Stecher is maintained below.
On page 28 of the Appeal Brief, Appellant did not provide arguments as to why dependent claims 8-10 distinguish over the combination of references.
On pages 39-46 of the Appeal Brief, Appellant argued no portion of UV LED chip 205 (corresponding to the recited die) is exposed to an environment of the packaged UV LED 200 / 300 (corresponding to the package in Figures 2 / 3 of Toita). Therefore, Examiner agrees with Appellant on page 41 of the Appeal Brief that this argument concerns features Toita is recited as disclosing.
In response, this phrase is not part of a non-obvious technical application. Simply exposing an IC to an environment is not enough on its own a patentable limitation that is be part of a new, non-obvious package structure. The language would be considered and given patentable weight if the claim included specific structural details of how it is exposed (e.g., "a pressure / temperature sensor disposed on a die surface, the die surface encapsulated within a package, the pressure / temperature sensor exposed to an environment outside the package through a port / hole in the encapsulant".) The die 205 in Toita is capable of such a configuration.
Therefore, even if this specific phrasing is common in patent claims, the surrounding technical details are not robust and specific enough to overcome "obviousness" rejection.
The motivation to combine the references is providing a metal wall having two regions with different widths in Toita would be obvious to provide a vertical interlocking structure which can be produced at low cost that clamps part of the wall to the molding as taught by Stecher ([0059]). This combination does not represent “improper hindsight” as argued by Appellant on page 41 of the Appeal Brief.
Rather, because providing a metal wall on the surface of a die is well-known in the package art, it would have been obvious to substitute the wall 10 in Stecher for the wall 305 in Toita as combined.
On pages 46-47 of the Appeal Brief, Appellant argued it is not possible that the width of one region of the metal wall is wider than the width of another region of the metal wall in Stecher. Therefore, this argument concerns features Stecher is recited as teaching.
In response, as stated above, Stecher teaches a metal wall 10 including a top region or projection 41 having a wider width than and stacked on a bottom region.
Therefore, the features in Stecher read on the recited metal wall.
The motivation to combine the references is providing a metal wall having two regions with different widths in Toita would be obvious to provide a vertical interlocking structure which can be produced at low cost that clamps part of the wall to the molding as taught by Stecher ([0059]). This combination does not represent “improper hindsight” as argued by Appellant on page 20 of the Appeal Brief.
Rather, because providing a metal wall on the surface of a die are both well known in the package art, it would have been obvious to substitute the wall 10 in Stecher for the wall 305 in Toita as combined.
Accordingly, Stecher properly modifies Toita and it would have been obvious to combine the two references.
On page 49 of the Appeal Brief, Appellant did not provide arguments as to why dependent claim 26 distinguishes over the combination of references.
On page 49 of the Appeal Brief, Appellant argued Stecher does not show second region 41 of the metal wall 10 overhangs a portion of the interface region of the die.
Whereas claim 28 recites a portion of the second region of the metal wall overhangs the interface region of the die.
In response, an interface region on a die can refer to several different physical and functional boundaries, depending on the context of the device architecture. The die 205 in Stecher has at least a semiconductor dielectric interface region (includes semiconductor base surface 1, passivation P, oxide O, and remaining chip RC) and a die attach interface region (includes Met, W/Ti, Cu-S, and remaining chip RC).
As discussed on page 13 of the Final Rejection mailed 9/25/2024, Stecher shows a metal wall 10 having a second region 41 that overhangs the interface region including Met. The combination does not represent “improper hindsight” as argued by Appellant on page 49 of the Appeal Brief.
Rather, because providing a metal wall overhanging an interface region is well-known in the package art, it would have been obvious to substitute the wall 10 in Stecher for the wall 305 in Toita as combined.
The rejection of claims 21, 26, 28 as unpatentable over Toita in view of Stecher is modified below.
On page 53 of the Appeal Brief, Appellant did not provide arguments as to why dependent claims 24, 25, and 27 distinguish over the combination of references.
Accordingly, the rejection of claims 24, 25, and 27 over Toita, and Stecher and Nagaraj is maintained below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2015/0287894 (Toita) in view of U.S. Patent Application Publication No. 2005/0127534 (Stecher).
Toita discloses
1. (Currently Amended) An integrated circuit package 300 comprising:
a die 205 comprising an interface region 215 situated on a surface of the die 205, wherein the interface region 215 is configured to be exposed to an environment of the IC package (circular language because the IC package is the subject of the claim; interpreted as exposed outside of molding 220);
305 mounted on the surface of the die 205 that circumscribes the interface region 215 and extends from the surface (side surface) of the die 205 (Fig. 3) to a wall height (above molding 220);
a molding (220) encasing a remaining portion of the die, wherein the molding has a height that extends from the surface of the die to a level that is less than the wall height of the metal wall (Fig. 3).
Note that limitations relating to size are not sufficient to patentably distinguish over the prior art. (See MPEP 2144.04 IV. A.)
Even though Toita discloses the material for barrier layer 225 is an encapsulant in paragraph [0030] immediately surrounding (i.e., circumscribing) the die 205, in paragraph [0033] Toita discloses barrier layer 225 can be replaced by barrier layer 305, which is a non-encapsulated material, which may include metal.
Toita fails to disclose a metal wall comprising a first region and a second region that is stacked on the first region, the first region having a first width and the second region having a second width, the second width being greater than the first width.
Stecher teaches
An integrated circuit (IC) package (Fig. 2B) comprising:
a metal wall 10 mounted on the surface of the die 2 and extends from the surface of the die 2 to a wall height 40, the metal wall 10 comprising a first region (bottom portion) and a second region 41 (top projection) that is stacked on the first region (bottom portion), the first region (bottom portion) having a first width and the second region 41 (top projection) having a second width, the second width being greater than the first width (Fig. 2B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal wall having two regions with different widths in Toita. The motivation would be to provide a vertical interlocking structure which can be produced at low cost that clamp part of the wall to the molding as taught by Stecher ([0059]).
Stecher teaches
2. (Original) The IC package of claim 1, wherein the metal wall (10) is formed of copper ([0059]).
It would have been obvious to substitute equivalents, the aluminum in Toita for the copper in Stecher, known for the same purpose. (See MPEP 2144.06 II.)
Toita discloses
3. (Original) The IC package of claim 1, wherein the molding (220) extends to a height that is about equal to a height of the first region (225) of the metal wall (305/225).
Stecher teaches
4. (Original) The IC package of claim 1, wherein the molding (3) extends to a height that is greater than a height of the first region (bottom) of the metal wall (10).
Stecher teaches
5. (Original) The IC package of claim 1, wherein a portion of the second region (41) of the metal wall (10) overhangs the interface region (Met) of the die (RC).
Claim(s) 6, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toita in view of Stecher as applied to claim 1 above, and further in view of U.S. Patent No. 5,278,446 (Nagaraj).
The combination of Toita and Stecher fails to teach
6. (Original) The IC package of claim 1, wherein the second region of the metal wall has a semicircle cross section.
Nagaraj teaches
An integrated circuit (IC) package (Fig. 2) comprising:
a metal wall (21), wherein the second region (top) of the metal wall has a semicircle cross section (Fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal wall having a semicircle cross-section shape in the modified device of Toita. This shape would be a matter of design choice. (See MPEP 2144.04 I and IV. B.)
Nagaraj teaches
7. (Original) The IC package of claim 1, wherein the second region (top) of the metal wall (21) has a planer surface on an end distal to the die (12).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toita in view of Stecher as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2012/0322208 (Uchida).
The combination of Toita and Stecher fails to teach
8. (Original) The IC package of claim 1, wherein the surface of the die is a first surface, the IC package further comprising:
an interconnect, wherein a second surface of the die is mounted on a die pad of the interconnect; and
a wire bond that is coupled to the first surface of the die and to a pad of the interconnect.
Uchida teaches
An integrated circuit (IC) package (108) comprising:
wherein the surface of the die (101) is a first surface (top), the IC package further comprising:
an interconnect (104), wherein a second surface (bottom) of the die (101) is mounted on a die pad (middle) of the interconnect (104); and
a wire bond (105) that is coupled to the first surface of the die (101) and to a pad (unlabeled) of the interconnect (104).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an interconnect having a die pad in the modified device of Toita. The motivation is that mounting a die on a die pad is well-known in the art as shown in Uchida. (See MPEP 2144.03)
Uchida teaches
9. (Original) The IC package of claim 1, wherein the metal wall (102) forms a ring ([0056]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a wall having a ring shape in the modified device of Toita. This shape would be a matter of design choice. (See MPEP 2144.04 I and IV. B.)
Note the diameter/size of the ring below is not sufficient to patentably distinguish over Uchida. (See MPEP 2144.04 IV. A.)
10. (Original) The IC package of claim 9, wherein the ring has a diameter of 55-60 micrometers.
Claim(s) 21, 26, 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toita in view of Stecher.
Toita discloses
21. (Currently Amended) An integrated circuit (IC) package (Figs. 1, 4), comprising:
a cavity (unlabeled cavity that die sits in) circumscribing an interface region (215) on a surface of a die (205), the cavity (unlabeled) extending from the surface of the die (205) to a first height (Fig. 3);
a metal wall 305 in the cavity (unlabeled) mounted on the surface of the die 205 that circumscribes the interface region 215 of the die 205 and extends from the surface (side surface) of the die 205 (Fig. 3) to a first height (above molding 220); and
a mold (220) to encasing the die (205), such that the interface region (215) is exposed to an environment of the IC package (circular language because the IC package is the subject of the claim; interpreted as exposed outside of molding 220), and the mold (220) extends from the surface of the die (205) to a height less than the second height of the metal wall.
Note that limitations relating to size are not sufficient to patentably distinguish over the prior art. (See MPEP 2144.04 IV. A.)
Even though Toita discloses the material for barrier layer 225 is an encapsulant in paragraph [0030] immediately surrounding (i.e., circumscribing) the die 205, in paragraph [0033] Toita discloses barrier layer 225 can be replaced by barrier layer 305, which is a non-encapsulated material, which may include metal.
Toita fails to disclose
wherein the metal wall comprises a first region having a first width, the first region extending from the surface of the die to the first height, and a second region stacked on the first region, and the second region extending from the first height to a second height.
Stecher teaches
An integrated circuit (IC) package (Fig. 2B) comprising:
metal in the cavity (unlabeled) forming a metal wall 10, wherein the metal wall 10 comprises a first region (bottom portion) and a second region 41 (top projection) that is stacked on the first region (bottom portion), the first region (bottom portion) having a first width and the second region 41 (top projection) having a second width, the second width being greater than the first width (Fig. 2B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal wall having two regions with different widths in Toita. The motivation would be to provide a vertical interlocking structure which can be produced at low cost that clamp part of the wall to the molding as taught by Stecher ([0059]).
Toita discloses a solder ball (140)
26. (Currently Amended) The IC package of claim 21, further including one of a solder ball in the cavity and solder paste in the cavity.
It would have been obvious to select solder based on its suitability for the die bonding material in Toita. (See MPEP 2144.07)
Stecher teaches
28. (Previously Presented) The IC package of claim 21, wherein a portion of the second region (41) of the metal wall (10) overhangs the interface region (Met) of the die (RC).
Claim(s) 22, 23, 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toita in view of Stecher as applied to claim 21 above, and further in view of Uchida.
The combination of references fails to teach
22. (Previously Presented) The IC package of claim 21, wherein the metal wall has a ring shape.
Uchida teaches
An integrated circuit (IC) package (108) comprising:
a wall (102), wherein the wall (102) has a ring shape ([0056]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a wall having a ring shape in the modified device of Toita. This shape would be a matter of design choice. (See MPEP 2144.04 I and IV. B.)
Note the diameter/size of the wall below is not sufficient to patentably distinguish over Uchida. (See MPEP 2144.04 IV. A.)
23. (Previously Presented) The IC package of claim 22, wherein the metal wall has a diameter of 55-60 micrometers.
Uchida teaches
29. (Previously Presented) The IC package of claim 21, further comprising a wire bond (105) coupling the surface of the die (101) to a pad (unlabeled) of an interconnect (104) to electrically couple the surface of the die (101) to the pad (unlabeled) of the interconnect (104).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an interconnect having a die pad in the modified device of Toita. The motivation is that mounting a die on a die pad is well-known in the art as shown in Uchida.
Claim(s) 24, 25, 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toita in view of Stecher as applied to claim 21 above, and further in view of Nagaraj.
The combination of references fails to teach
24. (Previously Presented) The IC package of claim 21, wherein the second region of the metal wall has a semicircle cross section.
Nagaraj teaches
An integrated circuit (IC) package (Fig. 2) comprising:
a metal wall (21), wherein the second region (top) of the metal wall has a semicircle cross section.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal wall having a semicircle cross-section shape in the modified device of Toita. This shape would be a matter of design choice. (See MPEP 2144.04 I and IV. B.)
Stecher teaches
25. (Currently Amended) The IC package of claim 24, wherein depositing the metal in the cavity comprises copper.
It would have been obvious to substitute equivalents, the aluminum in Toita for the copper in Stecher, known for the same purpose. (See MPEP 2144.06 II.)
Nagaraj teaches
27. (Previously Presented) The IC package of claim 26, wherein a surface of the metal wall (21) distal from the surface of the die (12) is planer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2002/0034022 (Nakamura), 2006/0091515 (Weng), 2011/0036174 (Hooper) teach a package including a metal wall for preventing molding material from flowing onto a sensor region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893