Prosecution Insights
Last updated: October 02, 2026
Application No. 17/508,009

IC PACKAGE WITH INTERFACE REGION

Non-Final OA §112
Filed
Oct 22, 2021
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
4 (Non-Final)
72%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
361 granted / 502 resolved
+3.9% vs TC avg
Strong +23% interview lift
Without
With
+23.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
57 currently pending
Career history
551
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
57.7%
+17.7% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
19.4%
-20.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 502 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see Remarks, filed 6/3/26, with respect to the rejection(s) of claim(s) 1-10, 21-29 under 35 USC §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an objection and rejection under 35 USC § 112. Claim Objections Claim 8 is/are objected to because of the following informalities: The second occurrence of “IC package” is redundant. Suggested amendment: 8. (Currently Amended) The IC package of claim 1, wherein the surface of the die is a first surface, and further comprising: an interconnect, wherein a second surface of the die is mounted on a die pad of the interconnect; and a wire bond that is coupled to the first surface of the die and to a pad of the interconnect. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-10, 21-46 is / are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 and 21 recite “the interface region is exposed to an environment of the IC package.” The phrase does not clearly identify the physical environment to which the interface region is exposed. Because the IC package itself is the claimed article, it is unclear whether the recited “environment” refers to an ambient environment external to the IC package, an internal environment within the IC package, a region outside the molding, or some other environment associated with the package. Suggested amendment: 1. (Currently amended) An integrated circuit (IC) package comprising: a die comprising an interface region situated on a surface of the die a metal wall mounted on the surface of the die that circumscribes the interface region and extends from the surface of the die to a wall height, the metal wall comprising a first region and a second region that is stacked on the first region, the first region having a first width and the second region having a second width, the second width being greater than the first width; and a molding encasing a remaining portion of the die, wherein the molding has a height that extends from the surface of the die to a level that is less than the wall height of the metal wall, wherein the interface region is exposed from the molding. Suggested amendment: 21. (Currently Amended) An integrated circuit (IC) package, comprising: a cavity circumscribing an interface region on a surface of a die, the cavity extending from the surface of the die to a first height; metal in the cavity forming a metal wall circumscribing the interface region of the die, wherein the metal wall comprises a first region having a first width, the first region extending from the surface of the die to the first height, and a second region stacked on the first region, the second region having a second width greater than the first width and the second region extending from the first height to a second height; and a mold encasing the die, such that the interface region is exposed from the mold, and the mold extends from the surface of the die to a height less than the second height of the metal wall. Claim 25 recites “wherein depositing the metal in the cavity comprises copper.” Claim 25 is directed to an IC package, yet the limitation is expressed in terms of a process instead of a product. Further, it is unclear how the act of depositing “comprises copper.” Suggested amendment: 25. (Currently Amended) The IC package of claim 24, wherein The other claims are rejected as being dependent on an indefinite base claim. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2021/0017018 (Liu), 2017/0081175 (Steiert), 2009/0215216 (Huang), teach a package including a wall for preventing molding material from flowing onto a sensor region. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 9 earlier events
Feb 21, 2025
Response after Non-Final Action
Oct 21, 2025
Response after Non-Final Action
Oct 23, 2025
Response after Non-Final Action
Nov 05, 2025
Response after Non-Final Action
Nov 07, 2025
Response after Non-Final Action
Feb 03, 2026
Non-Final Rejection mailed — §112
Jun 03, 2026
Response Filed
Aug 26, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707619
STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT
5y 7m to grant Granted Aug 11, 2026
Patent 12708058
SEMICONDUCTOR DEVICE
3y 4m to grant Granted Aug 11, 2026
Patent 12696774
SEMICONDUCTOR DEVICE AND CONTROL SYSTEM
3y 3m to grant Granted Jul 28, 2026
Patent 12690503
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 7m to grant Granted Jul 21, 2026
Patent 12690484
BONDING PAD STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
3y 2m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

4-5
Expected OA Rounds
72%
Grant Probability
95%
With Interview (+23.2%)
3y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 502 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month