Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 12, 25, 27, 30, 42, 43, 45, and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Kamgaing et al. (US 20220406523, hereinafter Kamgaing) in view of Kim (US 20160336311).
Regarding claim 1, Fig. 5 of Kamgaing discloses an interposer structure 500, comprising: a substrate portion 515; a wiring portion 502 over the substrate portion; an interconnect portion 514 over the wiring portion; a through via (not labeled) penetrating the substrate portion and the wiring portion; and a 3D capacitor structure 501 surrounded by the wiring portion; wherein the interconnect portion comprises a first metal wire 516 electrically coupled to the 3D capacitor structure, and the 3D capacitor structure comprises a 3D capacitor unit cell between a top metal plate 510 and a bottom metal plate 519 in the wiring portion, wherein the top metal plate is disposed on an upper side of the 3D capacitor structure, and the bottom metal plate is disposed on a lower side opposite to the upper side of the 3D capacitor structure, and the top metal plate and the bottom metal plate are plain metal plates parallel to each other, wherein each of the 3D capacitor unit cells comprises: a first conductor film 506, comprising: a first portion (lower portion of 506) connected to the bottom metal plate 519; and a second portion (upper portion of 506) connected to the first portion and extending toward the top metal plate from the bottom metal plate; and a second conductor film (portion of 510 extending down into trenches) adjacent to the first conductor film and connected to the top metal plate and extending toward the bottom metal plate from the top metal plate, wherein the second conductor film is vertically interleaving with the second portion of the first conductor film.
Kamgaing does not specifically disclose a plurality of 3D capacitor unit cells.
Fig. 4 of Kim discloses a semiconductor device comprising a plurality of 3D capacitor unit cells 113. In view of such teaching, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of capacitor unit cells as taught by Kim for the purpose of increasing the capacity of the device.
Regarding claim 3, Fig. 5 of Kamgaing discloses the through via (not labeled) penetrates the substrate portion 515, the wiring portion 502, and the interconnect portion 515, and the through via is disconnected from the first metal wire.
Regarding claim 4, the limitations “the interconnect portion is configured to bond with a first semiconductor die” and “the substrate portion is configured to bond with a package substrate” are both functional/intended use limitations that do not structurally distinguish the claimed invention over the prior art. The structure shown in Fig. 5 of Kamgaing is capable of being bonding with a die and a package substrate, therefore is considered to be “configured” to perform the recited intended use/function.
Regarding claim 12, Kamgaing does not specifically disclose a height of each of the 3D capacitor unit cells is in the range of about 1 µm to about 2 µm. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a capacitor height within the claimed range, since it has been held that when the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 25, the limitation “wherein the 3D capacitor structure is formed by a DRAM process” is a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art.
Regarding claim 27, Fig. 5 of Kamgaing discloses a concave type capacitor.
Regarding claim 30, Kamaing does not specifically disclose the 3D capacitor structure comprises a capacitance density greater than 1 µF/mm2. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a capacitance density within the claimed range, since it has been held that when the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 42, Fig. 5 of Kamgaing discloses a substrate portion 515; a wiring portion 502 over the substrate portion along a vertical direction; an interconnect portion 514 over the wiring portion along the vertical direction; a through via (not labeled) penetrating the substrate portion and the wiring portion along the vertical direction; a 3D capacitor structure 501 formed within the wiring portion, and the 3D capacitor structure comprises: a first plate 519 disposed in a first layer in the wiring portion; a second plate 510 disposed in a second layer in the wiring portion, the first layer and the second layer are located in different levels along the vertical direction in the wiring portion; at least a first contact 517 in contact with the first plate; and at least a second contact 516 in contact with the second plate, wherein a height difference between the first contact and the second contact is substantially equal to a height of the 3D capacitor unit cell along the vertical direction (height being the vertical distance between the bottom of contact 516 and the top of contact 517).
Kamgaing does not specifically disclose a plurality of 3D capacitor unit cells.
Fig. 4 of Kim discloses a semiconductor device comprising a plurality of 3D capacitor unit cells 113. In view of such teaching, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of capacitor unit cells as taught by Kim for the purpose of increasing the capacity of the device.
Regarding claim 43, Fig. 5 of Kamgaing discloses wherein the first plate 519 is disposed on a lower side of the 3D capacitor structure, and the second plate 510 is disposed on an upper side opposite to the lower side of the 3D capacitor structure, and the first plate and the second plate are plain metal plates parallel to each other, wherein each of the 3D capacitor unit cells comprises: a first conductor film 506, comprising: a first portion (lower portion of 506) connected to the first plate; and a second portion (upper portion of 506) connected to the first portion and extending toward the second plate from the first plate; and a second conductor film 508 adjacent to the first conductor film and connected to the second plate and extending toward the first plate from the second plate, wherein the second conductor film is vertically interleaving with the second portion of the first conductor film.
Regarding claim 45, Fig. 5 of Kamgaing discloses wherein the first contact 517 comprises a first depth along the vertical direction, the second contact 516 comprises a second depth along the vertical direction, and wherein the first depth is greater than the second depth. Note contact 517 is at a lower position, and therefore has a greater depth, than 516.
Regarding claim 47, Kamaing does not specifically disclose the 3D capacitor structure comprises a capacitance density greater than 1 µF/mm2. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a capacitance density within the claimed range, since it has been held that when the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 1, 3, 4, 7, 12, 25, and 27-30, 42, 43, 45, 47, and 48 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 9,991,333, hereinafter Liu) in view of Kim (US 20160336311).
Regarding claim 1, Fig. 1J of Liu discloses an interposer structure 600a, comprising: a substrate portion 200/212; a wiring portion 214/216/218 over the substrate portion; an interconnect portion 250 over the wiring portion; a through via 258/256/222/220/204 penetrating the substrate portion and the wiring portion; and a 3D capacitor structure 500a surrounded by the wiring portion 216; wherein the interconnect portion comprises a first metal wire 252/254 electrically coupled to the 3D capacitor structure, and the 3D capacitor structure comprises a plurality of 3D capacitor unit cells between a top metal plate 248 and a bottom metal plate 232 in the wiring portion, wherein the top metal plate is disposed on an upper side of the 3D capacitor structure, and the bottom metal plate is disposed on a lower side opposite to the upper side of the 3D capacitor structure, and the top metal plate and the bottom metal plate are plain metal plates parallel to each other, wherein each of the 3D capacitor unit cells comprises: a first conductor film 240, comprising: a first portion 240b connected to the bottom metal plate; and a second portion 240a connected to the first portion and extending toward the top metal plate from the bottom metal plate; and a second conductor film 248a adjacent to the first conductor film and connected to the top metal plate and extending toward the bottom metal plate from the top metal plate, wherein the second conductor film is vertically interleaving with the second portion of the first conductor film.
Liu does not specifically disclose a plurality of 3D capacitor unit cells.
Fig. 4 of Kim discloses a semiconductor device comprising a plurality of 3D capacitor unit cells 113. In view of such teaching, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of capacitor unit cells as taught by Kim for the purpose of increasing the capacity of the device.
Regarding claim 3, Fig. 1J of Liu discloses the through via 258/256/222/220/204 penetrates the substrate portion, the wiring portion, and the interconnect portion, and the through via is disconnected from the first metal wire.
Regarding claim 4, the limitations “the interconnect portion is configured to bond with a first semiconductor die” and “the substrate portion is configured to bond with a package substrate” are both functional/intended use limitations that do not structurally distinguish the claimed invention over the prior art. The structure shown in Fig. 1J of Liu is capable of being bonding with a die and a package substrate, therefore is considered to be “configured” to perform the recited intended use/function.
Regarding claim 7, Liu disclose the substrate portion is a semiconductor (col. 2, lines 38-40).
Regarding claim 12, Liu does not specifically disclose a height of each of the 3D capacitor unit cells is in the range of about 1 µm to about 2 µm. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a capacitor height within the claimed range, since it has been held that when the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 25, the limitation “wherein the 3D capacitor structure is formed by a DRAM process” is a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art.
Regarding claim 27, Fig. 1J of Liu discloses a concave type capacitor 500a.
Regarding claims 28 and 29, Fig. 1J of Liu discloses a discloses a dielectric of the 3D capacitor unit cell comprises Hafnium oxide (col. 9, lines 20-25).
Regarding claim 30, Liu does not specifically disclose the 3D capacitor structure comprises a capacitance density greater than 1 µF/mm2. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a capacitance density within the claimed range, since it has been held that when the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 42, Fig. 1J of Liu discloses a substrate portion 200/212 along a vertical direction; a wiring portion 214/216/218 over the substrate portion along the vertical direction; an interconnect portion 250 over the wiring portion along the vertical direction; a through via 258/256/222/220/204 penetrating the substrate portion and the wiring portion; a 3D capacitor structure 500a, and the 3D capacitor structure comprises: a first plate 232 disposed in a first layer in the wiring portion; a second plate 248 disposed in a second layer in the wiring portion, the first layer and the second layer are located in different levels along the vertical direction in the wiring portion; at least a first contact 202 in contact with the first plate; and at least a second contact 252/254 in contact with the second plate, wherein a height difference between the first contact and the second contact is substantially equal to a height of the 3D capacitor unit cell along the vertical direction (height being the vertical distance between the bottom of contact 252/254 and the top of contact 202).
Liu does not specifically disclose a plurality of 3D capacitor unit cells.
Fig. 4 of Kim discloses a semiconductor device comprising a plurality of 3D capacitor unit cells 113. In view of such teaching, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of capacitor unit cells as taught by Kim for the purpose of increasing the capacity of the device.
Regarding claim 43, Fig. 1J of Liu discloses wherein the first plate 232 is disposed on a lower side of the 3D capacitor structure, and the second plate 248 is disposed on an upper side opposite to the lower side of the 3D capacitor structure, and the first plate and the second plate are plain metal plates parallel to each other, wherein each of the 3D capacitor unit cells comprises: a first conductor film 240, comprising: a first portion 240b connected to the first plate; and a second portion 240a connected to the first portion and extending toward the second plate from the first plate; and a second conductor film 248a adjacent to the first conductor film and connected to the second plate and extending toward the first plate from the second plate, wherein the second conductor film is vertically interleaving with the second portion of the first conductor film.
Regarding claim 45, Fig. 1J of Liu discloses wherein the first contact 202 comprises a first depth along the vertical direction, the second contact 252/254 comprises a second depth along the vertical direction, and wherein the first depth is greater than the second depth. Note contact 202 is at a lower position, and therefore has a greater depth, than 252/254.
Regarding claim 47, Liu does not specifically disclose the 3D capacitor structure comprises a capacitance density greater than 1 µF/mm2. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a capacitance density within the claimed range, since it has been held that when the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 48, Liu does not specifically disclose the substrate portion comprises a glass substrate. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention since the use of a glass substrate is very well known in the art, and it has been held that the selection of a known material based on its suitability for its intended purpose is obvious (see MPEP 2144.07 and 2143 (I)(B)”substitution of one known element for another to obtain predictable results).
Allowable Subject Matter
Claims 2, 5, 6, 44, and 46 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW C LANDAU whose telephone number is (571)272-1731. The examiner can normally be reached M-F, 9:30-5:30.
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MATTHEW C. LANDAU
Supervisory Patent Examiner
Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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