DETAILED ACTION
Claims 1-30 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner recommends --Processor And Method For Loading A Microcode Patch From Cache Into Patch Memory--.
The lengthy replacement specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification, and as ensuring consistency between the specifications of this application and the related applications.
Drawings
The large number of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings.
Claim Interpretation
At least one claim is identified as including non-limiting contingent limitations. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 12, the claimed storing is only performed if the core is transitioned to the claimed power state. Thus, when the power state is not transitioned to, claim 12 sets forth no further step with respect to those in claim 11. The examiner recommends first claiming that the method further comprises transitioning the core to the power state so as to positively recite the transition and require the storing to occur.
Referring to claim 14, the broadest reasonable interpretation includes when the transition of claim 12 does not occur and when the core is not in a runtime power state (claim 14, line 2). In such a situation, claim 14 sets forth no further step with respect to those in claim 11.
Claim 15 is similarly contingent as claim 14 and sets forth no further step with respect to those in claim 11.
Referring to claim 19, the reloading only occurs when the overwrite occurs. Thus, claim 19, under one interpretation, sets forth no further step with respect to those in claim 11. Applicant will have to positively recite the overwriting as a step to remove the contingency if applicant combines claims 11 and 19.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 6-11, 16-21, and 26-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6-8, 1, 9-10, 15-17, 10, 18-19, 24-26, 19, and 27, respectively, of U.S. Patent No. 11,526,352. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘352 anticipate the instant claims. Of note, reloading “when execution…is complete” (e.g. claim 1 of ‘352) anticipates reloading “after execution…is complete” (e.g. instant claim 9)
Claims 2-5, 12-15, and 22-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-5, 11-14, and 20-23, respectively, of ‘352 in view of Jahagirdar (as referenced below in the prior art rejections).
Referring to claims 2, 12, and 22, these claims are mostly anticipated by claims 2, 11, and 20, respectively, of ‘352, with the exception that the claims of ‘352 do not teach that the power state does not shut down the cache. However, Jahagirdar has taught an on-die cache (FIG.2A, 340) within the processor that maintains power during the C6 power state (of the ACPI standard) so as to retain the data needed by the processor for quick restoration of that data when the processor is powered back on. See paragraphs [0052]-[0055] and [0060]. As such, to allow for quickly resuming state after powering down, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claims 2, 12, and 22 of ‘352 such that the power state does not shut down the cache.
Claims 1, 6-11, 16-21, and 26-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,429,385. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘385 anticipate the instant claims. Of note:
The third instruction of ‘385 corresponds to the instruction of instant claim 1.
With respect to instant claim 6, the cache of claim 1 of ‘385 is not user accessible because cache is not addressed like the register file and system DRAM.
With respect to instant claim 7, wherever the code that loads the patch set from cache resides in ‘385 may be considered part of the patch memory.
Claims 2-5, 12-15, and 22-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 1 of ‘385 in view of Jahagirdar.
Of note, claims 2, 12, and 22 are obvious over claims of ‘385 in view of Jahagirdar for similar reasoning given above for claims of ‘352.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-8, 10-12, 14-18, 20-22, 24-28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baumberger et al., U.S. Patent Application Publication No. 2007/0088939 A1 (as cited by applicant).
Referring to claim 1, Baumberger has taught a processor (FIG.2, processor 12) comprising:
an execution circuit to execute micro-operations (FIG.2, execution circuit 24, which executes micro-operations from UROM and/or URAM);
a cache (FIG.2, cache 26); and
a microcode sequencer circuit comprising a patch memory (FIG.2, URAM 112, which stores patches (paragraph [0016]). Alternatively, the UROM 110 and URAM 112 may make up the patch memory (paragraph [0016] refers to this combination as the “microcode memory”). The patch memory may be considered part of the microcode sequencer circuit, which sequences through appropriate sequences of microcode for a given decoded macro-instruction (paragraph [0006])), wherein the microcode sequencer circuit is to:
determine that an instruction requested for execution is to be patched (see FIG.3, steps 320-370 and paragraphs [0018], [0020], and [0023]. A patch will be loaded on demand for an instruction, if the patch is not already in URAM),
cause, in response to the determination that the instruction requested for execution is to be patched, execution of patch code by the execution circuit to load a patch set of at least one micro-operation for the instruction that is to be patched into the patch memory from the cache (see paragraphs [0029] and [0032]-[0033]. To summarize, in response to determining the instruction is to be patched (FIG.3, steps 320-370), the required patch is decrypted and authenticated and stored in cache 26. This patch is then loaded, by patch code 115, from cache into URAM (FIG.3, step 380)), and
cause execution of the patch set of at least one micro-operation for the instruction from the patch memory by the execution circuit (see FIG.3, step 395. The loaded micro-operation patch will be sent to the execution circuit for execution).
Referring to claim 6, Baumberger has taught the processor of claim 1, wherein the cache is not user accessible (a cache is not user-accessible like a register file or DRAM because a user cannot designate a cache location to store operands).
Referring to claim 7, Baumberger has taught the processor of claim 1, wherein the microcode sequencer circuit is to cause the execution of the patch code from the patch memory (from FIG.2, the sequencer causes execution of patch code 115 from UROM, which, again, is part of patch/microcode memory (paragraph [0016])).
Referring to claim 8, Baumberger has taught the processor of claim 1, wherein firmware, in non-transitory storage coupled to the processor, comprises an instruction that when decoded and executed by the processor is to cause the processor to store the patch set of at least one micro-operation into the cache (see paragraph [0027], last sentence).
Referring to claim 10, Baumberger has taught the processor of claim 1, wherein the microcode sequencer circuit is to cause, in response to a request for execution of a second instruction, a second patch set of at least one micro-operation, different than the patch set, to be loaded into the patch memory from the cache, and execution of the second patch set of at least one micro-operation for the second instruction from the patch memory by the execution circuit (the patch operation of Baumberger described above is the same for any instruction that needs to be patched. All instructions will go through the flow of FIG.3 and be patched where necessary. For instance, there could be two separate ADD instructions that need to be patched as explained in paragraph [0018]. Or, also from paragraph [0018], there may be a first instruction that is augmented by a patch and a second instruction that is completely overridden by another patch).
Claims 11, 16-18, 20-21, 26-28, and 30 are respectively rejected for similar reasons as claims 1, 6-8, 10, 1, 6-8, and 10. With respect to claim 28, the code may include code that updates firmware, which must occur in Baumberger because the firmware associates an instruction with a patch. So, when a new patch is released, the firmware must be updated to associate an instruction with the new patch.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 12-13, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Baumberger in view of Jahagirdar et al., U.S. Patent Application Publication No. 2007/0157036 (as cited by applicant).
Referring to claim 2, Baumberger has taught the processor of claim 1, wherein the cache comprises a section dedicated to store context information from a core comprising the execution circuit (see paragraph [0014]. In addition to patches, cache 26 stores context information, including instructions, data, and results, in a dedicated storage area (note that any given storage cell can only store one item and, thus, each cell is dedicated to storing whatever is stored to it at a given time). Baumberger has not taught that the context information is stored in the cache when the core is transitioned to a power state that shuts off voltage to the core but does not shut down the cache. However, Jahagirdar has taught an on-die cache (FIG.2A, 340) within the processor that maintains power during the C6 state (of the ACPI standard) so as to retain the data needed by the processor for quick restoration of that data when the processor is powered back on. See paragraphs [0052]-[0055] and [0060]). As such, to allow for quickly resuming state after powering down, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baumberger such that the context information is stored in the Baumberger’s cache 26 of the processor 12 when the core is transitioned to a power state that shuts off voltage to the core but does not shut down the cache.
Referring to claim 3, Baumberger, as modified, has taught the processor of claim 2, wherein the power state is a C6 power state according to an Advanced Configuration and Power Interface (ACPI) standard (again, see paragraph [0052] of Jahagirdar).
Claim 12-13 and 22-23 are respectively rejected for reasons set forth in the rejections of claims 2-3 and 2-3 above.
Claims 4-5, 14-15, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Baumberger in view of Jahagirdar and Branover et al., U.S. Patent Application Publication No. 2009/0235099 A1 (as cited by applicant).
Referring to claim 4, Baumberger, as modified, has taught the processor of claim 2, but has not taught wherein the patch set of at least one micro-operation for the instruction is to be loaded, when the core is in a runtime power state, into the patch memory from the section of the cache dedicated to store the context information when the core is transitioned to the power state that shuts off the voltage to the core but does not shut down the cache. Jahagirdar has taught restoring data saved to cache when power is reapplied to the core (in a runtime power state) (paragraphs [0056] and [0060]). This data includes state variables associated with a microcode path (paragraph [0060]), but is not explicitly taught as including the patch set of at least one micro-operation for the instruction. However, Branover has taught saving patch code in patch RAM when the core is in C6 state, and then restoring the patch code back into patch RAM when the core is powered again (see paragraphs [0015]-[0016]). One of ordinary skill in the art would have recognized that URAM 112 of Baumberger could be any form of memory, including known fast volatile memory for fast access to patches, and also that patch code in URAM 112 could similarly be stored to a dedicated portion of cache 26 and then restored so that the system has patches available in URAM, to speed up operation, as the core resumes operation (as opposed to re-fetching patches on demand). As a result it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baumberger such that the patch set of at least one micro-operation for the instruction is to be loaded, when the core is in a runtime power state, into the patch memory from the section of the cache dedicated to store the context information when the core is transitioned to the power state that shuts off the voltage to the core but does not shut down the cache.
Referring to claim 5, Baumberger, as modified, has taught the processor of claim 4, wherein the microcode sequencer circuit is to cause execution of code by the execution circuit to load, when the core is in a runtime power state, the patch set of at least one micro-operation from a system memory coupled to the processor into the section of the cache dedicated to store the context information when the core is transitioned to the power state that shuts off the voltage to the core but does not shut down the cache (see paragraphs [0029] and [0032]. There is a two-stage loading process. First the patch is loaded into main memory 16 by code 124. Then, after the patch from main memory 16 is decrypted and stored into cache, code 115 loads the decrypted patch from cache into patch memory (URAM). This occurs when the core is powered. Also, the code is stored in a dedicated portion, i.e., the portion dedicated to storing code at any given time).
Claims 14-15 and 24-25 are respectively rejected for reasons set forth in the rejections of claims 4-5 and 4-5 above.
Allowable Subject Matter
Claims 9, 19, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and assuming all contingent limitations are required by the claims.
Response to Arguments
Based on applicant’s arguments of the 112 rejection of claim 28 (p.10 of applicant’s response), the examiner has withdrawn the rejection.
On pages 12-13 of applicant’s response, applicant argues that the examiner hasn’t mapped the reference to the claimed microcode sequencer circuit and execution circuit and, thus, asserts that a prima facie case of anticipation has not been made.
The examiner respectfully disagrees. The claimed microcode sequencer circuit includes a patch memory. The examiner cited a patch memory, and, thus, at least part of the microcode sequencer circuit, in the prior art. Additionally, applicant claims that the sequencer circuit performs various functions, which the examiner also mapped the reference to. One of ordinary skill in the art understands that a processor contains circuitry to carry out functions. As such, the patch memory and whatever circuitry is performing the claimed functions would collectively form the sequencer circuit. For the execution unit, the examiner pointed to execution unit 24, which is the execution unit of the only processor 12 in the system. The execution will load patches by executing patch loader 115, which, for instance, is microcode in UROM. As such, the examiner has reasonably cited portions of Baumberger that correspond to the sequencer circuit and execution unit.
On page 13 of applicant’s response, applicant argues that claims 11 and 21 utilize different terms than claim 1 and, thus, cannot be rejected for similar reasoning as claim 1.
The differences are minimal. One of ordinary skill in the art understands that the processor of claim 1 would perform the method of claim 11 and thus claim 11 would be rejected for similar reasoning. Additionally, all functionality in a processor occurs in response to a medium storing code to be executed. Thus, claim 21 would be similarly rejected as claim 1.
On page 15 of applicant’s response, applicant notes that claim 6 appears to have been rejected using Official Notice for a feature not capable of instant and unquestionable demonstration as being well-known.
The examiner respectfully disagrees. The claim 6 rejection is a 102 rejection, not a 103 rejection based on Official Notice.
On page 16 of applicant’s response, applicant argues that the action does not offer explanation of cited paragraph [0027].
The examiner believes that the citation to paragraph [0027], given the context of Baumberger, would be sufficient to allow one of ordinary skill in the art to determine that claim 8 is not patentable. The claim sets forth that firmware can store a patch into the cache. The patch loader firmware can include microcode which would be executed by execution unit 24 to load authenticated and decrypted patches into URAM (paragraph [0029]). The authenticated and decrypted patches can also be stored in the cache (paragraph [0032]) so that they don’t need to be retrieved from main memory each time.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mahalingaiah, 6,141,740, has taught loading patch code from external memory into cache and then routing the patch code from cache to the microcode unit. The microcode unit is shown in FIG.3 as include patch memory 304 to store patch code.
Hebda, US 2005/0108508, has taught loading patches from patch cache 180 into patch memory 160.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183