DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In view of the appeal brief filed on 3/10/2025, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/EVA Y MONTALVO/ Supervisory Patent Examiner, Art Unit 2818
Claim Objections
Claims 19 and 23 is objected to because of the following informalities:
Claim 19 should be amended to correct an apparent typographic error:
19. The semiconductor package of claim 15, wherein a minimum spacing between adjacent ones of the pre-separated leads is less than or equal to a thickness of the leadframe.
Claim 23 should be amended to correct an apparent typographic error:
23. The packaged semiconductor device of claim 21, further including a die attach pad between the opposing plurality of leads, wherein an inactive side of the semiconductor die is attached to the die attach pad, with an inactive side of the semiconductor die facing away from the plurality of leads .
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 23 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 23 recites “an inactive side of the semiconductor die is attached to the die attach pad” and “an inactive side of the semiconductor die facing away from the plurality of leads the leads”. Therefore, claim 23 requires an inactive side of a semiconductor die attached to a die attach pad, and an inactive side also facing away from a plurality of leads. Fig. 2A provides for an embodiment where an inactive surface of die 120 is attached to die pad 251 and facing leads 181, and fig. 2B provides for an embodiment where an inactive surface of die 120 is faces away from leads 181. The application as originally filed does not provide support for an inactive side of a semiconductor die both attached to a die pad and facing away from leadframe leads.
For the purposes of compact prosecution, the Examiner has interpreted claim 23 to mean “…an inactive side of the semiconductor die is attached to the die attach pad, with an active side of the semiconductor die facing away from the plurality of leads the leads.”
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 4, 15, 19, 21, 23 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 4, 15, 21 and 29 recite “pre-separated leads on at least opposing sides”, which is an incomplete sentence or phrase. It is unclear what “sides” the leads or arranged or disposed on. For example, are they disposed on opposing sides of the leadframe (claim 1, claim 15), the leadframe sheet (claim 4, claim 29), the package (claim 1, claim 15), the packaged device (claim 21) or some other element?
For the purposes of compact prosecution, the Examiner has interpreted claims 1, 4, 15, 21 and 29 to mean “…pre-separated leads on at least opposing sides of a/the leadframe…”
Claim 3 recites “a minimum spacing between adjacent ones the pre-separated leads is less than or equal to a thickness of the leadframe”. As understood by the Examiner, the term ‘minimum spacing’ is an open range without an upper limit. Any spaced-apart leadframe leads would inherently have a non-zero thickness and therefore meet a minimum spacing of >0, and any leadframe would inherently have a thickness of >0. Accordingly, the metes and bounds of claim 3 are unclear, since any leads of any leadframe would meet the dimensions required by claim 3. See MPEP § 2173.05(c)(II).
Claim 19 recites limitations equivalent to claim 3, and is rejected under 35 USC § 112(b) for the same reasons.
For the purposes of compact prosecution, the Examiner has interpreted claims 3 and 19 to mean “…a
Claim 23 recites “wherein an inactive side of the semiconductor die is attached to the die attach pad, with an inactive side of the semiconductor die facing away from the plurality of leads the leads”. Since the term “an inactive side” is recited twice, it is unclear if the second recitation is referring to the same inactive (attached) side, or a second inactive side. This renders to scope of claim 23 indefinite. Based on the disclosed embodiments, the semiconductor die in each embodiment appears to have one active side and one inactive side, rather than two inactive sides.
For the purposes of compact prosecution, the Examiner has interpreted claim 23 to mean “…an inactive side of the semiconductor die is attached to the die attach pad, with an active side of the semiconductor die facing away from the plurality of leads the leads.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 21, 23 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibuya et al. (PG Pub. No. US 2019/0206768 A1).
Regarding claim 1, Shibuya teaches a leadframe (¶ 0054: 1802) for a semiconductor package (2300), comprising:
a plurality of pre-separated leads (¶ 0055: individual 1806) on at least opposing sides (fig. 18: 1806 disposed on opposing sides of 1802), and
metal plating (¶ 0055: 1826) on a distal end of the plurality of pre-separated leads including on an outer facing edge (fig. 18: 1826 disposed on distal end of 1806 including outer facing edge of end 1814).
Regarding claim 3, Shibuya teaches the leadframe of claim 1, wherein a minimum spacing between adjacent ones of the pre-separated leads is less than or equal to a thickness of the leadframe (figs. 3, 11, 18: minimum spacing between adjacent 110 or 1806 greater than 0, thickness of 104 and/or 1802 greater than 0).
Regarding claim 21, Shibuya teaches a packaged semiconductor device (¶ 0059 & fig. 23: 2300), comprising:
a plurality of leads (1¶ 0054: 1806) on at least opposing sides each having an outer facing edge (fig. 18: 1806 disposed on opposing sides);
a semiconductor die (¶ 0057: die 2200) electrically connected to at least some of the plurality of leads (fig. 23: 2200 electrically connected to 1806);
a molding material (¶ 0057: encapsulant 2204) covering the semiconductor die and at least some portion of the plurality of leads (fig. 23: 2204 covers 2200 and 1806); and
metal plating (¶ 0055: 1826) on a distal end of the plurality of leads including on the outer facing edge (fig. 23: 1826 disposed on distal end of 1806).
Regarding claim 23, Shibuya teaches the packaged semiconductor device of claim 21, further including a die attach pad (¶ 0054: 1804) between the opposing plurality of leads (fig. 23: 1804 disposed between opposing 1806), wherein an inactive side of the semiconductor die is attached to the die attach pad (fig. 23: inactive side of 2200 attached to 1804), with an [inactive] active side of the semiconductor die facing away from the plurality of leads the leads (fig. 23: active side of 2200 faces away from 1806. See 35 USC § 112 rejection(s) above for the Examiner’s interpretation of claim 23).
Regarding claim 27, Shibuya teaches the leadframe of Claim 1, wherein the metal plating covers the distal end of the plurality of pre-separated leads (fig. 18 among others: 1826 covers at least top, bottom, and side surfaces of distal ends of 1806).
Claim(s) 4, 6 and 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (PG Pub. No. US 2017/0358523 A1)
Regarding claim 4, Lee teaches a leadframe sheet (¶ 0022: 110), comprising:
a plurality of leadframe units (¶ 0023: 118 of columns 131/132/133) each including a plurality of pre-separated leads (¶ 0023: 122) and dam bars (¶ 0023: 124 and/or 126) on at least opposing sides (fig. 5), connected together in a 2-dimensional array so that adjacent ones of the plurality of leadframe units have the plurality of pre-separated leads interdigitated (¶0023 & fig. 5: leads 122 of adjacent leadframes in adjacent columns are interdigitated), wherein the plurality of pre-separated leads have an outer edge (Implicit: each 122 has at least one outer edge), and
wherein the dam bars that run an entire dimension of the leadframe sheet (fig. 5: 124 runs an entire vertical length of 110) for enabling mold injection (¶ 0024: 140) using mold plates to cover during a single injection an entire vertical row of the leadframe sheet (fig. 6: mold 140 formed to cover an entire vertical row of 110).
Examiner’s note: the terms “using mold plates” and “during a single injection” have not been given patentable weight, since they are process and/or temporal limitations which do not carry weight in a claim drawn to structure. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). In the instant case, the dam bar of Lee is patentably indistinct from a structure formed without mold plates, and with a plurality of injections.
Regarding claim 6, Lee teaches the leadframe sheet of claim 4, further comprising at least one dummy lead connection between the dam bars of adjacent ones of the plurality of leadframe units (fig. 5: at least one dummy lead, i.e. protruding portion of 122, disposed between 124 and 126 of adjacent leadframes 118).
Regarding claim 29, Lee teaches a plurality of leadframe units (¶ 0022: 118) each including a plurality of pre-separated leads (¶ 0023: 122) and dam bars (¶ 0023: 124 and/or 126) on at least opposing sides (fig. 5), connected together in a 2-dimensional array so that adjacent ones of the plurality of leadframe units have the plurality of pre-separated leads interdigitated (¶ 0023 & fig. 5: leads 122 of adjacent leadframes in adjacent columns are interdigitated), wherein the plurality of pre-separated leads have a gap between a distal end of each pre-separated lead and an adjacent leadframe unit (fig. 5: 122 has a gap between distal end of each 122 and adjacent 118).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 7, 22 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya as applied to claims 1 and 21 above, and further in view of Gong et al. (PG Pub. No. US 2011/0244629 A1).
Regarding claims 2 and 25, Shibuya teaches the leadframe of claim 1 and the packaged semiconductor device of claim 21, wherein the metal plating comprises tin or NiPdAu (¶ 0055).
Shibuya is silent to the metal plating having a thickness in a range of 3 um to 20 um.
Gong teaches a leadframe (¶ 0017) including a metal plating (¶ 0023: tin, NiPdAu or similar) having a thickness in a range of 2 um to 15 um (¶ 0030).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the metal plating of Shibuya with the thickness of Gong, as a means to provide a wettable layer (Gong, ¶ 0030), increasing the overall solder joint strength and reliability (Gong, ¶ 0031).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed metal plating thickness range of 3 um to 20 um overlaps the range disclosed by Gong.
Regarding claim 22, Shibuya teaches the packaged semiconductor device of claim 21, wherein the semiconductor die is connected to the leads (fig. 23: 2200 connected to 1806).
Shibuya does not teach the semiconductor die is mounted in a flip chip configuration with an active side of the semiconductor die facing toward the leads.
Gong teaches a semiconductor package including a flip-chip disposed on a leadframe (¶ 0028: die mounted on leadframe in a flip-chip process).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Khoo in view of Shibuya as a flip chip package, as a means to connect the bond pads of the integrated circuit die to the internal electrical leads in the lead frame (Gong, ¶ 0028).
Furthermore, the Examiner notes that the features of claim 22 (“the semiconductor die is mounted to the leads in a flip chip configuration”) appears to be mutually exclusive to features of claim 23 (“an inactive side of the semiconductor die is attached to the die attach pad”). The instant application provides support for a semiconductor die mounted to the leads in a flip chip configuration in the embodiment of fig. 2B, and an inactive side of the semiconductor die is attached to the die attach pad in the embodiment of fig. 2A. Based on the application as originally filed, these features appear to be mutually exclusive. Should applicant traverse on the grounds that the flip chip configuration of Gong is patentably distinct from the wirebond configuration of Shibuya, Applicant should submit evidence or identify such evidence now of record showing these to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 4 above, and further in view of Shibuya.
Regarding claim 5, Lee teaches the leadframe sheet of claim 4, comprising distal ends of a plurality of pre-separated leads (fig. 5: individual leads 122 include distal ends).
Lee does not teach the leadframe further comprising metal plating on the distal ends of the plurality of pre-separated leads.
Shibuya teaches a leadframe (¶ 0054: 1802) including a metal plating (¶ 0055: 1826) on a distal end of a plurality of pre-separated leads (fig. 18: 1826 disposed on distal ends of each 1806).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the leads of Lee with the metal plating of Shibuya, as a means to increase the wettability of the exterior surface for soldering (Shibuya, ¶ 0055).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Shibuya as applied to claim 5 above, and further in view of Gong.
Regarding claim 7, Lee in view of Shibuya teaches the leadframe sheet of claim 5, wherein the metal plating comprises tin or NiPdAu (Shibuya, ¶ 0055).
Lee in view of Shibuya is silent to the metal plating having a thickness in a range of 3 um to 20 um.
Gong teaches a leadframe (¶ 0017) including a metal plating (¶ 0023: tin, NiPdAu or similar) having a thickness in a range of 2 um to 15 um (¶ 0030).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the metal plating of Lee in view of Shibuya with the thickness of Gong, as a means to provide a wettable layer (Gong, ¶ 0030), increasing the overall solder joint strength and reliability (Gong, ¶ 0031).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed metal plating thickness range of 3 um to 20 um overlaps the range disclosed by Gong.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 4 above, and further in view of Yee et al. (PG Pub. no. US 2007/0281392 A1).
Regarding claim 8, Lee teaches the leadframe sheet of claim 4, comprising a spacing between the pre-separated leads and the dam bars (fig. 5: spacing between 122 and 124 or 126).
Lee does not teach wherein a spacing between the pre-separated leads and the dam bars is 0.10 mm to 0.18 mm.
Yee teaches a leadframe strip (¶ 0043: 300) including leadframes (¶ 0042: 310) comprising leads (508) and dam bars (¶ 0044: connecting bars 506/508), wherein a spacing between the pre-separated leads is 0.5um (¶ 0048).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the spacing between the pre-separated leads and the dam bars of Lee, as a means to more easily remove the dam bars, and/or increase the package density by allowing tight pitch between leadframe units.
Furthermore, adjusting the spacing to arrive at the claimed range of “0.10 mm to 0.18 mm” would be a matter of routine skill, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, the general conditions of a leadframe with dam bars, leads, and sub-mm spacing is taught by Yee.
Claim(s) 15, 17, 19 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khoo et al. (PG Pub. No. US 2016/0005663 A1) in view of in view of Shibuya.
Regarding claim 15, Khoo teaches a semiconductor package, comprising:
a leadframe (¶ 0018: 102), comprising:
a plurality of pre-separated leads (¶ 0018: individual leads 108) on at least opposing sides (fig. 6: 108 disposed on opposing sides of 102), and
a semiconductor die (¶ 0018: 105) having bond pads (¶ 0020: terminals of 105) mounted on the leadframe (¶ 0021 & fig. 1: 105 mounted on 102) having the bond pads electrically connected to the plurality of pre-separated leads (¶ 0023: terminals of 105 electrically connected to a subset of 108).
Khoo does not teach metal plating on a distal end of the plurality of pre-separated leads including on an outer facing edge.
Shibuya teaches a semiconductor package (2300), comprising metal plating (¶ 0055: 1826) on a distal end of a plurality of pre-separated leads including on an outer facing edge (fig. 18: 1826 disposed on distal end of 1806 including outer facing edge of end 1814).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the leads of Lee with the metal plating of Shibuya, as a means to increase the wettability of the exterior surface for soldering (Shibuya, ¶ 0055).
Regarding claim 17, Khoo in view oof Shibuya teaches the semiconductor package of claim 15, wherein the semiconductor die comprises an integrated circuit (IC) (Khoo, ¶ 0023: 105 comprises MOSFET, JFET, or IGBT, which are types of integrated circuit devices).
Regarding claim 19, Khoo in view oof Shibuya teaches the semiconductor package of claim 15, wherein a minimum spacing between adjacent ones the pre-separated leads is less than or equal to a thickness of the leadframe (Shibuya, figs. 3, 11, 18: minimum spacing between adjacent 110 or 1806 greater than 0, thickness of 104 and/or 1802 greater than 0).
Regarding claim 28, Khoo in view oof Shibuya teaches the semiconductor package of Claim 15, wherein the metal plating covers the distal end of the plurality of pre-separated leads (Shibuya, fig. 23 among others: 1826 covers at least top, bottom, and side surfaces of distal ends of 1806).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khoo in view of Shibyua as applied to claim 15 above, and further in view of Koduri (PG Pub. No. US 2020/0058576 A1).
Regarding claim 20, Khoo in view oof Shibuya teaches the semiconductor package of claim 15, comprising a plurality of leads (Khoo, 108). Shibuya further teaches leads with a stepped profile (¶ 0045).
Khoo in view oof Shibuya as applied to claim 15 above does not teach wherein the plurality of leads comprise gull-wing leads.
Koduri teaches a semiconductor package (100B) including leads (¶ 0020: 118) formed in a gull-wing configuration (¶ 0017) analogous to the stepped profile of Shibuya.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Khoo in view of Shibuya with gull-wing leads, as a means to provide stress-absorbing (e.g., spring-like) structures when mounted on a substrate (e.g., system board) (Koduri, ¶ 0012).
Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khoo in view of Shibuya as applied to claim 15 above, and further in view of Gong.
Regarding claim 16, Khoo in view oof Shibuya teaches the semiconductor package of claim 15, comprising a semiconductor package (Khoo, ¶ 0036).
Khoo in view of Shibuya is silent to wherein the semiconductor package comprises a flipchip package.
Gong teaches a semiconductor package including a flipchip disposed on a leadframe (¶ 0028: die mounted on leadframe in a flip-chip process).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Khoo in view of Shibuya as a flip chip package, as a means to connect the bond pads of the integrated circuit die to the internal electrical leads in the lead frame (Gong, ¶ 0028).
Regarding claim 18, Khoo in view oof Shibuya teaches the semiconductor package of claim 15, wherein the metal plating comprises tin or NiPdAu (Shibuya, ¶ 0055: 1826 comprises material such as include nickel, palladium, tin, and gold)
Khoo in view oof Shibuya does not teach the metal plating having a thickness in a range of 3 um to 20 um.
Gong teaches a leadframe (¶ 0017) including a metal plating (¶ 0023: tin, NiPdAu or similar) having a thickness in a range of 2 um to 15 um (¶ 0030).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the metal plating of Khoo in view of Shibuya with the thickness of Gong, as a means to provide a wettable layer (Gong, ¶ 0030), increasing the overall solder joint strength and reliability (Gong, ¶ 0031).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed metal plating thickness range of 3 um to 20 um overlaps the range disclosed by Gong.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya as applied to claim 21 above, and further in view of Truhitte et al. (PG Pub. No. US 2019/0122967 A1).
Regarding claim 24, Shibuya teaches the packaged semiconductor device of claim 21, comprising a semiconductor die (2200) and leads (1806).
Shibuya does not explicitly teach wherein an opposing inactive side of the semiconductor die faces away from the leads.
Truhitte teaches a semiconductor package including a semiconductor die (¶ 0004: 124) mounted on a leadframe (¶ 126) in a flip-chip configuration (¶ 0028: in a non-illustrated embodiment, die 124 mounted on leadframe contacts 204 in a flip-chip configuration), such that opposing inactive side of the semiconductor die faces away from the leads (implicit: flip-chip includes terminals of a die directly bonded to leads of a leadframe, such that an inactive side of the die faces away from the leads).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Khoo in view of Shibuya as a flip chip package, as a means to connect the bond pads of the integrated circuit die to the internal electrical leads in the lead frame without needing a die paddle and a die pad (Truhitte, ¶ 0028).
Furthermore, the Examiner notes that the features of claim 24 (“an opposing inactive side of the semiconductor die faces away from the leads”) appears to be mutually exclusive to features of claim 23 (“an inactive side of the semiconductor die is attached to the die attach pad”). The instant application provides support for an inactive side of a semiconductor die facing away from leads in the embodiment of fig. 2B, and provides support for an inactive side of the semiconductor die is attached to a die attach pad in the embodiment of fig. 2A. Based on the application as originally filed, these features appear to be mutually exclusive to each embodiment. Should applicant traverse on the grounds that the flip chip configuration of Gong is patentably distinct from the wirebond configuration of Shibuya, Applicant should submit evidence or identify such evidence now of record showing these to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya as applied to claim 21 above, and further in view of Koduri.
Regarding claim 26, Shibuya teaches the semiconductor package of claim 15, comprising leads (1806), and further teaches leads with a stepped profile (¶ 0045).
Shibuya does not teach wherein the plurality of leads comprise gull-wing leads.
Koduri teaches a semiconductor package (100B) including leads (¶ 0020: 118) formed in a gull-wing configuration (¶ 0017).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Shibuya with gull-wing leads, as a means to provide stress-absorbing (e.g., spring-like) structures when mounted on a substrate (e.g., system board) (Koduri, ¶ 0012).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 and 15-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818