DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 9, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 20, the limitations “a fifth (sixth) gap” are unclear because a third and fourth gap have not been recited.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2022/0343823; herein “Wang”) in view of Kwon et al. (US 20140159037; herein “Kwon”).
Regarding claims 1 and 20, Wang discloses in Figs. 2, 12, 13 and related text a display device, comprising a display panel (see abstract at least); wherein the display panel comprises:
a base substrate (1000);
a first transistor (e.g. M3) and a second transistor (M2), wherein the first transistor and the second transistor are formed on the base substrate, wherein the first transistor comprises a first active layer (600, including M3-A) containing silicon (see [0201]), a first gate (M3-G), a first source (first or second region, see [0201]), and a first drain (second or first region, see [0201]);
the second transistor comprises a second active layer (700, including M2-A) containing an oxide semiconductor (see [0216]), a second gate (G2), a second source (third or fourth region, see [0221]), and a second drain (fourth or third region, see [0221]), and the second active layer is located on a side of the first active layer facing away from the base substrate (see Figs. 12-13); and
wherein the second active layer comprises a channel region (e.g. region of M2-A under G2, see [0221]; see also Figs. 11D-E) and a non-channel region (e.g. region outside of channel region, see [0221]), the second gate (G2) and the channel region of the second active layer are overlapped with each other (see Fig. 13).
Wang does not explicitly disclose
a conductive layer, wherein the conductive layer comprises a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are located on the second active layer, the second source is electrically connected to the first conductive layer, and the second drain is electrically connected to the second conductive layer;
the first conductive layer and the second conductive layer are disposed on the non-channel region of the second active layer,
wherein in a direction from the first conductive layer to the second conductive layer, a first gap is provided between the first conductive layer and the second gate, a second gap is provided between the second conductive layer and the second gate, a width of the first gap is W1, and a width of the second gap is W2, W1> 0, and W2 > 0; and
wherein in the direction from the first conductive layer to the second conductive layer, a fifth gap is provided between the second source and the second drain, a sixth gap is provided between the first conductive layer and the second conductive layer, a width of the fifth gap is W5, a width of the sixth gap is W6, W5> 0, W6> 0, and W5 <W6.
In the same field of endeavor, Kwon teaches in Fig. 1B and related text a display panel comprising
a conductive layer (130, see [0056]), wherein the conductive layer comprises a first conductive layer (131) and a second conductive layer (132), wherein the first conductive layer and the second conductive layer are located on the second active layer (120, see [0050]), the second source (121, see [0053]) is electrically connected to the first conductive layer, and the second drain (122, see [0053]) is electrically connected to the second conductive layer;
the first conductive layer and the second conductive layer are disposed on the non-channel region of the second active layer (see [0053]),
wherein in a direction from the first conductive layer to the second conductive layer, a first gap is provided between the first conductive layer and the second gate, a second gap is provided between the second conductive layer and the second gate, a width of the first gap is W1, and a width of the second gap is W2, W1> 0, and W2 > 0 (d1 and d2, see [0074]); and
wherein in the direction from the first conductive layer to the second conductive layer, a fifth gap (e.g. gap represented by 123, between 121 and 122) is provided between the second source and the second drain, a sixth gap is provided between the first conductive layer and the second conductive layer (e.g. gap represented by 123+d1+d2), a width of the fifth gap is W5, a width of the sixth gap is W6, W5> 0, W6> 0, and W5 <W6 (see Fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang by having a first conductive layer and a second conductive layer located on the second active layer, the second source electrically connected to the first conductive layer and the second drain electrically connected to the second conductive layer; the first conductive layer and the second conductive layer disposed on the non-channel region of the second active layer, a first gap is provided between the first conductive layer and the second gate, a second gap is provided between the second conductive layer and the second gate, a width of the first gap is W1, and a width of the second gap is W2, W1> 0, and W2 > 0; and in the direction from the first conductive layer to the second conductive layer, a fifth gap is provided between the second source and the second drain, a sixth gap is provided between the first conductive layer and the second conductive layer, a width of the fifth gap is W5, a width of the sixth gap is W6, W5> 0, W6> 0, and W5 <W6, as taught by Kwon, in order to reduce contact resistance and parasitic capacitance and apply the transistor structure to a high resolution display (see Kwon [0075] and [0143]).
Regarding claim 2, Wang further discloses
wherein the display panel comprises a pixel circuit (see Fig. 2 and [0110]), the pixel circuit comprises a drive transistor (M0), and the second drain of the second transistor (fourth or third region of M2) is connected to a gate of the drive transistor (see Fig. 2), and
wherein the second source (third or fourth region of M2) is connected to a reset signal terminal and configured to provide a resent signal for the gate of the drive transistor, or the second source is connected to a drain of the drive transistor (see Fig. 2) and configured to compensate a threshold voltage of the drive transistor (see [0102]).
Regarding claim 19, Wang further discloses wherein the first source and the first drain are located on a same layer (first and second regions of M3-A on layer 1000), and the second source, the second drain and the second gate are located on a same layer (third and fourth regions of M2-A on layer 870), and wherein the second gate (G2) is located on a side of the second active layer (M2-A) facing away from the base substrate (1000).
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Kwon, as applied to claim 2 above, or in the alternative, further in view of Kubota et al. (US 6,255,695; herein “Kubota”).
Regarding claim 3, Wang further discloses wherein a rate of the second source transmitting a current to the channel region is greater than a rate of the second drain transmitting a current to the channel region; or, a path length of the second source transmitting a current to the channel region is less than a path length of the second drain transmitting a current to the channel region (path length from GK3 is greater than path length from GK5, see Fig. 13; note that third and fourth regions can each be source or drain, see [0116]).
In the alternative, in the same field of endeavor, Kubota teaches a display device (see col. 1 lines 24-26) wherein a rate of the second source transmitting a current to the channel region is greater than a rate of the second drain transmitting a current to the channel region; or, a path length of the second source transmitting a current to the channel region is less than a path length of the second drain transmitting a current to the channel region (D2>D1, see col. 7 lines 20-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device by having a path length of the second source transmitting a current to the channel region is less than a path length of the second drain transmitting a current to the channel region, as shown by Kubota, in order to reduce power consumption (see Kubota col. 5 lines 59-67).
Regarding claim 4, Wang further discloses wherein W2 > W1 (see Fig. 13).
In the alternative, in the same field of endeavor, Kubota teaches a display device Kubota teaches a display device (see col. 1 lines 24-26) wherein W2 > W1 (D2>D1, see col. 7 lines 20-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device by having W2 > W1, as shown by Kubota, in order to reduce power consumption (see Kubota col. 5 lines 59-67).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Kwon, as applied to claim 4 above, and further in view of Kubota.
Regarding claim 5, Wang does not explicitly disclose wherein (W2 - W1)≤ 1 µm.
In the same field of endeavor, Kubota teaches a display device (see col. 1 lines 24-26) wherein (W2 - W1)≤ 1 µm (D1 is about 1-5 µm, D2 is double, thus the range of (W2 - W1) is 1-5µm, which overlaps the claimed range, see col. 7 lines 23-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device by having (W2 - W1)≤ 1 µm, as shown by Kubota, in order to reduce power consumption (see Kubota col. 5 lines 59-67).
Note that the range disclosed by Kubota overlaps the claimed range. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the difference in gap widths to be a result effective variable affecting power consumption. Thus, it would have been obvious to modify the device of Wang to have the difference in widths within the claimed range in order to achieve the desired degree of power consumption balanced with the desired device size, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Kwon, as applied to claim 2 above, and in view of Li et al. (US 2017/0162703; herein “Li”).
Regarding claim 9, Wang in view of Kwon does not explicitly disclose wherein a resistivity of the first conductive layer is less than a resistivity of the second conductive layer.
In the same field of endeavor, Li teaches in Fig. 1 and related text a resistivity of the first conductive layer is less than a resistivity of the second conductive layer (when the first conductive layer is interpreted as the lower conductivity layer of 6 and 8 and the second conductive layer is interpreted as the higher resistivity layer of 6 and 8, see [0043] and [0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang by having a resistivity of the first conductive layer is less than a resistivity of the second conductive layer, as taught by Li, in order to achieve a good ohmic contact (see Li [0069]).
Response to Arguments
Applicant's arguments filed 5/20/2026 have been fully considered but are moot in view of the new grounds of rejection presented above. In particular, it is noted that the references have been newly interpreted such that the claimed invention is taught by the references as outlined in the rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/ Primary Examiner, Art Unit 2896
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