Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21 and 22 recites the limitation "the rectangular multi-height logic cell". There is insufficient antecedent basis for this limitation in the claim. For purpose of examination, the Examiner interprets the limitation as a rectangular multi-height logic cell.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 6, 8, 9, 11-13 and 15-19 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (U.S. Patent Pub. No. 2011/0049575) of record, in view of Gheewala (U.S. Patent No. 6,838,713) of record.
Regarding Claim 1
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height (height of SHSC) and a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure comprising at least two transistors and interconnections (FIG. 2), and for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a multi-height logic cell (WHSC1) arranged over the semiconductor substrate, wherein the multi-height logic cell has a second height that is greater than the first height and a second height that is greater than the first height and a second width, and wherein (FIG. 15) the multi-height logic cell includes: a first semiconductor structure (right) located entirely between the first and second centerlines and configured to implement a first logic function [0052]; and a second semiconductor structure (left) extending between the second and third centerlines over the first centerline and configured to implement a second logic function (CMOS logic).
Tanaka is silent with respect to “a second logic function separate from the first logic function”.
FIG. 3 of Gheewala discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (210) located entirely between the first (340) and second (350) centerlines and configured to implement a first logic function; and a second semiconductor structure (320) extending between the second and third (360) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Gheewala. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to achieve high density and improved power distribution (Col. 1, Lines 6-9 of Gheewala).
Regarding Claim 2
FIG. 1 of Tanaka discloses the second height is an integer multiple of the first height.
Regarding Claim 3
FIG. 1 of Tanaka discloses the second height is twice the first height.
Regarding Claim 5
FIG. 1 of Tanaka discloses the second width equals the unit width.
Regarding Claim 6
FIG. 1 of Tanaka discloses the second width is different from the first width.
Regarding Claim 8
FIG. 4 of Tanaka discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Tanaka discloses the first semiconductor circuit structure is configured to implement have a first maximum drive strength current; and the second semiconductor circuit structure is configured to implement have a different second maximum drive strength current greater than the first maximum drive current.
Regarding Claim 9
In general, timing delays through circuitry are caused by propagation delays through and between logic cells which comprise the circuitry. The actual amount of propagation delay through and between logic cells is generally dependent on various capacitances within and between the logic cells, as well as the current available to charge or discharge the capacitances (Col. 1, Lines 16-22 of U.S. Patent No. 5,903,468 to Misheloff provides documentary evidence). Therefore, Tanaka discloses the second logic function is configured to have a lower propagation delay than the third logic function.
Regarding Claim 11
FIG. 1 of Tanaka discloses the semiconductor structure implements at least one of an inverter, a NAND gate, and a NOR gate [0041].
Regarding Claim 12
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance, the first centerline between the second and third centerlines; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells having a first height (height of SHSC) and a first width that is an integer multiple of a unit width and including corresponding logic gate components [0053], and for each single-height logic cell in the first row, the corresponding logic gate components are located entirely between the first and second centerlines (FIG. 2), and for each single-height logic cell in the second row, the corresponding logic gate components are located entirely between the first and third centerlines; and a multi-height logic cell (WHSC1) arranged over the semiconductor substrate and including: a second height (height of WHSC1) that is an integer multiple of the first height, the integer being two or greater, and a first semiconductor structure located between the first and second centerlines and configured to implement a first logic function, and a second semiconductor structure located between the second and third centerlines and over the first centerline and configured to implement a second logic function (FIG. 15).
Tanaka is silent with respect to “a second logic function separate from the first logic function”.
FIG. 3 of Gheewala discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (210) located entirely between the first (340) and second (350) centerlines and configured to implement a first logic function; and a second semiconductor structure (320) extending between the second and third (360) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Gheewala. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to achieve high density and improved power distribution (Col. 1, Lines 6-9 of Gheewala).
Regarding Claim 13
FIG. 4 of Tanaka discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Tanaka discloses the first semiconductor structure is configured to provide a first maximum drive current than is less than a second maximum drive current of the second semiconductor structure.
Regarding Claim 15
Tanaka discloses the first and second semiconductor structures are configured to implement at least one of an inverter, a NAND gate, and a NOR gate [0041].
Regarding Claim 16
FIG. 1 of Tanaka discloses a method of forming an integrated circuit (IC), comprising: forming first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance, the first centerline between the second and third centerlines; forming a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height and a first width that is an integer multiple of a unit width, a first semiconductor structure (FIG. 2) comprising at least one transistor and interconnections, the corresponding semiconductor structure, for each single-height logic cell in the first row, the first semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and forming a multi-height logic cell (WHSC1) over the semiconductor substrate and having a second height (height of WHSC1) that is greater than the first height, a second width that is at least the unit width (FIG. 11), the multi-height logic cell including a first semiconductor structure configured to implement a first logic function and a second semiconductor structure configured to implement a second logic function, the first semiconductor structure located entirely between the first and second centerlines, and the second semiconductor structure extending between the second and third centerlines and over the first centerline (FIG. 15).
Tanaka is silent with respect to “a second semiconductor structure configured to implement a second logic function separate from the first logic function”.
FIG. 3 of Gheewala discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (210) located entirely between the first (340) and second (350) centerlines and configured to implement a first logic function; and a second semiconductor structure (320) extending between the second and third (360) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Gheewala. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to achieve high density and improved power distribution (Col. 1, Lines 6-9 of Gheewala).
Regarding Claim 17
FIG. 4 of Tanaka discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Tanaka discloses the first semiconductor structure is configured to provide a first maximum drive current than is less than a second maximum drive current of the second semiconductor structure.
Regarding Claim 18
FIG. 1 of Tanaka discloses forming the multi-height logic cell to have the second height that is greater than the first height comprises forming the multi-height logic cell to have a second height that is an integer multiple of the single-height logic cells, in which the multiple is at least 2.
Regarding Claim 19
FIG. 3 of Gheewala discloses a second logic function is different from the first logic function.
Claims 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, in view of Won (CN 105448764, machine-translation provided)
Regarding Claim 21
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; the first centerline between the second and third centerlines; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure extending between the first semiconductor structure and the third centerline over the first centerline.
Tanaka is silent with respect to “a second logic function separate from the first logic function”.
FIG. 9 of Won discloses a similar integrated circuit, comprising a first semiconductor structure (310) located entirely between the first and second centerlines and configured to implement a first logic function (standard logic cell); and a second semiconductor structure (330) extending between the first semiconductor structure and the third centerline over the first centerline and configured to implement a second logic function separate from the first logic function (common standard cell).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Won. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to drive various application programs ([0003] of Won).
Regarding Claim 22
FIG. 1 of Tanaka discloses the rectangular multi-height logic cell (WHSC1) has the second width over the first centerline and over the third centerline.
Regarding Claim 23
FIG. 1 of Tanaka discloses the rectangular multi-height logic cell (WHSC1) has a long axis extending between the first and third centerlines, and the first and second semiconductor structures are both centered with respect to the long axis.
Claims 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. Patent Pub. No. 2009/0212327), in view of Fabrice (EP 1104938, machine-translation provided)
Regarding Claim 21
FIG. 3 of Kim discloses an integrated circuit (IC), comprising: first (30), second (10) and third (20) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity (GND) and the second and third power rails configured to have a different second polarity (VDD) [0042], and the first, second and third power rails located along corresponding first, second and third centerlines spaced apart by a same distance [0037], the first centerline between the second and third centerlines; a plurality of single-height logic cells (430-460) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a first semiconductor structure (430) located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure (450) extending between the first semiconductor structure and the third centerline over the first centerline and configured to implement a second logic function separate from the first logic function.
Kim is silent with respect to “a second logic function separate from the first logic function”.
FIG. 1 of Fabrice discloses a similar integrated circuit, comprising a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function (NOR); and a second semiconductor structure extending between the first semiconductor structure and the third centerline over the first centerline and configured to implement a second logic function separate from the first logic function (NAND).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Fabrice. The ordinary artisan would have been motivated to modify Kim in the above manner in order to perform certain operations ([0003] of Fabrice).
Regarding Claim 22
FIG. 3 of Kim discloses the rectangular multi-height logic cell (420) has the second width over the first centerline and over the third centerline.
Regarding Claim 23
FIG. 3 of Kim discloses the rectangular multi-height logic cell (420) has a long axis extending between the first and third centerlines, and the first and second semiconductor structures are both centered with respect to the long axis.
Pertinent Art
US 20070290270 discloses a first semiconductor circuit located entirely between the first and second power rails; and a second semiconductor circuit that extends over the first power rail, the first and second semiconductor circuits not sharing any signal path through the semiconductor substrate. US 20130313615 also discloses a first semiconductor circuit located entirely between the first and second power rails; and a second semiconductor circuit that extends over the first power rail, the first and second semiconductor circuits not sharing any signal path through the semiconductor substrate. US 20070141766 discloses a first semiconductor circuit located between the first and second centerlines, and a second semiconductor circuit located between the first and third centerlines, the first and second semiconductor circuits not sharing any signal path through the semiconductor substrate. Pertinent art also includes 5903468.
Response to Arguments
Applicant’s arguments with respect to Claims 1, 12 and 16 have been considered but they are not persuasive. FIG. 15 of Tanaka discloses an embodiment different from FIG. 12 [0033, 0036]. In particular, it is not limited to a three-inverter clock buffer. FIG. 3 of Gheewala is used to modify Tanaka such that the second logic function is separate from the first logic function. The proposed modification would not render the device of Tanaka inoperable or unsuited for its intended purpose (see MPEP 2143.01), because FIG. 15 of Tanaka does NOT preclude the second logic function may be separate from the first logic function. In fact, the first semiconductor structure is separated from the second semiconductor structure.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897