Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/22/2026 has been entered.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21 and 22 recite the limitation "the rectangular multi-height logic cell". There is insufficient antecedent basis for this limitation in the claim. For purpose of examination, the Examiner interprets the limitation as a rectangular multi-height logic cell.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 8, 9, 12, 13, 16-19 and 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Gheewala (U.S. Patent No. 6,838,713) of record, in view of Hickman (U.S. Patent No. 5,452,245).
Regarding Claim 1
FIG. 3 of Gheewala discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; a plurality of single-height logic cells (210) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a multi-height logic cell (320) arranged over the semiconductor substrate, wherein the multi-height logic cell has a second height that is greater than the first height and a second width, and wherein the multi-height logic cell includes a second semiconductor structure extending between the second and third centerlines over the first centerline and configured to implement a second logic function.
Gheewala is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function” and “a second logic function separate from the first logic function”.
FIG. 1 of Hickman discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (14) located entirely between the first (102) and second (100) centerlines and configured to implement a first logic function; and a second semiconductor structure (52) extending between the second and third (101) centerlines over the first centerline (FIG. 2) and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Gheewala, as taught by Hickman. The ordinary artisan would have been motivated to modify Gheewala in the above manner in order to improve gate array architecture having a core cell which is both memory and logic efficient (Col. 1, Lines 26-29 of Hickman).
The claim “configured to implement a first logic function” and “configured to implement a second logic function” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Gheewala teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 2
FIG. 3 of Gheewala discloses the second height is an integer multiple of the first height.
Regarding Claim 3
FIG. 3 of Gheewala discloses the second height is twice the first height.
Regarding Claim 5
FIG. 3 of Gheewala discloses the second width equals the unit width.
Regarding Claim 8
FIG. 3 of Gheewala discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Gheewala discloses the first semiconductor circuit structure is configured to implement have a first maximum drive strength current; and the second semiconductor circuit structure is configured to implement have a different second maximum drive strength current greater than the first maximum drive current.
Regarding Claim 9
In general, timing delays through circuitry are caused by propagation delays through and between logic cells which comprise the circuitry. The actual amount of propagation delay through and between logic cells is generally dependent on various capacitances within and between the logic cells, as well as the current available to charge or discharge the capacitances (Col. 1, Lines 16-22 of U.S. Patent No. 5,903,468 to Misheloff provides documentary evidence). Therefore, Gheewala discloses the second logic function is configured to have a lower propagation delay than the third logic function.
Regarding Claim 12
FIG. 3 of Gheewala discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance, the first centerline between the second and third centerlines; a plurality of single-height logic cells (210) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells having a first height and a first width that is an integer multiple of a unit width and including corresponding logic gate components, and for each single-height logic cell in the first row, the corresponding logic gate components are located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding logic gate components are located entirely between the first and third centerlines; and a multi-height logic cell (320) arranged over the semiconductor substrate and including: a second height that is an integer multiple of the first height, the integer being two or greater, and a second semiconductor structure located between the second and third centerlines and over the first centerline and configured to implement a second logic function.
Gheewala is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function” and “a second logic function separate from the first logic function”.
FIG. 1 of Hickman discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (14) located entirely between the first (102) and second (100) centerlines and configured to implement a first logic function; and a second semiconductor structure (52) extending between the second and third (101) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Gheewala, as taught by Hickman. The ordinary artisan would have been motivated to modify Gheewala in the above manner in order to improve gate array architecture having a core cell which is both memory and logic efficient (Col. 1, Lines 26-29 of Hickman).
The claim “configured to implement a first logic function” and “configured to implement a second logic function” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Gheewala teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 13
FIG. 3 of Gheewala discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Tanaka discloses the first semiconductor structure is configured to provide a first maximum drive current than is less than a second maximum drive current of the second semiconductor structure.
Regarding Claim 16
FIG. 3 of Gheewala discloses a method of forming an integrated circuit (IC), comprising: forming first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance, the first centerline between the second and third centerlines; forming a plurality of single-height logic cells (210) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height and a first width that is an integer multiple of a unit width, a first semiconductor structure comprising at least one transistor and interconnections, the corresponding semiconductor structure, for each single-height logic cell in the first row, the first semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and forming a multi-height logic cell (320) over the semiconductor substrate and having a second height that is greater than the first height, a second width that is at least the unit width, the multi-height logic cell including a second semiconductor structure configured to implement a second logic function, the second semiconductor structure extending between the second and third centerlines and over the first centerline (FIG. 2) and configured to implement a second logic function.
Gheewala is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function” and “a second logic function separate from the first logic function”.
FIG. 1 of Hickman discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (14) located entirely between the first (102) and second (100) centerlines and configured to implement a first logic function; and a second semiconductor structure (52) extending between the second and third (101) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Gheewala, as taught by Hickman. The ordinary artisan would have been motivated to modify Gheewala in the above manner in order to improve gate array architecture having a core cell which is both memory and logic efficient (Col. 1, Lines 26-29 of Hickman).
The claim “configured to implement a first logic function” and “configured to implement a second logic function” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Gheewala teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 17
FIG. 3 of Gheewala discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Gheewala discloses the first semiconductor structure is configured to provide a first maximum drive current than is less than a second maximum drive current of the second semiconductor structure.
Regarding Claim 18
FIG. 3 of Gheewala discloses forming the multi-height logic cell to have the second height that is greater than the first height comprises forming the multi-height logic cell to have a second height that is an integer multiple of the single-height logic cells, in which the multiple is at least 2.
Regarding Claim 19
FIG. 1 of Hickman discloses a second logic function is different from the first logic function.
Regarding Claim 21
FIG. 3 of Gheewala discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; the first centerline between the second and third centerlines; a plurality of single-height logic cells (210) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a rectangular multi-height logic cell (320) comprising: a second semiconductor structure extending between the first semiconductor structure and the third centerline over the first centerline (FIG. 2) and configured to implement a second logic function.
Gheewala is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function” and “a second logic function separate from the first logic function”.
FIG. 1 of Hickman discloses a similar integrated circuit, wherein the multi-height logic cell includes: a first semiconductor structure (14) located entirely between the first (102) and second (100) centerlines and configured to implement a first logic function; and a second semiconductor structure (52) extending between the second and third (101) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Gheewala, as taught by Hickman. The ordinary artisan would have been motivated to modify Gheewala in the above manner in order to improve gate array architecture having a core cell which is both memory and logic efficient (Col. 1, Lines 26-29 of Hickman).
The claim “configured to implement a first logic function” and “configured to implement a second logic function” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Gheewala teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 22
FIG. 3 of Gheewala discloses the rectangular multi-height logic cell (320) has the second width over the first centerline and over the third centerline.
Regarding Claim 23
FIG. 3 of Gheewala discloses the rectangular multi-height logic cell (320) has a long axis extending between the first and third centerlines, and the first and second semiconductor structures are both centered with respect to the long axis.
Claims 1, 6, 11, 15-19 and 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (U.S. Patent Pub. No. 2011/0049575) of record, in view of Park (U.S. Patent Pub. No. 2021/0384295).
Regarding Claim 1
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height (height of SHSC) and a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure comprising at least two transistors and interconnections (FIG. 2), and for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a multi-height logic cell (WHSC1) arranged over the semiconductor substrate, wherein the multi-height logic cell has a second height that is greater than the first height and a second height that is greater than the first height and a second width.
Tanaka is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure extending between the second and third centerlines over the first centerline and configured to implement a second logic function a second logic function separate from the first logic function”.
FIG. 2 of Park discloses a similar integrated circuit, wherein the multi-height logic cell (DHC) includes: a first semiconductor structure (NR2) located entirely between the first (VDD) and second (VSS) centerlines and configured to implement a first logic function; and a second semiconductor structure (PR1/2) extending between the second and third (CSS) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function [0007].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Park. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to improving reliability and performance ([0003] of Park).
Regarding Claim 6
FIG. 1 of Tanaka discloses the second width is different from the first width.
Regarding Claim 11
FIG. 1 of Tanaka discloses the semiconductor structure implements at least one of an inverter, a NAND gate, and a NOR gate [0041].
Regarding Claim 15
Tanaka discloses the first and second semiconductor structures are configured to implement at least one of an inverter, a NAND gate, and a NOR gate [0041].
Regarding Claim 16
FIG. 1 of Tanaka discloses a method of forming an integrated circuit (IC), comprising: forming first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance, the first centerline between the second and third centerlines; forming a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height and a first width that is an integer multiple of a unit width, a first semiconductor structure (FIG. 2) comprising at least one transistor and interconnections, the corresponding semiconductor structure, for each single-height logic cell in the first row, the first semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and forming a multi-height logic cell (WHSC1) over the semiconductor substrate and having a second height (height of WHSC1) that is greater than the first height, a second width that is at least the unit width.
Tanaka is silent with respect to “the multi-height logic cell including a first semiconductor structure configured to implement a first logic function and a second semiconductor structure configured to implement a second logic function separate from the first logic function, the first semiconductor structure located entirely between the first and second centerlines, and the second semiconductor structure extending between the second and third centerlines and over the first centerline”.
FIG. 2 of Park discloses a similar integrated circuit, wherein the multi-height logic cell (DHC) includes: a first semiconductor structure (NR2) located entirely between the first (VDD) and second (VSS) centerlines and configured to implement a first logic function; and a second semiconductor structure (PR1/2) extending between the second and third (CSS) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function [0007].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Park. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to improving reliability and performance ([0003] of Park).
Regarding Claim 17
FIG. 4 of Tanaka discloses the first semiconductor circuit structure and the second semiconductor circuit structure are configured to having different sizes. Maximum drive strength current is the capacity of a cell to drive a value to the cell connected to its output. Different sizes of std cells have different capacitance, smaller cells have small capacitance and vice versa. It is easier to drive a small cell than a large one. Therefore, Tanaka discloses the first semiconductor structure is configured to provide a first maximum drive current than is less than a second maximum drive current of the second semiconductor structure.
Regarding Claim 18
FIG. 1 of Tanaka discloses forming the multi-height logic cell to have the second height that is greater than the first height comprises forming the multi-height logic cell to have a second height that is an integer multiple of the single-height logic cells, in which the multiple is at least 2.
Regarding Claim 19
FIG. 2 of Park discloses a second logic function is different from the first logic function.
Regarding Claim 21
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; the first centerline between the second and third centerlines; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a rectangular multi-height logic cell (WHSC1) comprising a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure extending between the first semiconductor structure and the third centerline over the first centerline.
Tanaka is silent with respect to “a rectangular multi-height logic cell comprising a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure extending between the first semiconductor structure and the third centerline over the first centerline and configured to implement a second logic function separate from the first logic function”.
FIG. 2 of Park discloses a similar integrated circuit, wherein the multi-height logic cell (DHC) includes: a first semiconductor structure (NR2) located entirely between the first (VDD) and second (VSS) centerlines and configured to implement a first logic function; and a second semiconductor structure (PR1/2) extending between the second and third (CSS) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function [0007].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Park. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to improving reliability and performance ([0003] of Park).
Regarding Claim 22
FIG. 1 of Tanaka discloses the rectangular multi-height logic cell (WHSC1) has the second width over the first centerline and over the third centerline.
Regarding Claim 23
FIG. 2of Park discloses the rectangular multi-height logic cell (DHC) has a long axis extending between the first and third centerlines, and the first and second semiconductor structures are both centered with respect to the long axis.
Claim 24 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, in view of Park (U.S. Patent Pub. No. 2021/0384295), in view of Lin (CN 110828450, machine-translation provided).
Regarding Claim 24
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; the first centerline between the second and third centerlines; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a multi-height logic cell (WHSC1) arranged over the semiconductor substrate, wherein the multi-height logic cell has a second height that is greater than the first height and a second width.
Tanaka is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure “configured to implement a second logic function separate from the first logic function, the second logic function being one of an inverter, a NAND gate, or a NOR gate”.
FIG. 2 of Park discloses a similar integrated circuit, wherein the multi-height logic cell (DHC) includes: a first semiconductor structure (NR2) located entirely between the first (VDD) and second (VSS) centerlines and configured to implement a first logic function; and a second semiconductor structure (PR1/2) extending between the second and third (CSS) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function [0007].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Park. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to improving reliability and performance ([0003] of Park).
Tanaka as modified by Park is silent with respect to “the second logic function being one of an inverter, a NAND gate, or a NOR gate”.
FIG. 11 of Lin discloses a similar integrated circuit, wherein the second logic function being one of an inverter, a NAND gate, or a NOR gate [0061].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Lin. The ordinary artisan would have been motivated to modify Tanaka in the above manner for purpose of enabling the design and functioning of complex electronic systems.
Claim 24 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, in view of Park, in view of Park1 (U.S. Patent Pub. No. 2023/0136881).
Regarding Claim 24
FIG. 1 of Tanaka discloses an integrated circuit (IC), comprising: first (VDD), second (VSS) and third (VSS) power rails located over a semiconductor substrate, the first power rail configured to have a first polarity and the second and third power rails configured to have a different second polarity, and the first, second and third power rails located along corresponding first, second and third centerlines (horizontal central lines of VDD and VSS) spaced apart by a same distance; the first centerline between the second and third centerlines; a plurality of single-height logic cells (SHSC) arranged over the semiconductor substrate in first and second rows, the first row separated from the second row by the first centerline, each of the plurality of single-height logic cells including a first height, a first width that is an integer multiple of a unit width, and a corresponding semiconductor structure, wherein: for each single-height logic cell in the first row, the corresponding semiconductor structure is located entirely between the first and second centerlines, and for each single-height logic cell in the second row, the corresponding semiconductor structure is located entirely between the first and third centerlines; and a multi-height logic cell (WHSC1) arranged over the semiconductor substrate, wherein the multi-height logic cell has a second height that is greater than the first height and a second width.
Tanaka is silent with respect to “the multi-height logic cell includes: a first semiconductor structure located entirely between the first and second centerlines and configured to implement a first logic function; and a second semiconductor structure “configured to implement a second logic function separate from the first logic function, the second logic function being one of an inverter, a NAND gate, or a NOR gate”.
FIG. 2 of Park discloses a similar integrated circuit, wherein the multi-height logic cell (DHC) includes: a first semiconductor structure (NR2) located entirely between the first (VDD) and second (VSS) centerlines and configured to implement a first logic function; and a second semiconductor structure (PR1/2) extending between the second and third (CSS) centerlines over the first centerline and configured to implement a second logic function separate from the first logic function [0007].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Park. The ordinary artisan would have been motivated to modify Tanaka in the above manner in order to improving reliability and performance ([0003] of Park).
Tanaka as modified by Park is silent with respect to “the second logic function being one of an inverter, a NAND gate, or a NOR gate”.
FIG. 1 of Park1 discloses a similar integrated circuit, wherein the second logic function being one of an inverter, a NAND gate, or a NOR gate [0070].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Park1. The ordinary artisan would have been motivated to modify Tanaka in the above manner for purpose of enabling the design and functioning of complex electronic systems.
Pertinent Art
US 20070290270 discloses a first semiconductor circuit located entirely between the first and second power rails; and a second semiconductor circuit that extends over the first power rail, the first and second semiconductor circuits not sharing any signal path through the semiconductor substrate. US 20130313615 also discloses a first semiconductor circuit located entirely between the first and second power rails; and a second semiconductor circuit that extends over the first power rail, the first and second semiconductor circuits not sharing any signal path through the semiconductor substrate. US 20070141766 discloses a first semiconductor circuit located between the first and second centerlines, and a second semiconductor circuit located between the first and third centerlines, the first and second semiconductor circuits not sharing any signal path through the semiconductor substrate. Pertinent art also includes US 5903468, Kim (U.S. Patent Pub. No. 2009/0212327), Fabrice (EP 1104938), Won (CN 105448764).
Response to Arguments
Applicant’s arguments with respect to Claims 1, 12 and 21 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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