Prosecution Insights
Last updated: October 02, 2026
Application No. 17/514,984

CONDUCTIVE MEMBERS WITH UNOBSTRUCTED INTERFACIAL AREA FOR DIE ATTACH IN FLIP CHIP PACKAGES

Non-Final OA §103
Filed
Oct 29, 2021
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
7 (Non-Final)
67%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
379 granted / 568 resolved
-1.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
31 currently pending
Career history
600
Total Applications
across all art units

Statute-Specific Performance

§103
55.1%
+15.1% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 568 resolved cases

Office Action

§103
Attorney’s Docket Number: T100861US01 Filing Date: 10/29/2021 Inventors: Arias et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the amendment filed on 8/31/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 18, mailed on 5/29/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/31/2026 has been entered. Amendment Status The RCE submission filed on 8/31/2026 as an amendment in reply to the Office action in paper no.18 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-8, 10-24 and 26. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 7, 8, 12, 22, 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Komatsu (US 10,541,220) in view of Oh (US 2013/0012015) and Nguyen (US 2020/0173013). Regarding the claim 7, Komatsu (see, e.g., figs. 11 and 15) shows most aspects of the instant invention including a semiconductor package 1500 comprising: A semiconductor die 120 having a device side, A conductive layer 124 coupled to the device side, A conductive pillar 126 coupled to the conductive layer, A polyimide (PI) layer 128 coupled to the conductive layer and the pillar, A solder layer (SB) 130 coupled to the pillar, and A conductive terminal 1502 coupled to the solder layer wherein: The pillar 126 has upper and base portions, and The base portion 126 is coupled to the conductive layer 124 and The PI layer 128 touches a sidewall of the conductive layer 124 and a sidewall of the upper portion 126. Komatsu, however, fails to show the base portion having a decreasing width towards the upper portion and further fails to expressly show the PI layer having a base portion with a linear sidewall and an upper portion having a concave shape sidewall. Oh (see, e.g., fig. 1, ¶0018), in a similar package to Komatsu, teaches a conductive pillar 150 having a base portion 152 with a decreasing width toward the upper portion 151. Oh teaches that such a configuration relieves stresses applied to the conductive layer. Accordingly, it would have been obvious at the time of filing the invention to a person having ordinary skill in the art (PHOSITA) to modify the pillar of Komatsu in accordance with the teachings of Oh to relieve stresses in the package. With respect to the PI layer, Nguyen (see, e.g., fig. 8G) teaches a semiconductor package having a PI layer 810 surrounding a conductive pillar 807, wherein the PI layer has a base portion having a substantially linear sidewall and an upper portion having a concave-shaped sidewall. Nguyen, therefore, demonstrates that the claimed contour of the PI layer was a known structural configuration in semiconductor packages. The applicant’s own disclosure further evidences that such a PI-layer configuration was known in the art. In particular, fig. 1 is expressly identified by the applicant as a prior art flip-chip (see ¶0015) and depicts a PI/passivation layer 107 having substantially the same general configuration, including substantially linear sidewalls in a lower portion and a curved/concave sidewall in an upper portion. Thus, the particular contour of the PI layer was not unique to the disclosed pillar configurations. Moreover, the instant specification does not identify any particular functional significance or unexpected result attributable to the PI layer having a base portion with a linear sidewall and an upper portion with a concave-shape sidewall. Rather, the specification attributes the improvements in the package to the interfacial area between the solder and the conductive pillar. ¶0021 additionally explains that the PI layer is applied after formation of the conductive pillar and that the shape of the pillar causes the PI layer to flow off the pillar. Thus, the specification itself indicates that the resulting configuration of the PI layer is influenced by the underlying pillar geometry and the process used to form the PI layer. Accordingly, it would have been obvious to PHOSITA to form the PI layer of the Komatsu/Oh package with the known sidewall configuration taught by Nguyen. Such modification would have amounted to the use of a known structural configuration in a similar semiconductor package using known fabrication techniques, with the resulting PI contour being a predictable result of the pillar geometry and formation of the PI layer. PHOSITA would have had a reasonable expectation of success in forming the PI layer with the configuration taught by Nguyen, particularly because the applicant’s own prior-art Fig. 1 demonstrates that such a PI-layer configuration was already known. Regarding claim 8, Komatsu (see, e.g., col.4/l.4) teaches that the pillar 126 comprises copper. Regarding claim 12, Komatsu (see, e.g., fig. 15) shows that the terminal is a portion of a lead frame 1502. Regarding claim 22, Komatsu (see, e.g., fig. 15) shows the package 1500 further comprising a mold compound 1504 covering the die 120, the conductive layer 124, the pillar 126, the PI layer 128, the SB 130 and the terminal 1502. Regarding claim 24, Komatsu (see, e.g., col.3/l.62) shows that the conductive layer 124 comprises a seed layer. Regarding claim 26, Oh (see, e.g., fig. 1) shows that the height of the base portion 152 of the pillar 150 is smaller than the height of the upper portion 151. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Komatsu/Oh/Nguyen in view of Mallari (US 2020/0211990). Regarding claim 10, Komatsu fails to show that the top surface of the pillar has a convex shape. Mallari (see, e.g., par. 0035) teaches that a convex shape results in yield improvement during packaging and improves reliability during usage. Accordingly, it would have been obvious at the time of filing the invention to a PHOSITA to have the top surface of the pillar of Komatsu with the convex shape of Mallari to improve yield and reliability. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Komatsu/Oh/Nguyen and Fujii (US 2020/0144211). Regarding claim 11, Komatsu (see, e.g., fig. 11) teaches a semiconductor package including a pillar 126 and a PI layer 128, wherein the pillar has a top surface exposed from the PI layer. However, Komatsu does not expressly teach that the top surface of the pillar 126 extends farther away from the device side of the die than the PI layer 128. Nguyen (see, e.g., fig. 8D) teaches a similar package configuration in which the pillar 807 extends farther away from the device side of the die 802 than the PI layer 810. Fujii (see, e.g., par. 0089) teaches that exposing a side surface of the upper portion 222 of the pillar so that the solder layer 30 contacts the side surface, increases the contact area between the solder layer and the pillar, thereby reducing current density in the solder layer and suppressing electromigration. It would have been obvious to a PHOSITA at the time of filing the invention to modify Komatsu’s pillar in view of Nguyen and Fujii such that the pillar extends farther away from the device side of the die than the PI layer. Nguyen demonstrates that such a pillar was known in the art, and Fujii provides an express technical motivation for the modification, namely, to expose the side surface of the pillar to increase solder contact area and improve reliability by reducing current density and suppressing electromigration. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Komatsu/Oh/Nguyen in view of Fujii and Pendse (US 2012/0223428). Regarding claim 21, Komatsu (see, e.g., fig. 11) shows the pillar 126 having an upper portion with straight, vertical sidewalls. The claim, however, recites that the upper portion has an increased width away from the base portion of the pillar, i.e., the upper portion flares outward. Komatsu fails to show the claimed flared upper portion. Fujii, however, shows a conductive pillar 222 having an upper portion that increases in width away from the base, a flared/tapered upper portion. Fujii further teaches that the upper portion of the pillar increases the contact area with an overlying solder layer 30, thereby reducing current density and suppressing electromigration (see, e.g., Fujii: par.0089 and fig.18). Accordingly, it would have been obvious at the time of filing the invention to a PHOSITA seeking to reduce current density and improve electromigration performance to modify the straight-walled pillars of Komatsu to include the upper portion of Fujii in order to increase the solder contact area and reduce current density. This modification would have been made with a reasonable expectation of success because the effect, reducing current density, is a predictable physical result of increasing the contact area between the upper portion of the pillar and the solder layer. Pendse further discloses that the conductive pillars may assume a variety of shapes, straight (see, e.g., fig. 9f), tapered wider-at-top (see, e.g., fig. 10e), tapered wider-at-bottom (see, e.g., fig. 11f), thereby, teaching that the artisan would have recognized tapered/flared pillar shapes as conventional and readily selectable alternatives to the straight sidewall pillars of Komatsu. Accordingly, the claimed upper portion with an increasing width, absent any criticality, is only considered to be an obvious modification of the upper portion of Komatsu. This is also in accordance with the courts, which have held that a change in shape or configuration, without any criticality, is within the level of skill in the art. In any event, Pendse and Fujii both show that pillars having upper portions with increasing widths are used and known in the art. Pendse and Fujii are evidence that the particular shape claimed by the applicant is nothing more than one of numerous shapes that a PHOSITA would have found obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Dailey, 149 USPQ 47 (CCPA1976). Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Komatsu/Oh/Nguyen in view of Mishra (US 2020/0035633). Regarding claim 23, Komatsu (see, e.g., fig. 15) teaches that the conductive terminal 1502 is a lead frame in a semiconductor package 1500, but does not disclose that the lead frame is copper; Mishra (see, e.g., par. 0026), in a similar package, expressly teaches a copper lead frame. It would have been obvious to a PHOSITA at the time of filing the invention to modify Komatsu’s lead frame to be copper, as taught by Mishra, because this is the selection of a known material based on its suitability for its intended use, and the result of such a substitution would have been predictable. MPEP§2143 recognizes “simple substitution of one known element for another to obtain predictable results” and MPEP§2144.07 specifically identifies selection of a known material for its intended purpose as a proper obviousness rationale; KSR likewise explains that combining familiar elements according to known methods is obvious when it yields predictable results. Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection. Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp September 10, 2026
Read full office action

Prosecution Timeline

Show 9 earlier events
Jan 08, 2026
Request for Continued Examination
Jan 24, 2026
Response after Non-Final Action
Feb 05, 2026
Non-Final Rejection mailed — §103
May 05, 2026
Response Filed
May 29, 2026
Final Rejection mailed — §103
Aug 31, 2026
Request for Continued Examination
Sep 04, 2026
Response after Non-Final Action
Sep 14, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
67%
Grant Probability
81%
With Interview (+14.3%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 568 resolved cases by this examiner. Grant probability derived from career allowance rate.

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