Prosecution Insights
Last updated: April 19, 2026
Application No. 17/514,984

CONDUCTIVE MEMBERS WITH UNOBSTRUCTED INTERFACIAL AREA FOR DIE ATTACH IN FLIP CHIP PACKAGES

Non-Final OA §103
Filed
Oct 29, 2021
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
5 (Non-Final)
66%
Grant Probability
Favorable
5-6
OA Rounds
3y 8m
To Grant
80%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
358 granted / 546 resolved
-2.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
40 currently pending
Career history
586
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§103
Attorney’s Docket Number: T100861US01 Filing Date: 10/29/2021 Inventors: Arias et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the amendment filed on 1/8/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 13, mailed on 10/8/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/8/2026 has been entered. Amendment Status The RCE submission filed on 1/8/2026 as an amendment in reply to the Office action in paper no.13 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-8 and 10-25. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 7, 8, 10-12 and 22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Mallari (US 2020/0211990) in view of Kuo (US 2012/0040524). Regarding claim 7, Mallari (see, e.g., figs. 3A) shows most aspects of the instant invention including a semiconductor package comprising: A semiconductor die 302 having a device side A conductive layer 306 coupled to the device side A conductive pillar 318/310 coupled to the conductive layer A polyimide (PI) layer 304 coupled to the conductive layer and the pillar A solder layer 312 coupled to the pillar A conductive terminal 641 coupled to the solder layer wherein: The pillar 318/310 has upper and base portions The base portion is coupled to the conductive layer 306 The PI layer 304 touches a sidewall of the conductive layer The device side faces the conductive terminal 641 Mallari, however, fails to show the base portion having a decreasing width towards the upper portion. Kuo (see, e.g., par.0022/ll.21-27), in a similar package to Mallari, teaches the that a decreasing width would lower the thermal stress of the package. Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the pillar of Kuo in the package of Fujii to lower the thermal stress of the package. Regarding claim 8, Mallari (see, e.g., par.0026/ll.8-9) teaches that the pillar comprises copper. Regarding claim 10, Mallari (see, e.g., par. 0035) teaches that the top surface of the pillar has a convex shape. Regarding claim 11, Mallari (see, e.g., fig. 3A) shows that the upper surface of the pillar 310 extends farther away from the device side than the PI layer 304. Regarding claim 12, Mallari (see, e.g., fig. 6F) shows that the terminal is a portion of a lead frame 640. Regarding claim 22, Mallari (see, e.g., fig. 6F) shows the package further comprising a mold compound 652 covering the die 602, the conductive layer, the pillar, the polymer layer, the solder layer and the terminal 640. Regarding claim 24, Mallari (see, e.g., fig. 3A) shows that the conductive layer comprises a seed layer 306. Claims 7, 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra (US 2020/0035633) in view of Kuo. Regarding claim 7, Mishra (see, e.g., fig. 1A) shows most aspects of the instant invention including a semiconductor package 100 comprising: A semiconductor die 202 having a device side A conductive layer 104 coupled to the device side A conductive pillar 110/108 coupled to the conductive layer A polyimide (PI) layer 106 coupled to the conductive layer and the pillar A solder layer 114 coupled to the pillar A conductive terminal 116 coupled to the solder layer wherein: The pillar 110/108 has upper and base portions The base portion is coupled to the conductive layer 104 The PI layer 106 touches a sidewall of the conductive layer 104 The device side faces the conductive terminal 116 Mishra, however, fails to show the base portion having a decreasing width towards the upper portion. See also the comments above in paragraphs 9 and 10 with respect to claim 1, which are considered repeated here. Regarding claim 23, Mishra (see, e.g., par. 0026) shows that the terminal 116 comprises copper. Regarding claim 25, Mishra (see, e.g., fig. 1A) shows that the PI layer 106 has curved sidewalls. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Mallari/Kuo in view of Fujii (US 2020/0144211) and Pendse (US 2012/0223428). Regarding claim 21, Mallari/Kuo shows the pillar having an upper portion with straight, vertical sidewalls in the upper portion. The claim, however, recites that the upper portion has an increased width away from the base portion of the pillar, i.e., the upper portion flares outward. Mallari/Kuo fail to show the claimed flared upper portion. Fujii, however, shows a conductive pillar 222 having an upper portion that increases in width away from the base, a flared/tapered upper portion. Fujii further teaches that shaping the end surface of the upper portion to produce a protruding shape increases the contact area with an overlying solder layer 30 thereby reducing current density and suppressing electromigration (see, e.g., Fujii: par.0089 and fig.18). Accordingly, it would have been obvious at the time of filing the invention to a person of ordinary skill in the art seeking to reduce current density and improve electromigration performance to modify the straight-walled pillars of Mallari/Kuo to include the flared upper portion of Fujii in order to increase solder contact area and reduce current density. This modification would have been made with a reasonable expectation of success because the effect, increased contact area reducing current density, is a predictable physical result of increasing the pillar end contact area. Pendse further discloses that the conductive pillars may assume a variety of shapes, straight (see, e.g., fig. 9f), tapered wider-at-top (see, e.g., fig. 10e), tapered wider-at-bottom (see, e.g., fig. 11f), thereby, teaching that the artisan would have recognized tapered/flared pillar shapes as conventional and readily selectable alternatives to the straight sidewall pillars of Millar/Kuo. Accordingly, the claimed upper portion with an increasing width, absent any criticality, is only considered to be an obvious modification of the upper portion of Millar/Kuo. This is also in accordance with the courts, which have held that a change in shape or configuration, without any criticality is within the level of skill in the art. In any event, Pendse and Fujii both show that pillars having upper portions with increasing widths are used and known in the art. Pendse and Fujii are evidence that the particular shape claimed by the applicant is nothing more than one of numerous shapes that a person having ordinary skill in the art would have found obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Dailey, 149 USPQ 47 (CCPA1976). Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection. Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp February 3, 2026
Read full office action

Prosecution Timeline

Oct 29, 2021
Application Filed
Mar 06, 2024
Non-Final Rejection — §103
May 29, 2024
Response Filed
Aug 15, 2024
Final Rejection — §103
Jan 21, 2025
Request for Continued Examination
Jan 27, 2025
Response after Non-Final Action
May 02, 2025
Non-Final Rejection — §103
Jul 31, 2025
Response Filed
Oct 06, 2025
Final Rejection — §103
Jan 08, 2026
Request for Continued Examination
Jan 24, 2026
Response after Non-Final Action
Feb 04, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
66%
Grant Probability
80%
With Interview (+14.8%)
3y 8m
Median Time to Grant
High
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allow rate.

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